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[SPARC64]: Use in-kernel OBP device tree for PCI controller probing.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_psycho.c
1 /* $Id: pci_psycho.c,v 1.33 2002/02/01 00:58:33 davem Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
15
16 #include <asm/pbm.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/starfire.h>
20 #include <asm/prom.h>
21
22 #include "pci_impl.h"
23 #include "iommu_common.h"
24
25 /* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29 #define psycho_read(__reg) \
30 ({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36 })
37 #define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44 /* Misc. PSYCHO PCI controller register offsets and definitions. */
45 #define PSYCHO_CONTROL 0x0010UL
46 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55 #define PSYCHO_PCIA_CTRL 0x2000UL
56 #define PSYCHO_PCIB_CTRL 0x4000UL
57 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69
70 /* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78 #define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89 {
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95 }
96
97 static int psycho_out_of_range(struct pci_pbm_info *pbm,
98 unsigned char bus,
99 unsigned char devfn)
100 {
101 return ((pbm->parent == 0) ||
102 ((pbm == &pbm->parent->pbm_B) &&
103 (bus == pbm->pci_first_busno) &&
104 PCI_SLOT(devfn) > 8) ||
105 ((pbm == &pbm->parent->pbm_A) &&
106 (bus == pbm->pci_first_busno) &&
107 PCI_SLOT(devfn) > 8));
108 }
109
110 /* PSYCHO PCI configuration space accessors. */
111
112 static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
113 int where, int size, u32 *value)
114 {
115 struct pci_pbm_info *pbm = bus_dev->sysdata;
116 unsigned char bus = bus_dev->number;
117 u32 *addr;
118 u16 tmp16;
119 u8 tmp8;
120
121 switch (size) {
122 case 1:
123 *value = 0xff;
124 break;
125 case 2:
126 *value = 0xffff;
127 break;
128 case 4:
129 *value = 0xffffffff;
130 break;
131 }
132
133 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
134 if (!addr)
135 return PCIBIOS_SUCCESSFUL;
136
137 if (psycho_out_of_range(pbm, bus, devfn))
138 return PCIBIOS_SUCCESSFUL;
139 switch (size) {
140 case 1:
141 pci_config_read8((u8 *)addr, &tmp8);
142 *value = (u32) tmp8;
143 break;
144
145 case 2:
146 if (where & 0x01) {
147 printk("pci_read_config_word: misaligned reg [%x]\n",
148 where);
149 return PCIBIOS_SUCCESSFUL;
150 }
151 pci_config_read16((u16 *)addr, &tmp16);
152 *value = (u32) tmp16;
153 break;
154
155 case 4:
156 if (where & 0x03) {
157 printk("pci_read_config_dword: misaligned reg [%x]\n",
158 where);
159 return PCIBIOS_SUCCESSFUL;
160 }
161 pci_config_read32(addr, value);
162 break;
163 }
164 return PCIBIOS_SUCCESSFUL;
165 }
166
167 static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
168 int where, int size, u32 value)
169 {
170 struct pci_pbm_info *pbm = bus_dev->sysdata;
171 unsigned char bus = bus_dev->number;
172 u32 *addr;
173
174 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
175 if (!addr)
176 return PCIBIOS_SUCCESSFUL;
177
178 if (psycho_out_of_range(pbm, bus, devfn))
179 return PCIBIOS_SUCCESSFUL;
180
181 switch (size) {
182 case 1:
183 pci_config_write8((u8 *)addr, value);
184 break;
185
186 case 2:
187 if (where & 0x01) {
188 printk("pci_write_config_word: misaligned reg [%x]\n",
189 where);
190 return PCIBIOS_SUCCESSFUL;
191 }
192 pci_config_write16((u16 *)addr, value);
193 break;
194
195 case 4:
196 if (where & 0x03) {
197 printk("pci_write_config_dword: misaligned reg [%x]\n",
198 where);
199 return PCIBIOS_SUCCESSFUL;
200 }
201 pci_config_write32(addr, value);
202 }
203 return PCIBIOS_SUCCESSFUL;
204 }
205
206 static struct pci_ops psycho_ops = {
207 .read = psycho_read_pci_cfg,
208 .write = psycho_write_pci_cfg,
209 };
210
211 /* PSYCHO interrupt mapping support. */
212 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
213 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
214 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
215 {
216 unsigned int bus = (ino & 0x10) >> 4;
217 unsigned int slot = (ino & 0x0c) >> 2;
218
219 if (bus == 0)
220 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
221 else
222 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
223 }
224
225 #define PSYCHO_IMAP_SCSI 0x1000UL
226 #define PSYCHO_IMAP_ETH 0x1008UL
227 #define PSYCHO_IMAP_BPP 0x1010UL
228 #define PSYCHO_IMAP_AU_REC 0x1018UL
229 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
230 #define PSYCHO_IMAP_PFAIL 0x1028UL
231 #define PSYCHO_IMAP_KMS 0x1030UL
232 #define PSYCHO_IMAP_FLPY 0x1038UL
233 #define PSYCHO_IMAP_SHW 0x1040UL
234 #define PSYCHO_IMAP_KBD 0x1048UL
235 #define PSYCHO_IMAP_MS 0x1050UL
236 #define PSYCHO_IMAP_SER 0x1058UL
237 #define PSYCHO_IMAP_TIM0 0x1060UL
238 #define PSYCHO_IMAP_TIM1 0x1068UL
239 #define PSYCHO_IMAP_UE 0x1070UL
240 #define PSYCHO_IMAP_CE 0x1078UL
241 #define PSYCHO_IMAP_A_ERR 0x1080UL
242 #define PSYCHO_IMAP_B_ERR 0x1088UL
243 #define PSYCHO_IMAP_PMGMT 0x1090UL
244 #define PSYCHO_IMAP_GFX 0x1098UL
245 #define PSYCHO_IMAP_EUPA 0x10a0UL
246
247 static unsigned long __onboard_imap_off[] = {
248 /*0x20*/ PSYCHO_IMAP_SCSI,
249 /*0x21*/ PSYCHO_IMAP_ETH,
250 /*0x22*/ PSYCHO_IMAP_BPP,
251 /*0x23*/ PSYCHO_IMAP_AU_REC,
252 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
253 /*0x25*/ PSYCHO_IMAP_PFAIL,
254 /*0x26*/ PSYCHO_IMAP_KMS,
255 /*0x27*/ PSYCHO_IMAP_FLPY,
256 /*0x28*/ PSYCHO_IMAP_SHW,
257 /*0x29*/ PSYCHO_IMAP_KBD,
258 /*0x2a*/ PSYCHO_IMAP_MS,
259 /*0x2b*/ PSYCHO_IMAP_SER,
260 /*0x2c*/ PSYCHO_IMAP_TIM0,
261 /*0x2d*/ PSYCHO_IMAP_TIM1,
262 /*0x2e*/ PSYCHO_IMAP_UE,
263 /*0x2f*/ PSYCHO_IMAP_CE,
264 /*0x30*/ PSYCHO_IMAP_A_ERR,
265 /*0x31*/ PSYCHO_IMAP_B_ERR,
266 /*0x32*/ PSYCHO_IMAP_PMGMT
267 };
268 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
269 #define PSYCHO_ONBOARD_IRQ_LAST 0x32
270 #define psycho_onboard_imap_offset(__ino) \
271 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
272
273 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
274 #define PSYCHO_ICLR_SCSI 0x1800UL
275
276 #define psycho_iclr_offset(ino) \
277 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
278 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
279
280 static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
281 struct pci_dev *pdev,
282 unsigned int ino)
283 {
284 unsigned long imap, iclr;
285 unsigned long imap_off, iclr_off;
286 int inofixup = 0;
287
288 ino &= PCI_IRQ_INO;
289 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
290 /* PCI slot */
291 imap_off = psycho_pcislot_imap_offset(ino);
292 } else {
293 /* Onboard device */
294 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
295 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
296 prom_halt();
297 }
298 imap_off = psycho_onboard_imap_offset(ino);
299 }
300
301 /* Now build the IRQ bucket. */
302 imap = pbm->controller_regs + imap_off;
303 imap += 4;
304
305 iclr_off = psycho_iclr_offset(ino);
306 iclr = pbm->controller_regs + iclr_off;
307 iclr += 4;
308
309 if ((ino & 0x20) == 0)
310 inofixup = ino & 0x03;
311
312 return build_irq(inofixup, iclr, imap);
313 }
314
315 /* PSYCHO error handling support. */
316 enum psycho_error_type {
317 UE_ERR, CE_ERR, PCI_ERR
318 };
319
320 /* Helper function of IOMMU error checking, which checks out
321 * the state of the streaming buffers. The IOMMU lock is
322 * held when this is called.
323 *
324 * For the PCI error case we know which PBM (and thus which
325 * streaming buffer) caused the error, but for the uncorrectable
326 * error case we do not. So we always check both streaming caches.
327 */
328 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
329 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
330 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
331 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
332 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
333 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
334 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
335 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
336 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
337 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
338 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
339 #define PSYCHO_STC_DATA_A 0xb000UL
340 #define PSYCHO_STC_DATA_B 0xc000UL
341 #define PSYCHO_STC_ERR_A 0xb400UL
342 #define PSYCHO_STC_ERR_B 0xc400UL
343 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
344 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
345 #define PSYCHO_STC_TAG_A 0xb800UL
346 #define PSYCHO_STC_TAG_B 0xc800UL
347 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
348 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
349 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
350 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
351 #define PSYCHO_STC_LINE_A 0xb900UL
352 #define PSYCHO_STC_LINE_B 0xc900UL
353 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
354 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
355 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
356 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
357 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
358 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
359
360 static DEFINE_SPINLOCK(stc_buf_lock);
361 static unsigned long stc_error_buf[128];
362 static unsigned long stc_tag_buf[16];
363 static unsigned long stc_line_buf[16];
364
365 static void __psycho_check_one_stc(struct pci_controller_info *p,
366 struct pci_pbm_info *pbm,
367 int is_pbm_a)
368 {
369 struct pci_strbuf *strbuf = &pbm->stc;
370 unsigned long regbase = p->pbm_A.controller_regs;
371 unsigned long err_base, tag_base, line_base;
372 u64 control;
373 int i;
374
375 if (is_pbm_a) {
376 err_base = regbase + PSYCHO_STC_ERR_A;
377 tag_base = regbase + PSYCHO_STC_TAG_A;
378 line_base = regbase + PSYCHO_STC_LINE_A;
379 } else {
380 err_base = regbase + PSYCHO_STC_ERR_B;
381 tag_base = regbase + PSYCHO_STC_TAG_B;
382 line_base = regbase + PSYCHO_STC_LINE_B;
383 }
384
385 spin_lock(&stc_buf_lock);
386
387 /* This is __REALLY__ dangerous. When we put the
388 * streaming buffer into diagnostic mode to probe
389 * it's tags and error status, we _must_ clear all
390 * of the line tag valid bits before re-enabling
391 * the streaming buffer. If any dirty data lives
392 * in the STC when we do this, we will end up
393 * invalidating it before it has a chance to reach
394 * main memory.
395 */
396 control = psycho_read(strbuf->strbuf_control);
397 psycho_write(strbuf->strbuf_control,
398 (control | PSYCHO_STRBUF_CTRL_DENAB));
399 for (i = 0; i < 128; i++) {
400 unsigned long val;
401
402 val = psycho_read(err_base + (i * 8UL));
403 psycho_write(err_base + (i * 8UL), 0UL);
404 stc_error_buf[i] = val;
405 }
406 for (i = 0; i < 16; i++) {
407 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
408 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
409 psycho_write(tag_base + (i * 8UL), 0UL);
410 psycho_write(line_base + (i * 8UL), 0UL);
411 }
412
413 /* OK, state is logged, exit diagnostic mode. */
414 psycho_write(strbuf->strbuf_control, control);
415
416 for (i = 0; i < 16; i++) {
417 int j, saw_error, first, last;
418
419 saw_error = 0;
420 first = i * 8;
421 last = first + 8;
422 for (j = first; j < last; j++) {
423 unsigned long errval = stc_error_buf[j];
424 if (errval != 0) {
425 saw_error++;
426 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
427 p->index,
428 (is_pbm_a ? 'A' : 'B'),
429 j,
430 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
431 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
432 }
433 }
434 if (saw_error != 0) {
435 unsigned long tagval = stc_tag_buf[i];
436 unsigned long lineval = stc_line_buf[i];
437 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
438 p->index,
439 (is_pbm_a ? 'A' : 'B'),
440 i,
441 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
442 (tagval & PSYCHO_STCTAG_VPN),
443 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
444 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
445 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
446 "V(%d)FOFN(%d)]\n",
447 p->index,
448 (is_pbm_a ? 'A' : 'B'),
449 i,
450 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
451 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
452 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
453 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
454 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
455 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
456 }
457 }
458
459 spin_unlock(&stc_buf_lock);
460 }
461
462 static void __psycho_check_stc_error(struct pci_controller_info *p,
463 unsigned long afsr,
464 unsigned long afar,
465 enum psycho_error_type type)
466 {
467 struct pci_pbm_info *pbm;
468
469 pbm = &p->pbm_A;
470 if (pbm->stc.strbuf_enabled)
471 __psycho_check_one_stc(p, pbm, 1);
472
473 pbm = &p->pbm_B;
474 if (pbm->stc.strbuf_enabled)
475 __psycho_check_one_stc(p, pbm, 0);
476 }
477
478 /* When an Uncorrectable Error or a PCI Error happens, we
479 * interrogate the IOMMU state to see if it is the cause.
480 */
481 #define PSYCHO_IOMMU_CONTROL 0x0200UL
482 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
483 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
484 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
485 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
486 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
487 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
488 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
489 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
490 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
491 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
492 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
493 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
494 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
495 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
496 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
497 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
498 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
499 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
500 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
501 #define PSYCHO_IOMMU_FLUSH 0x0210UL
502 #define PSYCHO_IOMMU_TAG 0xa580UL
503 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
504 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
505 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
506 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
507 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
508 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
509 #define PSYCHO_IOMMU_DATA 0xa600UL
510 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
511 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
512 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
513 static void psycho_check_iommu_error(struct pci_controller_info *p,
514 unsigned long afsr,
515 unsigned long afar,
516 enum psycho_error_type type)
517 {
518 struct pci_iommu *iommu = p->pbm_A.iommu;
519 unsigned long iommu_tag[16];
520 unsigned long iommu_data[16];
521 unsigned long flags;
522 u64 control;
523 int i;
524
525 spin_lock_irqsave(&iommu->lock, flags);
526 control = psycho_read(iommu->iommu_control);
527 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
528 char *type_string;
529
530 /* Clear the error encountered bit. */
531 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
532 psycho_write(iommu->iommu_control, control);
533
534 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
535 case 0:
536 type_string = "Protection Error";
537 break;
538 case 1:
539 type_string = "Invalid Error";
540 break;
541 case 2:
542 type_string = "TimeOut Error";
543 break;
544 case 3:
545 default:
546 type_string = "ECC Error";
547 break;
548 };
549 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
550 p->index, type_string);
551
552 /* Put the IOMMU into diagnostic mode and probe
553 * it's TLB for entries with error status.
554 *
555 * It is very possible for another DVMA to occur
556 * while we do this probe, and corrupt the system
557 * further. But we are so screwed at this point
558 * that we are likely to crash hard anyways, so
559 * get as much diagnostic information to the
560 * console as we can.
561 */
562 psycho_write(iommu->iommu_control,
563 control | PSYCHO_IOMMU_CTRL_DENAB);
564 for (i = 0; i < 16; i++) {
565 unsigned long base = p->pbm_A.controller_regs;
566
567 iommu_tag[i] =
568 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
569 iommu_data[i] =
570 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
571
572 /* Now clear out the entry. */
573 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
574 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
575 }
576
577 /* Leave diagnostic mode. */
578 psycho_write(iommu->iommu_control, control);
579
580 for (i = 0; i < 16; i++) {
581 unsigned long tag, data;
582
583 tag = iommu_tag[i];
584 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
585 continue;
586
587 data = iommu_data[i];
588 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
589 case 0:
590 type_string = "Protection Error";
591 break;
592 case 1:
593 type_string = "Invalid Error";
594 break;
595 case 2:
596 type_string = "TimeOut Error";
597 break;
598 case 3:
599 default:
600 type_string = "ECC Error";
601 break;
602 };
603 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
604 p->index, i, type_string,
605 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
606 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
607 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
608 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
609 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
610 p->index, i,
611 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
612 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
613 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
614 }
615 }
616 __psycho_check_stc_error(p, afsr, afar, type);
617 spin_unlock_irqrestore(&iommu->lock, flags);
618 }
619
620 /* Uncorrectable Errors. Cause of the error and the address are
621 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
622 * relating to UPA interface transactions.
623 */
624 #define PSYCHO_UE_AFSR 0x0030UL
625 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
626 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
627 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
628 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
629 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
630 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
631 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
632 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
633 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
634 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
635 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
636 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
637 #define PSYCHO_UE_AFAR 0x0038UL
638
639 static irqreturn_t psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
640 {
641 struct pci_controller_info *p = dev_id;
642 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
643 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
644 unsigned long afsr, afar, error_bits;
645 int reported;
646
647 /* Latch uncorrectable error status. */
648 afar = psycho_read(afar_reg);
649 afsr = psycho_read(afsr_reg);
650
651 /* Clear the primary/secondary error status bits. */
652 error_bits = afsr &
653 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
654 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
655 if (!error_bits)
656 return IRQ_NONE;
657 psycho_write(afsr_reg, error_bits);
658
659 /* Log the error. */
660 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
661 p->index,
662 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
663 "PIO" :
664 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
665 "DMA Read" :
666 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
667 "DMA Write" : "???")))));
668 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
669 p->index,
670 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
671 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
672 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
673 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
674 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
675 printk("PSYCHO%d: UE Secondary errors [", p->index);
676 reported = 0;
677 if (afsr & PSYCHO_UEAFSR_SPIO) {
678 reported++;
679 printk("(PIO)");
680 }
681 if (afsr & PSYCHO_UEAFSR_SDRD) {
682 reported++;
683 printk("(DMA Read)");
684 }
685 if (afsr & PSYCHO_UEAFSR_SDWR) {
686 reported++;
687 printk("(DMA Write)");
688 }
689 if (!reported)
690 printk("(none)");
691 printk("]\n");
692
693 /* Interrogate IOMMU for error status. */
694 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
695
696 return IRQ_HANDLED;
697 }
698
699 /* Correctable Errors. */
700 #define PSYCHO_CE_AFSR 0x0040UL
701 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
702 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
703 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
704 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
705 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
706 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
707 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
708 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
709 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
710 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
711 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
712 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
713 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
714 #define PSYCHO_CE_AFAR 0x0040UL
715
716 static irqreturn_t psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
717 {
718 struct pci_controller_info *p = dev_id;
719 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
720 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
721 unsigned long afsr, afar, error_bits;
722 int reported;
723
724 /* Latch error status. */
725 afar = psycho_read(afar_reg);
726 afsr = psycho_read(afsr_reg);
727
728 /* Clear primary/secondary error status bits. */
729 error_bits = afsr &
730 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
731 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
732 if (!error_bits)
733 return IRQ_NONE;
734 psycho_write(afsr_reg, error_bits);
735
736 /* Log the error. */
737 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
738 p->index,
739 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
740 "PIO" :
741 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
742 "DMA Read" :
743 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
744 "DMA Write" : "???")))));
745
746 /* XXX Use syndrome and afar to print out module string just like
747 * XXX UDB CE trap handler does... -DaveM
748 */
749 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
750 "UPA_MID[%02lx] was_block(%d)\n",
751 p->index,
752 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
753 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
754 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
755 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
756 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
757 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
758 printk("PSYCHO%d: CE Secondary errors [", p->index);
759 reported = 0;
760 if (afsr & PSYCHO_CEAFSR_SPIO) {
761 reported++;
762 printk("(PIO)");
763 }
764 if (afsr & PSYCHO_CEAFSR_SDRD) {
765 reported++;
766 printk("(DMA Read)");
767 }
768 if (afsr & PSYCHO_CEAFSR_SDWR) {
769 reported++;
770 printk("(DMA Write)");
771 }
772 if (!reported)
773 printk("(none)");
774 printk("]\n");
775
776 return IRQ_HANDLED;
777 }
778
779 /* PCI Errors. They are signalled by the PCI bus module since they
780 * are associated with a specific bus segment.
781 */
782 #define PSYCHO_PCI_AFSR_A 0x2010UL
783 #define PSYCHO_PCI_AFSR_B 0x4010UL
784 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
785 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
786 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
787 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
788 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
789 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
790 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
791 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
792 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
793 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
794 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
795 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
796 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
797 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
798 #define PSYCHO_PCI_AFAR_A 0x2018UL
799 #define PSYCHO_PCI_AFAR_B 0x4018UL
800
801 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
802 {
803 unsigned long csr_reg, csr, csr_error_bits;
804 irqreturn_t ret = IRQ_NONE;
805 u16 stat;
806
807 if (is_pbm_a) {
808 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
809 } else {
810 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
811 }
812 csr = psycho_read(csr_reg);
813 csr_error_bits =
814 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
815 if (csr_error_bits) {
816 /* Clear the errors. */
817 psycho_write(csr_reg, csr);
818
819 /* Log 'em. */
820 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
821 printk("%s: PCI streaming byte hole error asserted.\n",
822 pbm->name);
823 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
824 printk("%s: PCI SERR signal asserted.\n", pbm->name);
825 ret = IRQ_HANDLED;
826 }
827 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
828 if (stat & (PCI_STATUS_PARITY |
829 PCI_STATUS_SIG_TARGET_ABORT |
830 PCI_STATUS_REC_TARGET_ABORT |
831 PCI_STATUS_REC_MASTER_ABORT |
832 PCI_STATUS_SIG_SYSTEM_ERROR)) {
833 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
834 pbm->name, stat);
835 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
836 ret = IRQ_HANDLED;
837 }
838 return ret;
839 }
840
841 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
842 {
843 struct pci_pbm_info *pbm = dev_id;
844 struct pci_controller_info *p = pbm->parent;
845 unsigned long afsr_reg, afar_reg;
846 unsigned long afsr, afar, error_bits;
847 int is_pbm_a, reported;
848
849 is_pbm_a = (pbm == &pbm->parent->pbm_A);
850 if (is_pbm_a) {
851 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
852 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
853 } else {
854 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
855 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
856 }
857
858 /* Latch error status. */
859 afar = psycho_read(afar_reg);
860 afsr = psycho_read(afsr_reg);
861
862 /* Clear primary/secondary error status bits. */
863 error_bits = afsr &
864 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
865 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
866 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
867 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
868 if (!error_bits)
869 return psycho_pcierr_intr_other(pbm, is_pbm_a);
870 psycho_write(afsr_reg, error_bits);
871
872 /* Log the error. */
873 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
874 p->index, (is_pbm_a ? 'A' : 'B'),
875 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
876 "Master Abort" :
877 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
878 "Target Abort" :
879 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
880 "Excessive Retries" :
881 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
882 "Parity Error" : "???"))))));
883 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
884 p->index, (is_pbm_a ? 'A' : 'B'),
885 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
886 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
887 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
888 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
889 p->index, (is_pbm_a ? 'A' : 'B'), afar);
890 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
891 p->index, (is_pbm_a ? 'A' : 'B'));
892 reported = 0;
893 if (afsr & PSYCHO_PCIAFSR_SMA) {
894 reported++;
895 printk("(Master Abort)");
896 }
897 if (afsr & PSYCHO_PCIAFSR_STA) {
898 reported++;
899 printk("(Target Abort)");
900 }
901 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
902 reported++;
903 printk("(Excessive Retries)");
904 }
905 if (afsr & PSYCHO_PCIAFSR_SPERR) {
906 reported++;
907 printk("(Parity Error)");
908 }
909 if (!reported)
910 printk("(none)");
911 printk("]\n");
912
913 /* For the error types shown, scan PBM's PCI bus for devices
914 * which have logged that error type.
915 */
916
917 /* If we see a Target Abort, this could be the result of an
918 * IOMMU translation error of some sort. It is extremely
919 * useful to log this information as usually it indicates
920 * a bug in the IOMMU support code or a PCI device driver.
921 */
922 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
923 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
924 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
925 }
926 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
927 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
928
929 /* For excessive retries, PSYCHO/PBM will abort the device
930 * and there is no way to specifically check for excessive
931 * retries in the config space status registers. So what
932 * we hope is that we'll catch it via the master/target
933 * abort events.
934 */
935
936 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
937 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
938
939 return IRQ_HANDLED;
940 }
941
942 /* XXX What about PowerFail/PowerManagement??? -DaveM */
943 #define PSYCHO_ECC_CTRL 0x0020
944 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
945 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
946 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
947 #define PSYCHO_UE_INO 0x2e
948 #define PSYCHO_CE_INO 0x2f
949 #define PSYCHO_PCIERR_A_INO 0x30
950 #define PSYCHO_PCIERR_B_INO 0x31
951 static void psycho_register_error_handlers(struct pci_controller_info *p)
952 {
953 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
954 unsigned long base = p->pbm_A.controller_regs;
955 unsigned int irq, portid = pbm->portid;
956 u64 tmp;
957
958 /* Build IRQs and register handlers. */
959 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_UE_INO);
960 if (request_irq(irq, psycho_ue_intr,
961 SA_SHIRQ, "PSYCHO UE", p) < 0) {
962 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
963 p->index);
964 prom_halt();
965 }
966
967 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_CE_INO);
968 if (request_irq(irq, psycho_ce_intr,
969 SA_SHIRQ, "PSYCHO CE", p) < 0) {
970 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n",
971 p->index);
972 prom_halt();
973 }
974
975 pbm = &p->pbm_A;
976 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO);
977 if (request_irq(irq, psycho_pcierr_intr,
978 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) {
979 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
980 p->index);
981 prom_halt();
982 }
983
984 pbm = &p->pbm_B;
985 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO);
986 if (request_irq(irq, psycho_pcierr_intr,
987 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) {
988 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n",
989 p->index);
990 prom_halt();
991 }
992
993 /* Enable UE and CE interrupts for controller. */
994 psycho_write(base + PSYCHO_ECC_CTRL,
995 (PSYCHO_ECCCTRL_EE |
996 PSYCHO_ECCCTRL_UE |
997 PSYCHO_ECCCTRL_CE));
998
999 /* Enable PCI Error interrupts and clear error
1000 * bits for each PBM.
1001 */
1002 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
1003 tmp |= (PSYCHO_PCICTRL_SERR |
1004 PSYCHO_PCICTRL_SBH_ERR |
1005 PSYCHO_PCICTRL_EEN);
1006 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1007 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
1008
1009 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
1010 tmp |= (PSYCHO_PCICTRL_SERR |
1011 PSYCHO_PCICTRL_SBH_ERR |
1012 PSYCHO_PCICTRL_EEN);
1013 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1014 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
1015 }
1016
1017 /* PSYCHO boot time probing and initialization. */
1018 static void psycho_resource_adjust(struct pci_dev *pdev,
1019 struct resource *res,
1020 struct resource *root)
1021 {
1022 res->start += root->start;
1023 res->end += root->start;
1024 }
1025
1026 static void psycho_base_address_update(struct pci_dev *pdev, int resource)
1027 {
1028 struct pcidev_cookie *pcp = pdev->sysdata;
1029 struct pci_pbm_info *pbm = pcp->pbm;
1030 struct resource *res, *root;
1031 u32 reg;
1032 int where, size, is_64bit;
1033
1034 res = &pdev->resource[resource];
1035 if (resource < 6) {
1036 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1037 } else if (resource == PCI_ROM_RESOURCE) {
1038 where = pdev->rom_base_reg;
1039 } else {
1040 /* Somebody might have asked allocation of a non-standard resource */
1041 return;
1042 }
1043
1044 is_64bit = 0;
1045 if (res->flags & IORESOURCE_IO)
1046 root = &pbm->io_space;
1047 else {
1048 root = &pbm->mem_space;
1049 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1050 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1051 is_64bit = 1;
1052 }
1053
1054 size = res->end - res->start;
1055 pci_read_config_dword(pdev, where, &reg);
1056 reg = ((reg & size) |
1057 (((u32)(res->start - root->start)) & ~size));
1058 if (resource == PCI_ROM_RESOURCE) {
1059 reg |= PCI_ROM_ADDRESS_ENABLE;
1060 res->flags |= IORESOURCE_ROM_ENABLE;
1061 }
1062 pci_write_config_dword(pdev, where, reg);
1063
1064 /* This knows that the upper 32-bits of the address
1065 * must be zero. Our PCI common layer enforces this.
1066 */
1067 if (is_64bit)
1068 pci_write_config_dword(pdev, where + 4, 0);
1069 }
1070
1071 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1072 {
1073 u8 *addr;
1074
1075 /* Set cache-line size to 64 bytes, this is actually
1076 * a nop but I do it for completeness.
1077 */
1078 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1079 0, PCI_CACHE_LINE_SIZE);
1080 pci_config_write8(addr, 64 / sizeof(u32));
1081
1082 /* Set PBM latency timer to 64 PCI clocks. */
1083 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1084 0, PCI_LATENCY_TIMER);
1085 pci_config_write8(addr, 64);
1086 }
1087
1088 static void pbm_scan_bus(struct pci_controller_info *p,
1089 struct pci_pbm_info *pbm)
1090 {
1091 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1092
1093 if (!cookie) {
1094 prom_printf("PSYCHO: Critical allocation failure.\n");
1095 prom_halt();
1096 }
1097
1098 /* All we care about is the PBM. */
1099 cookie->pbm = pbm;
1100
1101 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1102 p->pci_ops,
1103 pbm);
1104 pci_fixup_host_bridge_self(pbm->pci_bus);
1105 pbm->pci_bus->self->sysdata = cookie;
1106
1107 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node->node);
1108 pci_record_assignments(pbm, pbm->pci_bus);
1109 pci_assign_unassigned(pbm, pbm->pci_bus);
1110 pci_fixup_irq(pbm, pbm->pci_bus);
1111 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1112 pci_setup_busmastering(pbm, pbm->pci_bus);
1113 }
1114
1115 static void psycho_scan_bus(struct pci_controller_info *p)
1116 {
1117 pbm_config_busmastering(&p->pbm_B);
1118 p->pbm_B.is_66mhz_capable = 0;
1119 pbm_config_busmastering(&p->pbm_A);
1120 p->pbm_A.is_66mhz_capable = 1;
1121 pbm_scan_bus(p, &p->pbm_B);
1122 pbm_scan_bus(p, &p->pbm_A);
1123
1124 /* After the PCI bus scan is complete, we can register
1125 * the error interrupt handlers.
1126 */
1127 psycho_register_error_handlers(p);
1128 }
1129
1130 static void psycho_iommu_init(struct pci_controller_info *p)
1131 {
1132 struct pci_iommu *iommu = p->pbm_A.iommu;
1133 unsigned long i;
1134 u64 control;
1135
1136 /* Register addresses. */
1137 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
1138 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
1139 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
1140 /* PSYCHO's IOMMU lacks ctx flushing. */
1141 iommu->iommu_ctxflush = 0;
1142
1143 /* We use the main control register of PSYCHO as the write
1144 * completion register.
1145 */
1146 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
1147
1148 /*
1149 * Invalidate TLB Entries.
1150 */
1151 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1152 control |= PSYCHO_IOMMU_CTRL_DENAB;
1153 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1154 for(i = 0; i < 16; i++) {
1155 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
1156 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1157 }
1158
1159 /* Leave diag mode enabled for full-flushing done
1160 * in pci_iommu.c
1161 */
1162 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1163
1164 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
1165 __pa(iommu->page_table));
1166
1167 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1168 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
1169 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
1170 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1171
1172 /* If necessary, hook us up for starfire IRQ translations. */
1173 if (this_is_starfire)
1174 p->starfire_cookie = starfire_hookup(p->pbm_A.portid);
1175 else
1176 p->starfire_cookie = NULL;
1177 }
1178
1179 #define PSYCHO_IRQ_RETRY 0x1a00UL
1180 #define PSYCHO_PCIA_DIAG 0x2020UL
1181 #define PSYCHO_PCIB_DIAG 0x4020UL
1182 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
1183 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
1184 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
1185 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
1186 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
1187 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
1188 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
1189 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1190
1191 static void psycho_controller_hwinit(struct pci_controller_info *p)
1192 {
1193 u64 tmp;
1194
1195 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1196
1197 /* Enable arbiter for all PCI slots. */
1198 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1199 tmp |= PSYCHO_PCICTRL_AEN;
1200 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1201
1202 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1203 tmp |= PSYCHO_PCICTRL_AEN;
1204 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1205
1206 /* Disable DMA write / PIO read synchronization on
1207 * both PCI bus segments.
1208 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1209 */
1210 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1211 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1212 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1213
1214 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1215 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1216 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1217 }
1218
1219 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1220 struct pci_pbm_info *pbm)
1221 {
1222 char *name = pbm->name;
1223
1224 sprintf(name, "PSYCHO%d PBM%c",
1225 p->index,
1226 (pbm == &p->pbm_A ? 'A' : 'B'));
1227 pbm->io_space.name = pbm->mem_space.name = name;
1228
1229 request_resource(&ioport_resource, &pbm->io_space);
1230 request_resource(&iomem_resource, &pbm->mem_space);
1231 pci_register_legacy_regions(&pbm->io_space,
1232 &pbm->mem_space);
1233 }
1234
1235 static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1236 struct pci_pbm_info *pbm,
1237 int is_pbm_a)
1238 {
1239 unsigned long base = pbm->controller_regs;
1240 u64 control;
1241
1242 if (is_pbm_a) {
1243 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1244 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1245 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1246 } else {
1247 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1248 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1249 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1250 }
1251 /* PSYCHO's streaming buffer lacks ctx flushing. */
1252 pbm->stc.strbuf_ctxflush = 0;
1253 pbm->stc.strbuf_ctxmatch_base = 0;
1254
1255 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1256 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1257 + 63UL)
1258 & ~63UL);
1259 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1260 __pa(pbm->stc.strbuf_flushflag);
1261
1262 /* Enable the streaming buffer. We have to be careful
1263 * just in case OBP left it with LRU locking enabled.
1264 *
1265 * It is possible to control if PBM will be rerun on
1266 * line misses. Currently I just retain whatever setting
1267 * OBP left us with. All checks so far show it having
1268 * a value of zero.
1269 */
1270 #undef PSYCHO_STRBUF_RERUN_ENABLE
1271 #undef PSYCHO_STRBUF_RERUN_DISABLE
1272 control = psycho_read(pbm->stc.strbuf_control);
1273 control |= PSYCHO_STRBUF_CTRL_ENAB;
1274 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1275 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1276 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1277 #else
1278 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1279 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1280 #endif
1281 #endif
1282 psycho_write(pbm->stc.strbuf_control, control);
1283
1284 pbm->stc.strbuf_enabled = 1;
1285 }
1286
1287 #define PSYCHO_IOSPACE_A 0x002000000UL
1288 #define PSYCHO_IOSPACE_B 0x002010000UL
1289 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1290 #define PSYCHO_MEMSPACE_A 0x100000000UL
1291 #define PSYCHO_MEMSPACE_B 0x180000000UL
1292 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1293
1294 static void psycho_pbm_init(struct pci_controller_info *p,
1295 struct device_node *dp, int is_pbm_a)
1296 {
1297 unsigned int *busrange;
1298 struct property *prop;
1299 struct pci_pbm_info *pbm;
1300 int len;
1301
1302 if (is_pbm_a) {
1303 pbm = &p->pbm_A;
1304 pbm->pci_first_slot = 1;
1305 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_A;
1306 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_A;
1307 } else {
1308 pbm = &p->pbm_B;
1309 pbm->pci_first_slot = 2;
1310 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_B;
1311 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_B;
1312 }
1313
1314 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1315 pbm->chip_version = 0;
1316 prop = of_find_property(dp, "version#", NULL);
1317 if (prop)
1318 pbm->chip_version = *(int *) prop->value;
1319 pbm->chip_revision = 0;
1320 prop = of_find_property(dp, "module-revision#", NULL);
1321 if (prop)
1322 pbm->chip_revision = *(int *) prop->value;
1323
1324 pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE;
1325 pbm->io_space.flags = IORESOURCE_IO;
1326 pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE;
1327 pbm->mem_space.flags = IORESOURCE_MEM;
1328 pbm_register_toplevel_resources(p, pbm);
1329
1330 pbm->parent = p;
1331 pbm->prom_node = dp;
1332 pbm->name = dp->full_name;
1333
1334 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1335 pbm->name,
1336 pbm->chip_version, pbm->chip_revision);
1337
1338 prop = of_find_property(dp, "ranges", &len);
1339 if (prop) {
1340 pbm->pbm_ranges = prop->value;
1341 pbm->num_pbm_ranges =
1342 (len / sizeof(struct linux_prom_pci_ranges));
1343 } else {
1344 pbm->num_pbm_ranges = 0;
1345 }
1346
1347 prop = of_find_property(dp, "interrupt-map", &len);
1348 if (prop) {
1349 pbm->pbm_intmap = prop->value;
1350 pbm->num_pbm_intmap =
1351 (len / sizeof(struct linux_prom_pci_intmap));
1352
1353 prop = of_find_property(dp, "interrupt-map-mask", NULL);
1354 pbm->pbm_intmask = prop->value;
1355 } else {
1356 pbm->num_pbm_intmap = 0;
1357 }
1358
1359 prop = of_find_property(dp, "bus-range", NULL);
1360 busrange = prop->value;
1361 pbm->pci_first_busno = busrange[0];
1362 pbm->pci_last_busno = busrange[1];
1363
1364 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1365 }
1366
1367 #define PSYCHO_CONFIGSPACE 0x001000000UL
1368
1369 void psycho_init(struct device_node *dp, char *model_name)
1370 {
1371 struct linux_prom64_registers *pr_regs;
1372 struct pci_controller_info *p;
1373 struct pci_iommu *iommu;
1374 struct property *prop;
1375 u32 upa_portid;
1376 int is_pbm_a;
1377
1378 upa_portid = 0xff;
1379 prop = of_find_property(dp, "upa-portid", NULL);
1380 if (prop)
1381 upa_portid = *(u32 *) prop->value;
1382
1383 for(p = pci_controller_root; p; p = p->next) {
1384 if (p->pbm_A.portid == upa_portid) {
1385 is_pbm_a = (p->pbm_A.prom_node == NULL);
1386 psycho_pbm_init(p, dp, is_pbm_a);
1387 return;
1388 }
1389 }
1390
1391 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1392 if (!p) {
1393 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1394 prom_halt();
1395 }
1396 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1397 if (!iommu) {
1398 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1399 prom_halt();
1400 }
1401 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1402
1403 p->next = pci_controller_root;
1404 pci_controller_root = p;
1405
1406 p->pbm_A.portid = upa_portid;
1407 p->pbm_B.portid = upa_portid;
1408 p->index = pci_num_controllers++;
1409 p->pbms_same_domain = 0;
1410 p->scan_bus = psycho_scan_bus;
1411 p->irq_build = psycho_irq_build;
1412 p->base_address_update = psycho_base_address_update;
1413 p->resource_adjust = psycho_resource_adjust;
1414 p->pci_ops = &psycho_ops;
1415
1416 prop = of_find_property(dp, "reg", NULL);
1417 pr_regs = prop->value;
1418
1419 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1420 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1421
1422 p->pbm_A.config_space = p->pbm_B.config_space =
1423 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1424
1425 /*
1426 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1427 * we need to adjust our MEM space mask.
1428 */
1429 pci_memspace_mask = 0x7fffffffUL;
1430
1431 psycho_controller_hwinit(p);
1432
1433 psycho_iommu_init(p);
1434
1435 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1436 psycho_pbm_init(p, dp, is_pbm_a);
1437 }
Linux kernel - Deliverables
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