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Merge branch 'upstream' of git://electric-eye.fr.zoreil.com/home/romieu/linux-2.6...
[deliverable/linux.git] / arch / sparc64 / kernel / pci_psycho.c
1 /* $Id: pci_psycho.c,v 1.33 2002/02/01 00:58:33 davem Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
15
16 #include <asm/pbm.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/starfire.h>
20
21 #include "pci_impl.h"
22 #include "iommu_common.h"
23
24 /* All PSYCHO registers are 64-bits. The following accessor
25 * routines are how they are accessed. The REG parameter
26 * is a physical address.
27 */
28 #define psycho_read(__reg) \
29 ({ u64 __ret; \
30 __asm__ __volatile__("ldxa [%1] %2, %0" \
31 : "=r" (__ret) \
32 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
33 : "memory"); \
34 __ret; \
35 })
36 #define psycho_write(__reg, __val) \
37 __asm__ __volatile__("stxa %0, [%1] %2" \
38 : /* no outputs */ \
39 : "r" (__val), "r" (__reg), \
40 "i" (ASI_PHYS_BYPASS_EC_E) \
41 : "memory")
42
43 /* Misc. PSYCHO PCI controller register offsets and definitions. */
44 #define PSYCHO_CONTROL 0x0010UL
45 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
46 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
47 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
48 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
49 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
50 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
51 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
52 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
53 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
54 #define PSYCHO_PCIA_CTRL 0x2000UL
55 #define PSYCHO_PCIB_CTRL 0x4000UL
56 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
57 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
58 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
59 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
60 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
61 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
62 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
63 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
64 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
65 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
66 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
67 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
68
69 /* U2P Programmer's Manual, page 13-55, configuration space
70 * address format:
71 *
72 * 32 24 23 16 15 11 10 8 7 2 1 0
73 * ---------------------------------------------------------
74 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
75 * ---------------------------------------------------------
76 */
77 #define PSYCHO_CONFIG_BASE(PBM) \
78 ((PBM)->config_space | (1UL << 24))
79 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
80 (((unsigned long)(BUS) << 16) | \
81 ((unsigned long)(DEVFN) << 8) | \
82 ((unsigned long)(REG)))
83
84 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
85 unsigned char bus,
86 unsigned int devfn,
87 int where)
88 {
89 if (!pbm)
90 return NULL;
91 return (void *)
92 (PSYCHO_CONFIG_BASE(pbm) |
93 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
94 }
95
96 static int psycho_out_of_range(struct pci_pbm_info *pbm,
97 unsigned char bus,
98 unsigned char devfn)
99 {
100 return ((pbm->parent == 0) ||
101 ((pbm == &pbm->parent->pbm_B) &&
102 (bus == pbm->pci_first_busno) &&
103 PCI_SLOT(devfn) > 8) ||
104 ((pbm == &pbm->parent->pbm_A) &&
105 (bus == pbm->pci_first_busno) &&
106 PCI_SLOT(devfn) > 8));
107 }
108
109 /* PSYCHO PCI configuration space accessors. */
110
111 static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
112 int where, int size, u32 *value)
113 {
114 struct pci_pbm_info *pbm = bus_dev->sysdata;
115 unsigned char bus = bus_dev->number;
116 u32 *addr;
117 u16 tmp16;
118 u8 tmp8;
119
120 switch (size) {
121 case 1:
122 *value = 0xff;
123 break;
124 case 2:
125 *value = 0xffff;
126 break;
127 case 4:
128 *value = 0xffffffff;
129 break;
130 }
131
132 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
133 if (!addr)
134 return PCIBIOS_SUCCESSFUL;
135
136 if (psycho_out_of_range(pbm, bus, devfn))
137 return PCIBIOS_SUCCESSFUL;
138 switch (size) {
139 case 1:
140 pci_config_read8((u8 *)addr, &tmp8);
141 *value = (u32) tmp8;
142 break;
143
144 case 2:
145 if (where & 0x01) {
146 printk("pci_read_config_word: misaligned reg [%x]\n",
147 where);
148 return PCIBIOS_SUCCESSFUL;
149 }
150 pci_config_read16((u16 *)addr, &tmp16);
151 *value = (u32) tmp16;
152 break;
153
154 case 4:
155 if (where & 0x03) {
156 printk("pci_read_config_dword: misaligned reg [%x]\n",
157 where);
158 return PCIBIOS_SUCCESSFUL;
159 }
160 pci_config_read32(addr, value);
161 break;
162 }
163 return PCIBIOS_SUCCESSFUL;
164 }
165
166 static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
167 int where, int size, u32 value)
168 {
169 struct pci_pbm_info *pbm = bus_dev->sysdata;
170 unsigned char bus = bus_dev->number;
171 u32 *addr;
172
173 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
174 if (!addr)
175 return PCIBIOS_SUCCESSFUL;
176
177 if (psycho_out_of_range(pbm, bus, devfn))
178 return PCIBIOS_SUCCESSFUL;
179
180 switch (size) {
181 case 1:
182 pci_config_write8((u8 *)addr, value);
183 break;
184
185 case 2:
186 if (where & 0x01) {
187 printk("pci_write_config_word: misaligned reg [%x]\n",
188 where);
189 return PCIBIOS_SUCCESSFUL;
190 }
191 pci_config_write16((u16 *)addr, value);
192 break;
193
194 case 4:
195 if (where & 0x03) {
196 printk("pci_write_config_dword: misaligned reg [%x]\n",
197 where);
198 return PCIBIOS_SUCCESSFUL;
199 }
200 pci_config_write32(addr, value);
201 }
202 return PCIBIOS_SUCCESSFUL;
203 }
204
205 static struct pci_ops psycho_ops = {
206 .read = psycho_read_pci_cfg,
207 .write = psycho_write_pci_cfg,
208 };
209
210 /* PSYCHO interrupt mapping support. */
211 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
212 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
213 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
214 {
215 unsigned int bus = (ino & 0x10) >> 4;
216 unsigned int slot = (ino & 0x0c) >> 2;
217
218 if (bus == 0)
219 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
220 else
221 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
222 }
223
224 #define PSYCHO_IMAP_SCSI 0x1000UL
225 #define PSYCHO_IMAP_ETH 0x1008UL
226 #define PSYCHO_IMAP_BPP 0x1010UL
227 #define PSYCHO_IMAP_AU_REC 0x1018UL
228 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
229 #define PSYCHO_IMAP_PFAIL 0x1028UL
230 #define PSYCHO_IMAP_KMS 0x1030UL
231 #define PSYCHO_IMAP_FLPY 0x1038UL
232 #define PSYCHO_IMAP_SHW 0x1040UL
233 #define PSYCHO_IMAP_KBD 0x1048UL
234 #define PSYCHO_IMAP_MS 0x1050UL
235 #define PSYCHO_IMAP_SER 0x1058UL
236 #define PSYCHO_IMAP_TIM0 0x1060UL
237 #define PSYCHO_IMAP_TIM1 0x1068UL
238 #define PSYCHO_IMAP_UE 0x1070UL
239 #define PSYCHO_IMAP_CE 0x1078UL
240 #define PSYCHO_IMAP_A_ERR 0x1080UL
241 #define PSYCHO_IMAP_B_ERR 0x1088UL
242 #define PSYCHO_IMAP_PMGMT 0x1090UL
243 #define PSYCHO_IMAP_GFX 0x1098UL
244 #define PSYCHO_IMAP_EUPA 0x10a0UL
245
246 static unsigned long __onboard_imap_off[] = {
247 /*0x20*/ PSYCHO_IMAP_SCSI,
248 /*0x21*/ PSYCHO_IMAP_ETH,
249 /*0x22*/ PSYCHO_IMAP_BPP,
250 /*0x23*/ PSYCHO_IMAP_AU_REC,
251 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
252 /*0x25*/ PSYCHO_IMAP_PFAIL,
253 /*0x26*/ PSYCHO_IMAP_KMS,
254 /*0x27*/ PSYCHO_IMAP_FLPY,
255 /*0x28*/ PSYCHO_IMAP_SHW,
256 /*0x29*/ PSYCHO_IMAP_KBD,
257 /*0x2a*/ PSYCHO_IMAP_MS,
258 /*0x2b*/ PSYCHO_IMAP_SER,
259 /*0x2c*/ PSYCHO_IMAP_TIM0,
260 /*0x2d*/ PSYCHO_IMAP_TIM1,
261 /*0x2e*/ PSYCHO_IMAP_UE,
262 /*0x2f*/ PSYCHO_IMAP_CE,
263 /*0x30*/ PSYCHO_IMAP_A_ERR,
264 /*0x31*/ PSYCHO_IMAP_B_ERR,
265 /*0x32*/ PSYCHO_IMAP_PMGMT
266 };
267 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
268 #define PSYCHO_ONBOARD_IRQ_LAST 0x32
269 #define psycho_onboard_imap_offset(__ino) \
270 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
271
272 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
273 #define PSYCHO_ICLR_SCSI 0x1800UL
274
275 #define psycho_iclr_offset(ino) \
276 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
277 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
278
279 static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
280 struct pci_dev *pdev,
281 unsigned int ino)
282 {
283 unsigned long imap, iclr;
284 unsigned long imap_off, iclr_off;
285 int inofixup = 0;
286
287 ino &= PCI_IRQ_INO;
288 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
289 /* PCI slot */
290 imap_off = psycho_pcislot_imap_offset(ino);
291 } else {
292 /* Onboard device */
293 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
294 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
295 prom_halt();
296 }
297 imap_off = psycho_onboard_imap_offset(ino);
298 }
299
300 /* Now build the IRQ bucket. */
301 imap = pbm->controller_regs + imap_off;
302 imap += 4;
303
304 iclr_off = psycho_iclr_offset(ino);
305 iclr = pbm->controller_regs + iclr_off;
306 iclr += 4;
307
308 if ((ino & 0x20) == 0)
309 inofixup = ino & 0x03;
310
311 return build_irq(inofixup, iclr, imap);
312 }
313
314 /* PSYCHO error handling support. */
315 enum psycho_error_type {
316 UE_ERR, CE_ERR, PCI_ERR
317 };
318
319 /* Helper function of IOMMU error checking, which checks out
320 * the state of the streaming buffers. The IOMMU lock is
321 * held when this is called.
322 *
323 * For the PCI error case we know which PBM (and thus which
324 * streaming buffer) caused the error, but for the uncorrectable
325 * error case we do not. So we always check both streaming caches.
326 */
327 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
328 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
329 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
330 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
331 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
332 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
333 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
334 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
335 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
336 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
337 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
338 #define PSYCHO_STC_DATA_A 0xb000UL
339 #define PSYCHO_STC_DATA_B 0xc000UL
340 #define PSYCHO_STC_ERR_A 0xb400UL
341 #define PSYCHO_STC_ERR_B 0xc400UL
342 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
343 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
344 #define PSYCHO_STC_TAG_A 0xb800UL
345 #define PSYCHO_STC_TAG_B 0xc800UL
346 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
347 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
348 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
349 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
350 #define PSYCHO_STC_LINE_A 0xb900UL
351 #define PSYCHO_STC_LINE_B 0xc900UL
352 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
353 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
354 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
355 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
356 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
357 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
358
359 static DEFINE_SPINLOCK(stc_buf_lock);
360 static unsigned long stc_error_buf[128];
361 static unsigned long stc_tag_buf[16];
362 static unsigned long stc_line_buf[16];
363
364 static void __psycho_check_one_stc(struct pci_controller_info *p,
365 struct pci_pbm_info *pbm,
366 int is_pbm_a)
367 {
368 struct pci_strbuf *strbuf = &pbm->stc;
369 unsigned long regbase = p->pbm_A.controller_regs;
370 unsigned long err_base, tag_base, line_base;
371 u64 control;
372 int i;
373
374 if (is_pbm_a) {
375 err_base = regbase + PSYCHO_STC_ERR_A;
376 tag_base = regbase + PSYCHO_STC_TAG_A;
377 line_base = regbase + PSYCHO_STC_LINE_A;
378 } else {
379 err_base = regbase + PSYCHO_STC_ERR_B;
380 tag_base = regbase + PSYCHO_STC_TAG_B;
381 line_base = regbase + PSYCHO_STC_LINE_B;
382 }
383
384 spin_lock(&stc_buf_lock);
385
386 /* This is __REALLY__ dangerous. When we put the
387 * streaming buffer into diagnostic mode to probe
388 * it's tags and error status, we _must_ clear all
389 * of the line tag valid bits before re-enabling
390 * the streaming buffer. If any dirty data lives
391 * in the STC when we do this, we will end up
392 * invalidating it before it has a chance to reach
393 * main memory.
394 */
395 control = psycho_read(strbuf->strbuf_control);
396 psycho_write(strbuf->strbuf_control,
397 (control | PSYCHO_STRBUF_CTRL_DENAB));
398 for (i = 0; i < 128; i++) {
399 unsigned long val;
400
401 val = psycho_read(err_base + (i * 8UL));
402 psycho_write(err_base + (i * 8UL), 0UL);
403 stc_error_buf[i] = val;
404 }
405 for (i = 0; i < 16; i++) {
406 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
407 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
408 psycho_write(tag_base + (i * 8UL), 0UL);
409 psycho_write(line_base + (i * 8UL), 0UL);
410 }
411
412 /* OK, state is logged, exit diagnostic mode. */
413 psycho_write(strbuf->strbuf_control, control);
414
415 for (i = 0; i < 16; i++) {
416 int j, saw_error, first, last;
417
418 saw_error = 0;
419 first = i * 8;
420 last = first + 8;
421 for (j = first; j < last; j++) {
422 unsigned long errval = stc_error_buf[j];
423 if (errval != 0) {
424 saw_error++;
425 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
426 p->index,
427 (is_pbm_a ? 'A' : 'B'),
428 j,
429 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
430 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
431 }
432 }
433 if (saw_error != 0) {
434 unsigned long tagval = stc_tag_buf[i];
435 unsigned long lineval = stc_line_buf[i];
436 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
437 p->index,
438 (is_pbm_a ? 'A' : 'B'),
439 i,
440 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
441 (tagval & PSYCHO_STCTAG_VPN),
442 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
443 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
444 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
445 "V(%d)FOFN(%d)]\n",
446 p->index,
447 (is_pbm_a ? 'A' : 'B'),
448 i,
449 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
450 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
451 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
452 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
453 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
454 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
455 }
456 }
457
458 spin_unlock(&stc_buf_lock);
459 }
460
461 static void __psycho_check_stc_error(struct pci_controller_info *p,
462 unsigned long afsr,
463 unsigned long afar,
464 enum psycho_error_type type)
465 {
466 struct pci_pbm_info *pbm;
467
468 pbm = &p->pbm_A;
469 if (pbm->stc.strbuf_enabled)
470 __psycho_check_one_stc(p, pbm, 1);
471
472 pbm = &p->pbm_B;
473 if (pbm->stc.strbuf_enabled)
474 __psycho_check_one_stc(p, pbm, 0);
475 }
476
477 /* When an Uncorrectable Error or a PCI Error happens, we
478 * interrogate the IOMMU state to see if it is the cause.
479 */
480 #define PSYCHO_IOMMU_CONTROL 0x0200UL
481 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
482 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
483 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
484 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
485 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
486 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
487 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
488 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
489 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
490 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
491 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
492 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
493 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
494 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
495 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
496 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
497 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
498 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
499 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
500 #define PSYCHO_IOMMU_FLUSH 0x0210UL
501 #define PSYCHO_IOMMU_TAG 0xa580UL
502 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
503 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
504 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
505 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
506 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
507 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
508 #define PSYCHO_IOMMU_DATA 0xa600UL
509 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
510 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
511 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
512 static void psycho_check_iommu_error(struct pci_controller_info *p,
513 unsigned long afsr,
514 unsigned long afar,
515 enum psycho_error_type type)
516 {
517 struct pci_iommu *iommu = p->pbm_A.iommu;
518 unsigned long iommu_tag[16];
519 unsigned long iommu_data[16];
520 unsigned long flags;
521 u64 control;
522 int i;
523
524 spin_lock_irqsave(&iommu->lock, flags);
525 control = psycho_read(iommu->iommu_control);
526 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
527 char *type_string;
528
529 /* Clear the error encountered bit. */
530 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
531 psycho_write(iommu->iommu_control, control);
532
533 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
534 case 0:
535 type_string = "Protection Error";
536 break;
537 case 1:
538 type_string = "Invalid Error";
539 break;
540 case 2:
541 type_string = "TimeOut Error";
542 break;
543 case 3:
544 default:
545 type_string = "ECC Error";
546 break;
547 };
548 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
549 p->index, type_string);
550
551 /* Put the IOMMU into diagnostic mode and probe
552 * it's TLB for entries with error status.
553 *
554 * It is very possible for another DVMA to occur
555 * while we do this probe, and corrupt the system
556 * further. But we are so screwed at this point
557 * that we are likely to crash hard anyways, so
558 * get as much diagnostic information to the
559 * console as we can.
560 */
561 psycho_write(iommu->iommu_control,
562 control | PSYCHO_IOMMU_CTRL_DENAB);
563 for (i = 0; i < 16; i++) {
564 unsigned long base = p->pbm_A.controller_regs;
565
566 iommu_tag[i] =
567 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
568 iommu_data[i] =
569 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
570
571 /* Now clear out the entry. */
572 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
573 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
574 }
575
576 /* Leave diagnostic mode. */
577 psycho_write(iommu->iommu_control, control);
578
579 for (i = 0; i < 16; i++) {
580 unsigned long tag, data;
581
582 tag = iommu_tag[i];
583 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
584 continue;
585
586 data = iommu_data[i];
587 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
588 case 0:
589 type_string = "Protection Error";
590 break;
591 case 1:
592 type_string = "Invalid Error";
593 break;
594 case 2:
595 type_string = "TimeOut Error";
596 break;
597 case 3:
598 default:
599 type_string = "ECC Error";
600 break;
601 };
602 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
603 p->index, i, type_string,
604 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
605 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
606 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
607 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
608 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
609 p->index, i,
610 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
611 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
612 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
613 }
614 }
615 __psycho_check_stc_error(p, afsr, afar, type);
616 spin_unlock_irqrestore(&iommu->lock, flags);
617 }
618
619 /* Uncorrectable Errors. Cause of the error and the address are
620 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
621 * relating to UPA interface transactions.
622 */
623 #define PSYCHO_UE_AFSR 0x0030UL
624 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
625 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
626 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
627 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
628 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
629 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
630 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
631 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
632 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
633 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
634 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
635 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
636 #define PSYCHO_UE_AFAR 0x0038UL
637
638 static irqreturn_t psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
639 {
640 struct pci_controller_info *p = dev_id;
641 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
642 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
643 unsigned long afsr, afar, error_bits;
644 int reported;
645
646 /* Latch uncorrectable error status. */
647 afar = psycho_read(afar_reg);
648 afsr = psycho_read(afsr_reg);
649
650 /* Clear the primary/secondary error status bits. */
651 error_bits = afsr &
652 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
653 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
654 if (!error_bits)
655 return IRQ_NONE;
656 psycho_write(afsr_reg, error_bits);
657
658 /* Log the error. */
659 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
660 p->index,
661 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
662 "PIO" :
663 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
664 "DMA Read" :
665 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
666 "DMA Write" : "???")))));
667 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
668 p->index,
669 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
670 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
671 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
672 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
673 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
674 printk("PSYCHO%d: UE Secondary errors [", p->index);
675 reported = 0;
676 if (afsr & PSYCHO_UEAFSR_SPIO) {
677 reported++;
678 printk("(PIO)");
679 }
680 if (afsr & PSYCHO_UEAFSR_SDRD) {
681 reported++;
682 printk("(DMA Read)");
683 }
684 if (afsr & PSYCHO_UEAFSR_SDWR) {
685 reported++;
686 printk("(DMA Write)");
687 }
688 if (!reported)
689 printk("(none)");
690 printk("]\n");
691
692 /* Interrogate IOMMU for error status. */
693 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
694
695 return IRQ_HANDLED;
696 }
697
698 /* Correctable Errors. */
699 #define PSYCHO_CE_AFSR 0x0040UL
700 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
701 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
702 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
703 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
704 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
705 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
706 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
707 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
708 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
709 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
710 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
711 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
712 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
713 #define PSYCHO_CE_AFAR 0x0040UL
714
715 static irqreturn_t psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
716 {
717 struct pci_controller_info *p = dev_id;
718 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
719 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
720 unsigned long afsr, afar, error_bits;
721 int reported;
722
723 /* Latch error status. */
724 afar = psycho_read(afar_reg);
725 afsr = psycho_read(afsr_reg);
726
727 /* Clear primary/secondary error status bits. */
728 error_bits = afsr &
729 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
730 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
731 if (!error_bits)
732 return IRQ_NONE;
733 psycho_write(afsr_reg, error_bits);
734
735 /* Log the error. */
736 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
737 p->index,
738 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
739 "PIO" :
740 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
741 "DMA Read" :
742 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
743 "DMA Write" : "???")))));
744
745 /* XXX Use syndrome and afar to print out module string just like
746 * XXX UDB CE trap handler does... -DaveM
747 */
748 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
749 "UPA_MID[%02lx] was_block(%d)\n",
750 p->index,
751 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
752 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
753 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
754 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
755 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
756 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
757 printk("PSYCHO%d: CE Secondary errors [", p->index);
758 reported = 0;
759 if (afsr & PSYCHO_CEAFSR_SPIO) {
760 reported++;
761 printk("(PIO)");
762 }
763 if (afsr & PSYCHO_CEAFSR_SDRD) {
764 reported++;
765 printk("(DMA Read)");
766 }
767 if (afsr & PSYCHO_CEAFSR_SDWR) {
768 reported++;
769 printk("(DMA Write)");
770 }
771 if (!reported)
772 printk("(none)");
773 printk("]\n");
774
775 return IRQ_HANDLED;
776 }
777
778 /* PCI Errors. They are signalled by the PCI bus module since they
779 * are associated with a specific bus segment.
780 */
781 #define PSYCHO_PCI_AFSR_A 0x2010UL
782 #define PSYCHO_PCI_AFSR_B 0x4010UL
783 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
784 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
785 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
786 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
787 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
788 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
789 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
790 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
791 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
792 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
793 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
794 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
795 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
796 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
797 #define PSYCHO_PCI_AFAR_A 0x2018UL
798 #define PSYCHO_PCI_AFAR_B 0x4018UL
799
800 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
801 {
802 unsigned long csr_reg, csr, csr_error_bits;
803 irqreturn_t ret = IRQ_NONE;
804 u16 stat;
805
806 if (is_pbm_a) {
807 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
808 } else {
809 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
810 }
811 csr = psycho_read(csr_reg);
812 csr_error_bits =
813 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
814 if (csr_error_bits) {
815 /* Clear the errors. */
816 psycho_write(csr_reg, csr);
817
818 /* Log 'em. */
819 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
820 printk("%s: PCI streaming byte hole error asserted.\n",
821 pbm->name);
822 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
823 printk("%s: PCI SERR signal asserted.\n", pbm->name);
824 ret = IRQ_HANDLED;
825 }
826 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
827 if (stat & (PCI_STATUS_PARITY |
828 PCI_STATUS_SIG_TARGET_ABORT |
829 PCI_STATUS_REC_TARGET_ABORT |
830 PCI_STATUS_REC_MASTER_ABORT |
831 PCI_STATUS_SIG_SYSTEM_ERROR)) {
832 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
833 pbm->name, stat);
834 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
835 ret = IRQ_HANDLED;
836 }
837 return ret;
838 }
839
840 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
841 {
842 struct pci_pbm_info *pbm = dev_id;
843 struct pci_controller_info *p = pbm->parent;
844 unsigned long afsr_reg, afar_reg;
845 unsigned long afsr, afar, error_bits;
846 int is_pbm_a, reported;
847
848 is_pbm_a = (pbm == &pbm->parent->pbm_A);
849 if (is_pbm_a) {
850 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
851 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
852 } else {
853 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
854 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
855 }
856
857 /* Latch error status. */
858 afar = psycho_read(afar_reg);
859 afsr = psycho_read(afsr_reg);
860
861 /* Clear primary/secondary error status bits. */
862 error_bits = afsr &
863 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
864 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
865 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
866 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
867 if (!error_bits)
868 return psycho_pcierr_intr_other(pbm, is_pbm_a);
869 psycho_write(afsr_reg, error_bits);
870
871 /* Log the error. */
872 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
873 p->index, (is_pbm_a ? 'A' : 'B'),
874 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
875 "Master Abort" :
876 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
877 "Target Abort" :
878 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
879 "Excessive Retries" :
880 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
881 "Parity Error" : "???"))))));
882 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
883 p->index, (is_pbm_a ? 'A' : 'B'),
884 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
885 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
886 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
887 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
888 p->index, (is_pbm_a ? 'A' : 'B'), afar);
889 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
890 p->index, (is_pbm_a ? 'A' : 'B'));
891 reported = 0;
892 if (afsr & PSYCHO_PCIAFSR_SMA) {
893 reported++;
894 printk("(Master Abort)");
895 }
896 if (afsr & PSYCHO_PCIAFSR_STA) {
897 reported++;
898 printk("(Target Abort)");
899 }
900 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
901 reported++;
902 printk("(Excessive Retries)");
903 }
904 if (afsr & PSYCHO_PCIAFSR_SPERR) {
905 reported++;
906 printk("(Parity Error)");
907 }
908 if (!reported)
909 printk("(none)");
910 printk("]\n");
911
912 /* For the error types shown, scan PBM's PCI bus for devices
913 * which have logged that error type.
914 */
915
916 /* If we see a Target Abort, this could be the result of an
917 * IOMMU translation error of some sort. It is extremely
918 * useful to log this information as usually it indicates
919 * a bug in the IOMMU support code or a PCI device driver.
920 */
921 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
922 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
923 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
924 }
925 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
926 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
927
928 /* For excessive retries, PSYCHO/PBM will abort the device
929 * and there is no way to specifically check for excessive
930 * retries in the config space status registers. So what
931 * we hope is that we'll catch it via the master/target
932 * abort events.
933 */
934
935 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
936 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
937
938 return IRQ_HANDLED;
939 }
940
941 /* XXX What about PowerFail/PowerManagement??? -DaveM */
942 #define PSYCHO_ECC_CTRL 0x0020
943 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
944 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
945 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
946 #define PSYCHO_UE_INO 0x2e
947 #define PSYCHO_CE_INO 0x2f
948 #define PSYCHO_PCIERR_A_INO 0x30
949 #define PSYCHO_PCIERR_B_INO 0x31
950 static void psycho_register_error_handlers(struct pci_controller_info *p)
951 {
952 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
953 unsigned long base = p->pbm_A.controller_regs;
954 unsigned int irq, portid = pbm->portid;
955 u64 tmp;
956
957 /* Build IRQs and register handlers. */
958 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_UE_INO);
959 if (request_irq(irq, psycho_ue_intr,
960 SA_SHIRQ, "PSYCHO UE", p) < 0) {
961 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
962 p->index);
963 prom_halt();
964 }
965
966 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_CE_INO);
967 if (request_irq(irq, psycho_ce_intr,
968 SA_SHIRQ, "PSYCHO CE", p) < 0) {
969 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n",
970 p->index);
971 prom_halt();
972 }
973
974 pbm = &p->pbm_A;
975 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO);
976 if (request_irq(irq, psycho_pcierr_intr,
977 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) {
978 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
979 p->index);
980 prom_halt();
981 }
982
983 pbm = &p->pbm_B;
984 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO);
985 if (request_irq(irq, psycho_pcierr_intr,
986 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) {
987 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n",
988 p->index);
989 prom_halt();
990 }
991
992 /* Enable UE and CE interrupts for controller. */
993 psycho_write(base + PSYCHO_ECC_CTRL,
994 (PSYCHO_ECCCTRL_EE |
995 PSYCHO_ECCCTRL_UE |
996 PSYCHO_ECCCTRL_CE));
997
998 /* Enable PCI Error interrupts and clear error
999 * bits for each PBM.
1000 */
1001 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
1002 tmp |= (PSYCHO_PCICTRL_SERR |
1003 PSYCHO_PCICTRL_SBH_ERR |
1004 PSYCHO_PCICTRL_EEN);
1005 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1006 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
1007
1008 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
1009 tmp |= (PSYCHO_PCICTRL_SERR |
1010 PSYCHO_PCICTRL_SBH_ERR |
1011 PSYCHO_PCICTRL_EEN);
1012 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1013 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
1014 }
1015
1016 /* PSYCHO boot time probing and initialization. */
1017 static void psycho_resource_adjust(struct pci_dev *pdev,
1018 struct resource *res,
1019 struct resource *root)
1020 {
1021 res->start += root->start;
1022 res->end += root->start;
1023 }
1024
1025 static void psycho_base_address_update(struct pci_dev *pdev, int resource)
1026 {
1027 struct pcidev_cookie *pcp = pdev->sysdata;
1028 struct pci_pbm_info *pbm = pcp->pbm;
1029 struct resource *res, *root;
1030 u32 reg;
1031 int where, size, is_64bit;
1032
1033 res = &pdev->resource[resource];
1034 if (resource < 6) {
1035 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1036 } else if (resource == PCI_ROM_RESOURCE) {
1037 where = pdev->rom_base_reg;
1038 } else {
1039 /* Somebody might have asked allocation of a non-standard resource */
1040 return;
1041 }
1042
1043 is_64bit = 0;
1044 if (res->flags & IORESOURCE_IO)
1045 root = &pbm->io_space;
1046 else {
1047 root = &pbm->mem_space;
1048 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1049 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1050 is_64bit = 1;
1051 }
1052
1053 size = res->end - res->start;
1054 pci_read_config_dword(pdev, where, &reg);
1055 reg = ((reg & size) |
1056 (((u32)(res->start - root->start)) & ~size));
1057 if (resource == PCI_ROM_RESOURCE) {
1058 reg |= PCI_ROM_ADDRESS_ENABLE;
1059 res->flags |= IORESOURCE_ROM_ENABLE;
1060 }
1061 pci_write_config_dword(pdev, where, reg);
1062
1063 /* This knows that the upper 32-bits of the address
1064 * must be zero. Our PCI common layer enforces this.
1065 */
1066 if (is_64bit)
1067 pci_write_config_dword(pdev, where + 4, 0);
1068 }
1069
1070 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1071 {
1072 u8 *addr;
1073
1074 /* Set cache-line size to 64 bytes, this is actually
1075 * a nop but I do it for completeness.
1076 */
1077 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1078 0, PCI_CACHE_LINE_SIZE);
1079 pci_config_write8(addr, 64 / sizeof(u32));
1080
1081 /* Set PBM latency timer to 64 PCI clocks. */
1082 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1083 0, PCI_LATENCY_TIMER);
1084 pci_config_write8(addr, 64);
1085 }
1086
1087 static void pbm_scan_bus(struct pci_controller_info *p,
1088 struct pci_pbm_info *pbm)
1089 {
1090 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1091
1092 if (!cookie) {
1093 prom_printf("PSYCHO: Critical allocation failure.\n");
1094 prom_halt();
1095 }
1096
1097 /* All we care about is the PBM. */
1098 cookie->pbm = pbm;
1099
1100 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1101 p->pci_ops,
1102 pbm);
1103 pci_fixup_host_bridge_self(pbm->pci_bus);
1104 pbm->pci_bus->self->sysdata = cookie;
1105
1106 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1107 pci_record_assignments(pbm, pbm->pci_bus);
1108 pci_assign_unassigned(pbm, pbm->pci_bus);
1109 pci_fixup_irq(pbm, pbm->pci_bus);
1110 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1111 pci_setup_busmastering(pbm, pbm->pci_bus);
1112 }
1113
1114 static void psycho_scan_bus(struct pci_controller_info *p)
1115 {
1116 pbm_config_busmastering(&p->pbm_B);
1117 p->pbm_B.is_66mhz_capable = 0;
1118 pbm_config_busmastering(&p->pbm_A);
1119 p->pbm_A.is_66mhz_capable = 1;
1120 pbm_scan_bus(p, &p->pbm_B);
1121 pbm_scan_bus(p, &p->pbm_A);
1122
1123 /* After the PCI bus scan is complete, we can register
1124 * the error interrupt handlers.
1125 */
1126 psycho_register_error_handlers(p);
1127 }
1128
1129 static void psycho_iommu_init(struct pci_controller_info *p)
1130 {
1131 struct pci_iommu *iommu = p->pbm_A.iommu;
1132 unsigned long i;
1133 u64 control;
1134
1135 /* Register addresses. */
1136 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
1137 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
1138 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
1139 /* PSYCHO's IOMMU lacks ctx flushing. */
1140 iommu->iommu_ctxflush = 0;
1141
1142 /* We use the main control register of PSYCHO as the write
1143 * completion register.
1144 */
1145 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
1146
1147 /*
1148 * Invalidate TLB Entries.
1149 */
1150 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1151 control |= PSYCHO_IOMMU_CTRL_DENAB;
1152 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1153 for(i = 0; i < 16; i++) {
1154 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
1155 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1156 }
1157
1158 /* Leave diag mode enabled for full-flushing done
1159 * in pci_iommu.c
1160 */
1161 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1162
1163 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
1164 __pa(iommu->page_table));
1165
1166 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1167 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
1168 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
1169 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1170
1171 /* If necessary, hook us up for starfire IRQ translations. */
1172 if (this_is_starfire)
1173 p->starfire_cookie = starfire_hookup(p->pbm_A.portid);
1174 else
1175 p->starfire_cookie = NULL;
1176 }
1177
1178 #define PSYCHO_IRQ_RETRY 0x1a00UL
1179 #define PSYCHO_PCIA_DIAG 0x2020UL
1180 #define PSYCHO_PCIB_DIAG 0x4020UL
1181 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
1182 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
1183 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
1184 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
1185 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
1186 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
1187 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
1188 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1189
1190 static void psycho_controller_hwinit(struct pci_controller_info *p)
1191 {
1192 u64 tmp;
1193
1194 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1195
1196 /* Enable arbiter for all PCI slots. */
1197 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1198 tmp |= PSYCHO_PCICTRL_AEN;
1199 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1200
1201 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1202 tmp |= PSYCHO_PCICTRL_AEN;
1203 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1204
1205 /* Disable DMA write / PIO read synchronization on
1206 * both PCI bus segments.
1207 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1208 */
1209 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1210 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1211 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1212
1213 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1214 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1215 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1216 }
1217
1218 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1219 struct pci_pbm_info *pbm)
1220 {
1221 char *name = pbm->name;
1222
1223 sprintf(name, "PSYCHO%d PBM%c",
1224 p->index,
1225 (pbm == &p->pbm_A ? 'A' : 'B'));
1226 pbm->io_space.name = pbm->mem_space.name = name;
1227
1228 request_resource(&ioport_resource, &pbm->io_space);
1229 request_resource(&iomem_resource, &pbm->mem_space);
1230 pci_register_legacy_regions(&pbm->io_space,
1231 &pbm->mem_space);
1232 }
1233
1234 static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1235 struct pci_pbm_info *pbm,
1236 int is_pbm_a)
1237 {
1238 unsigned long base = pbm->controller_regs;
1239 u64 control;
1240
1241 if (is_pbm_a) {
1242 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1243 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1244 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1245 } else {
1246 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1247 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1248 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1249 }
1250 /* PSYCHO's streaming buffer lacks ctx flushing. */
1251 pbm->stc.strbuf_ctxflush = 0;
1252 pbm->stc.strbuf_ctxmatch_base = 0;
1253
1254 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1255 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1256 + 63UL)
1257 & ~63UL);
1258 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1259 __pa(pbm->stc.strbuf_flushflag);
1260
1261 /* Enable the streaming buffer. We have to be careful
1262 * just in case OBP left it with LRU locking enabled.
1263 *
1264 * It is possible to control if PBM will be rerun on
1265 * line misses. Currently I just retain whatever setting
1266 * OBP left us with. All checks so far show it having
1267 * a value of zero.
1268 */
1269 #undef PSYCHO_STRBUF_RERUN_ENABLE
1270 #undef PSYCHO_STRBUF_RERUN_DISABLE
1271 control = psycho_read(pbm->stc.strbuf_control);
1272 control |= PSYCHO_STRBUF_CTRL_ENAB;
1273 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1274 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1275 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1276 #else
1277 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1278 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1279 #endif
1280 #endif
1281 psycho_write(pbm->stc.strbuf_control, control);
1282
1283 pbm->stc.strbuf_enabled = 1;
1284 }
1285
1286 #define PSYCHO_IOSPACE_A 0x002000000UL
1287 #define PSYCHO_IOSPACE_B 0x002010000UL
1288 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1289 #define PSYCHO_MEMSPACE_A 0x100000000UL
1290 #define PSYCHO_MEMSPACE_B 0x180000000UL
1291 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1292
1293 static void psycho_pbm_init(struct pci_controller_info *p,
1294 int prom_node, int is_pbm_a)
1295 {
1296 unsigned int busrange[2];
1297 struct pci_pbm_info *pbm;
1298 int err;
1299
1300 if (is_pbm_a) {
1301 pbm = &p->pbm_A;
1302 pbm->pci_first_slot = 1;
1303 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_A;
1304 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_A;
1305 } else {
1306 pbm = &p->pbm_B;
1307 pbm->pci_first_slot = 2;
1308 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_B;
1309 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_B;
1310 }
1311
1312 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1313 pbm->chip_version =
1314 prom_getintdefault(prom_node, "version#", 0);
1315 pbm->chip_revision =
1316 prom_getintdefault(prom_node, "module-revision#", 0);
1317
1318 pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE;
1319 pbm->io_space.flags = IORESOURCE_IO;
1320 pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE;
1321 pbm->mem_space.flags = IORESOURCE_MEM;
1322 pbm_register_toplevel_resources(p, pbm);
1323
1324 pbm->parent = p;
1325 pbm->prom_node = prom_node;
1326 prom_getstring(prom_node, "name",
1327 pbm->prom_name,
1328 sizeof(pbm->prom_name));
1329
1330 err = prom_getproperty(prom_node, "ranges",
1331 (char *)pbm->pbm_ranges,
1332 sizeof(pbm->pbm_ranges));
1333 if (err != -1)
1334 pbm->num_pbm_ranges =
1335 (err / sizeof(struct linux_prom_pci_ranges));
1336 else
1337 pbm->num_pbm_ranges = 0;
1338
1339 err = prom_getproperty(prom_node, "interrupt-map",
1340 (char *)pbm->pbm_intmap,
1341 sizeof(pbm->pbm_intmap));
1342 if (err != -1) {
1343 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1344 err = prom_getproperty(prom_node, "interrupt-map-mask",
1345 (char *)&pbm->pbm_intmask,
1346 sizeof(pbm->pbm_intmask));
1347 if (err == -1) {
1348 prom_printf("PSYCHO-PBM: Fatal error, no "
1349 "interrupt-map-mask.\n");
1350 prom_halt();
1351 }
1352 } else {
1353 pbm->num_pbm_intmap = 0;
1354 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1355 }
1356
1357 err = prom_getproperty(prom_node, "bus-range",
1358 (char *)&busrange[0],
1359 sizeof(busrange));
1360 if (err == 0 || err == -1) {
1361 prom_printf("PSYCHO-PBM: Fatal error, no bus-range.\n");
1362 prom_halt();
1363 }
1364 pbm->pci_first_busno = busrange[0];
1365 pbm->pci_last_busno = busrange[1];
1366
1367 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1368 }
1369
1370 #define PSYCHO_CONFIGSPACE 0x001000000UL
1371
1372 void psycho_init(int node, char *model_name)
1373 {
1374 struct linux_prom64_registers pr_regs[3];
1375 struct pci_controller_info *p;
1376 struct pci_iommu *iommu;
1377 u32 upa_portid;
1378 int is_pbm_a, err;
1379
1380 upa_portid = prom_getintdefault(node, "upa-portid", 0xff);
1381
1382 for(p = pci_controller_root; p; p = p->next) {
1383 if (p->pbm_A.portid == upa_portid) {
1384 is_pbm_a = (p->pbm_A.prom_node == 0);
1385 psycho_pbm_init(p, node, is_pbm_a);
1386 return;
1387 }
1388 }
1389
1390 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1391 if (!p) {
1392 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1393 prom_halt();
1394 }
1395 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1396 if (!iommu) {
1397 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1398 prom_halt();
1399 }
1400 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1401
1402 p->next = pci_controller_root;
1403 pci_controller_root = p;
1404
1405 p->pbm_A.portid = upa_portid;
1406 p->pbm_B.portid = upa_portid;
1407 p->index = pci_num_controllers++;
1408 p->pbms_same_domain = 0;
1409 p->scan_bus = psycho_scan_bus;
1410 p->irq_build = psycho_irq_build;
1411 p->base_address_update = psycho_base_address_update;
1412 p->resource_adjust = psycho_resource_adjust;
1413 p->pci_ops = &psycho_ops;
1414
1415 err = prom_getproperty(node, "reg",
1416 (char *)&pr_regs[0],
1417 sizeof(pr_regs));
1418 if (err == 0 || err == -1) {
1419 prom_printf("PSYCHO: Fatal error, no reg property.\n");
1420 prom_halt();
1421 }
1422
1423 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1424 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1425 printk("PCI: Found PSYCHO, control regs at %016lx\n",
1426 p->pbm_A.controller_regs);
1427
1428 p->pbm_A.config_space = p->pbm_B.config_space =
1429 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1430 printk("PSYCHO: Shared PCI config space at %016lx\n",
1431 p->pbm_A.config_space);
1432
1433 /*
1434 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1435 * we need to adjust our MEM space mask.
1436 */
1437 pci_memspace_mask = 0x7fffffffUL;
1438
1439 psycho_controller_hwinit(p);
1440
1441 psycho_iommu_init(p);
1442
1443 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1444 psycho_pbm_init(p, node, is_pbm_a);
1445 }
Linux kernel - Deliverables
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