1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
16 #include <asm/iommu.h>
18 #include <asm/starfire.h>
20 #include <asm/of_device.h>
23 #include "iommu_common.h"
25 /* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
29 #define psycho_read(__reg) \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
37 #define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
44 /* Misc. PSYCHO PCI controller register offsets and definitions. */
45 #define PSYCHO_CONTROL 0x0010UL
46 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55 #define PSYCHO_PCIA_CTRL 0x2000UL
56 #define PSYCHO_PCIB_CTRL 0x4000UL
57 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
70 /* U2P Programmer's Manual, page 13-55, configuration space
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
78 #define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
85 static void *psycho_pci_config_mkaddr(struct pci_pbm_info
*pbm
,
93 (PSYCHO_CONFIG_BASE(pbm
) |
94 PSYCHO_CONFIG_ENCODE(bus
, devfn
, where
));
97 static int psycho_out_of_range(struct pci_pbm_info
*pbm
,
101 return ((pbm
->parent
== 0) ||
102 ((pbm
== &pbm
->parent
->pbm_B
) &&
103 (bus
== pbm
->pci_first_busno
) &&
104 PCI_SLOT(devfn
) > 8) ||
105 ((pbm
== &pbm
->parent
->pbm_A
) &&
106 (bus
== pbm
->pci_first_busno
) &&
107 PCI_SLOT(devfn
) > 8));
110 /* PSYCHO PCI configuration space accessors. */
112 static int psycho_read_pci_cfg(struct pci_bus
*bus_dev
, unsigned int devfn
,
113 int where
, int size
, u32
*value
)
115 struct pci_pbm_info
*pbm
= bus_dev
->sysdata
;
116 unsigned char bus
= bus_dev
->number
;
121 if (bus_dev
== pbm
->pci_bus
&& devfn
== 0x00)
122 return pci_host_bridge_read_pci_cfg(bus_dev
, devfn
, where
,
137 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
139 return PCIBIOS_SUCCESSFUL
;
141 if (psycho_out_of_range(pbm
, bus
, devfn
))
142 return PCIBIOS_SUCCESSFUL
;
145 pci_config_read8((u8
*)addr
, &tmp8
);
151 printk("pci_read_config_word: misaligned reg [%x]\n",
153 return PCIBIOS_SUCCESSFUL
;
155 pci_config_read16((u16
*)addr
, &tmp16
);
156 *value
= (u32
) tmp16
;
161 printk("pci_read_config_dword: misaligned reg [%x]\n",
163 return PCIBIOS_SUCCESSFUL
;
165 pci_config_read32(addr
, value
);
168 return PCIBIOS_SUCCESSFUL
;
171 static int psycho_write_pci_cfg(struct pci_bus
*bus_dev
, unsigned int devfn
,
172 int where
, int size
, u32 value
)
174 struct pci_pbm_info
*pbm
= bus_dev
->sysdata
;
175 unsigned char bus
= bus_dev
->number
;
178 if (bus_dev
== pbm
->pci_bus
&& devfn
== 0x00)
179 return pci_host_bridge_write_pci_cfg(bus_dev
, devfn
, where
,
181 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
183 return PCIBIOS_SUCCESSFUL
;
185 if (psycho_out_of_range(pbm
, bus
, devfn
))
186 return PCIBIOS_SUCCESSFUL
;
190 pci_config_write8((u8
*)addr
, value
);
195 printk("pci_write_config_word: misaligned reg [%x]\n",
197 return PCIBIOS_SUCCESSFUL
;
199 pci_config_write16((u16
*)addr
, value
);
204 printk("pci_write_config_dword: misaligned reg [%x]\n",
206 return PCIBIOS_SUCCESSFUL
;
208 pci_config_write32(addr
, value
);
210 return PCIBIOS_SUCCESSFUL
;
213 static struct pci_ops psycho_ops
= {
214 .read
= psycho_read_pci_cfg
,
215 .write
= psycho_write_pci_cfg
,
218 /* PSYCHO error handling support. */
219 enum psycho_error_type
{
220 UE_ERR
, CE_ERR
, PCI_ERR
223 /* Helper function of IOMMU error checking, which checks out
224 * the state of the streaming buffers. The IOMMU lock is
225 * held when this is called.
227 * For the PCI error case we know which PBM (and thus which
228 * streaming buffer) caused the error, but for the uncorrectable
229 * error case we do not. So we always check both streaming caches.
231 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
232 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
233 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
234 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
235 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
236 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
237 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
238 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
239 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
240 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
241 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
242 #define PSYCHO_STC_DATA_A 0xb000UL
243 #define PSYCHO_STC_DATA_B 0xc000UL
244 #define PSYCHO_STC_ERR_A 0xb400UL
245 #define PSYCHO_STC_ERR_B 0xc400UL
246 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
247 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
248 #define PSYCHO_STC_TAG_A 0xb800UL
249 #define PSYCHO_STC_TAG_B 0xc800UL
250 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
251 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
252 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
253 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
254 #define PSYCHO_STC_LINE_A 0xb900UL
255 #define PSYCHO_STC_LINE_B 0xc900UL
256 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
257 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
258 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
259 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
260 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
261 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
263 static DEFINE_SPINLOCK(stc_buf_lock
);
264 static unsigned long stc_error_buf
[128];
265 static unsigned long stc_tag_buf
[16];
266 static unsigned long stc_line_buf
[16];
268 static void __psycho_check_one_stc(struct pci_controller_info
*p
,
269 struct pci_pbm_info
*pbm
,
272 struct strbuf
*strbuf
= &pbm
->stc
;
273 unsigned long regbase
= p
->pbm_A
.controller_regs
;
274 unsigned long err_base
, tag_base
, line_base
;
279 err_base
= regbase
+ PSYCHO_STC_ERR_A
;
280 tag_base
= regbase
+ PSYCHO_STC_TAG_A
;
281 line_base
= regbase
+ PSYCHO_STC_LINE_A
;
283 err_base
= regbase
+ PSYCHO_STC_ERR_B
;
284 tag_base
= regbase
+ PSYCHO_STC_TAG_B
;
285 line_base
= regbase
+ PSYCHO_STC_LINE_B
;
288 spin_lock(&stc_buf_lock
);
290 /* This is __REALLY__ dangerous. When we put the
291 * streaming buffer into diagnostic mode to probe
292 * it's tags and error status, we _must_ clear all
293 * of the line tag valid bits before re-enabling
294 * the streaming buffer. If any dirty data lives
295 * in the STC when we do this, we will end up
296 * invalidating it before it has a chance to reach
299 control
= psycho_read(strbuf
->strbuf_control
);
300 psycho_write(strbuf
->strbuf_control
,
301 (control
| PSYCHO_STRBUF_CTRL_DENAB
));
302 for (i
= 0; i
< 128; i
++) {
305 val
= psycho_read(err_base
+ (i
* 8UL));
306 psycho_write(err_base
+ (i
* 8UL), 0UL);
307 stc_error_buf
[i
] = val
;
309 for (i
= 0; i
< 16; i
++) {
310 stc_tag_buf
[i
] = psycho_read(tag_base
+ (i
* 8UL));
311 stc_line_buf
[i
] = psycho_read(line_base
+ (i
* 8UL));
312 psycho_write(tag_base
+ (i
* 8UL), 0UL);
313 psycho_write(line_base
+ (i
* 8UL), 0UL);
316 /* OK, state is logged, exit diagnostic mode. */
317 psycho_write(strbuf
->strbuf_control
, control
);
319 for (i
= 0; i
< 16; i
++) {
320 int j
, saw_error
, first
, last
;
325 for (j
= first
; j
< last
; j
++) {
326 unsigned long errval
= stc_error_buf
[j
];
329 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
331 (is_pbm_a
? 'A' : 'B'),
333 (errval
& PSYCHO_STCERR_WRITE
) ? 1 : 0,
334 (errval
& PSYCHO_STCERR_READ
) ? 1 : 0);
337 if (saw_error
!= 0) {
338 unsigned long tagval
= stc_tag_buf
[i
];
339 unsigned long lineval
= stc_line_buf
[i
];
340 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
342 (is_pbm_a
? 'A' : 'B'),
344 ((tagval
& PSYCHO_STCTAG_PPN
) >> 19UL),
345 (tagval
& PSYCHO_STCTAG_VPN
),
346 ((tagval
& PSYCHO_STCTAG_VALID
) ? 1 : 0),
347 ((tagval
& PSYCHO_STCTAG_WRITE
) ? 1 : 0));
348 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
351 (is_pbm_a
? 'A' : 'B'),
353 ((lineval
& PSYCHO_STCLINE_LINDX
) >> 21UL),
354 ((lineval
& PSYCHO_STCLINE_SPTR
) >> 15UL),
355 ((lineval
& PSYCHO_STCLINE_LADDR
) >> 8UL),
356 ((lineval
& PSYCHO_STCLINE_EPTR
) >> 2UL),
357 ((lineval
& PSYCHO_STCLINE_VALID
) ? 1 : 0),
358 ((lineval
& PSYCHO_STCLINE_FOFN
) ? 1 : 0));
362 spin_unlock(&stc_buf_lock
);
365 static void __psycho_check_stc_error(struct pci_controller_info
*p
,
368 enum psycho_error_type type
)
370 struct pci_pbm_info
*pbm
;
373 if (pbm
->stc
.strbuf_enabled
)
374 __psycho_check_one_stc(p
, pbm
, 1);
377 if (pbm
->stc
.strbuf_enabled
)
378 __psycho_check_one_stc(p
, pbm
, 0);
381 /* When an Uncorrectable Error or a PCI Error happens, we
382 * interrogate the IOMMU state to see if it is the cause.
384 #define PSYCHO_IOMMU_CONTROL 0x0200UL
385 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
386 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
387 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
388 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
389 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
390 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
391 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
392 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
393 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
394 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
395 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
396 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
397 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
398 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
399 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
400 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
401 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
402 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
403 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
404 #define PSYCHO_IOMMU_FLUSH 0x0210UL
405 #define PSYCHO_IOMMU_TAG 0xa580UL
406 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
407 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
408 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
409 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
410 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
411 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
412 #define PSYCHO_IOMMU_DATA 0xa600UL
413 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
414 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
415 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
416 static void psycho_check_iommu_error(struct pci_controller_info
*p
,
419 enum psycho_error_type type
)
421 struct iommu
*iommu
= p
->pbm_A
.iommu
;
422 unsigned long iommu_tag
[16];
423 unsigned long iommu_data
[16];
428 spin_lock_irqsave(&iommu
->lock
, flags
);
429 control
= psycho_read(iommu
->iommu_control
);
430 if (control
& PSYCHO_IOMMU_CTRL_XLTEERR
) {
433 /* Clear the error encountered bit. */
434 control
&= ~PSYCHO_IOMMU_CTRL_XLTEERR
;
435 psycho_write(iommu
->iommu_control
, control
);
437 switch((control
& PSYCHO_IOMMU_CTRL_XLTESTAT
) >> 25UL) {
439 type_string
= "Protection Error";
442 type_string
= "Invalid Error";
445 type_string
= "TimeOut Error";
449 type_string
= "ECC Error";
452 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
453 p
->index
, type_string
);
455 /* Put the IOMMU into diagnostic mode and probe
456 * it's TLB for entries with error status.
458 * It is very possible for another DVMA to occur
459 * while we do this probe, and corrupt the system
460 * further. But we are so screwed at this point
461 * that we are likely to crash hard anyways, so
462 * get as much diagnostic information to the
465 psycho_write(iommu
->iommu_control
,
466 control
| PSYCHO_IOMMU_CTRL_DENAB
);
467 for (i
= 0; i
< 16; i
++) {
468 unsigned long base
= p
->pbm_A
.controller_regs
;
471 psycho_read(base
+ PSYCHO_IOMMU_TAG
+ (i
* 8UL));
473 psycho_read(base
+ PSYCHO_IOMMU_DATA
+ (i
* 8UL));
475 /* Now clear out the entry. */
476 psycho_write(base
+ PSYCHO_IOMMU_TAG
+ (i
* 8UL), 0);
477 psycho_write(base
+ PSYCHO_IOMMU_DATA
+ (i
* 8UL), 0);
480 /* Leave diagnostic mode. */
481 psycho_write(iommu
->iommu_control
, control
);
483 for (i
= 0; i
< 16; i
++) {
484 unsigned long tag
, data
;
487 if (!(tag
& PSYCHO_IOMMU_TAG_ERR
))
490 data
= iommu_data
[i
];
491 switch((tag
& PSYCHO_IOMMU_TAG_ERRSTS
) >> 23UL) {
493 type_string
= "Protection Error";
496 type_string
= "Invalid Error";
499 type_string
= "TimeOut Error";
503 type_string
= "ECC Error";
506 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
507 p
->index
, i
, type_string
,
508 ((tag
& PSYCHO_IOMMU_TAG_WRITE
) ? 1 : 0),
509 ((tag
& PSYCHO_IOMMU_TAG_STREAM
) ? 1 : 0),
510 ((tag
& PSYCHO_IOMMU_TAG_SIZE
) ? 64 : 8),
511 (tag
& PSYCHO_IOMMU_TAG_VPAGE
) << IOMMU_PAGE_SHIFT
);
512 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
514 ((data
& PSYCHO_IOMMU_DATA_VALID
) ? 1 : 0),
515 ((data
& PSYCHO_IOMMU_DATA_CACHE
) ? 1 : 0),
516 (data
& PSYCHO_IOMMU_DATA_PPAGE
) << IOMMU_PAGE_SHIFT
);
519 __psycho_check_stc_error(p
, afsr
, afar
, type
);
520 spin_unlock_irqrestore(&iommu
->lock
, flags
);
523 /* Uncorrectable Errors. Cause of the error and the address are
524 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
525 * relating to UPA interface transactions.
527 #define PSYCHO_UE_AFSR 0x0030UL
528 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
529 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
530 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
531 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
532 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
533 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
534 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
535 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
536 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
537 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
538 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
539 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
540 #define PSYCHO_UE_AFAR 0x0038UL
542 static irqreturn_t
psycho_ue_intr(int irq
, void *dev_id
)
544 struct pci_controller_info
*p
= dev_id
;
545 unsigned long afsr_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_UE_AFSR
;
546 unsigned long afar_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_UE_AFAR
;
547 unsigned long afsr
, afar
, error_bits
;
550 /* Latch uncorrectable error status. */
551 afar
= psycho_read(afar_reg
);
552 afsr
= psycho_read(afsr_reg
);
554 /* Clear the primary/secondary error status bits. */
556 (PSYCHO_UEAFSR_PPIO
| PSYCHO_UEAFSR_PDRD
| PSYCHO_UEAFSR_PDWR
|
557 PSYCHO_UEAFSR_SPIO
| PSYCHO_UEAFSR_SDRD
| PSYCHO_UEAFSR_SDWR
);
560 psycho_write(afsr_reg
, error_bits
);
563 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
565 (((error_bits
& PSYCHO_UEAFSR_PPIO
) ?
567 ((error_bits
& PSYCHO_UEAFSR_PDRD
) ?
569 ((error_bits
& PSYCHO_UEAFSR_PDWR
) ?
570 "DMA Write" : "???")))));
571 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
573 (afsr
& PSYCHO_UEAFSR_BMSK
) >> 32UL,
574 (afsr
& PSYCHO_UEAFSR_DOFF
) >> 29UL,
575 (afsr
& PSYCHO_UEAFSR_MID
) >> 24UL,
576 ((afsr
& PSYCHO_UEAFSR_BLK
) ? 1 : 0));
577 printk("PSYCHO%d: UE AFAR [%016lx]\n", p
->index
, afar
);
578 printk("PSYCHO%d: UE Secondary errors [", p
->index
);
580 if (afsr
& PSYCHO_UEAFSR_SPIO
) {
584 if (afsr
& PSYCHO_UEAFSR_SDRD
) {
586 printk("(DMA Read)");
588 if (afsr
& PSYCHO_UEAFSR_SDWR
) {
590 printk("(DMA Write)");
596 /* Interrogate IOMMU for error status. */
597 psycho_check_iommu_error(p
, afsr
, afar
, UE_ERR
);
602 /* Correctable Errors. */
603 #define PSYCHO_CE_AFSR 0x0040UL
604 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
605 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
606 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
607 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
608 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
609 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
610 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
611 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
612 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
613 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
614 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
615 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
616 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
617 #define PSYCHO_CE_AFAR 0x0040UL
619 static irqreturn_t
psycho_ce_intr(int irq
, void *dev_id
)
621 struct pci_controller_info
*p
= dev_id
;
622 unsigned long afsr_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_CE_AFSR
;
623 unsigned long afar_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_CE_AFAR
;
624 unsigned long afsr
, afar
, error_bits
;
627 /* Latch error status. */
628 afar
= psycho_read(afar_reg
);
629 afsr
= psycho_read(afsr_reg
);
631 /* Clear primary/secondary error status bits. */
633 (PSYCHO_CEAFSR_PPIO
| PSYCHO_CEAFSR_PDRD
| PSYCHO_CEAFSR_PDWR
|
634 PSYCHO_CEAFSR_SPIO
| PSYCHO_CEAFSR_SDRD
| PSYCHO_CEAFSR_SDWR
);
637 psycho_write(afsr_reg
, error_bits
);
640 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
642 (((error_bits
& PSYCHO_CEAFSR_PPIO
) ?
644 ((error_bits
& PSYCHO_CEAFSR_PDRD
) ?
646 ((error_bits
& PSYCHO_CEAFSR_PDWR
) ?
647 "DMA Write" : "???")))));
649 /* XXX Use syndrome and afar to print out module string just like
650 * XXX UDB CE trap handler does... -DaveM
652 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
653 "UPA_MID[%02lx] was_block(%d)\n",
655 (afsr
& PSYCHO_CEAFSR_ESYND
) >> 48UL,
656 (afsr
& PSYCHO_CEAFSR_BMSK
) >> 32UL,
657 (afsr
& PSYCHO_CEAFSR_DOFF
) >> 29UL,
658 (afsr
& PSYCHO_CEAFSR_MID
) >> 24UL,
659 ((afsr
& PSYCHO_CEAFSR_BLK
) ? 1 : 0));
660 printk("PSYCHO%d: CE AFAR [%016lx]\n", p
->index
, afar
);
661 printk("PSYCHO%d: CE Secondary errors [", p
->index
);
663 if (afsr
& PSYCHO_CEAFSR_SPIO
) {
667 if (afsr
& PSYCHO_CEAFSR_SDRD
) {
669 printk("(DMA Read)");
671 if (afsr
& PSYCHO_CEAFSR_SDWR
) {
673 printk("(DMA Write)");
682 /* PCI Errors. They are signalled by the PCI bus module since they
683 * are associated with a specific bus segment.
685 #define PSYCHO_PCI_AFSR_A 0x2010UL
686 #define PSYCHO_PCI_AFSR_B 0x4010UL
687 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
688 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
689 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
690 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
691 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
692 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
693 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
694 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
695 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
696 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
697 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
698 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
699 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
700 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
701 #define PSYCHO_PCI_AFAR_A 0x2018UL
702 #define PSYCHO_PCI_AFAR_B 0x4018UL
704 static irqreturn_t
psycho_pcierr_intr_other(struct pci_pbm_info
*pbm
, int is_pbm_a
)
706 unsigned long csr_reg
, csr
, csr_error_bits
;
707 irqreturn_t ret
= IRQ_NONE
;
711 csr_reg
= pbm
->controller_regs
+ PSYCHO_PCIA_CTRL
;
713 csr_reg
= pbm
->controller_regs
+ PSYCHO_PCIB_CTRL
;
715 csr
= psycho_read(csr_reg
);
717 csr
& (PSYCHO_PCICTRL_SBH_ERR
| PSYCHO_PCICTRL_SERR
);
718 if (csr_error_bits
) {
719 /* Clear the errors. */
720 psycho_write(csr_reg
, csr
);
723 if (csr_error_bits
& PSYCHO_PCICTRL_SBH_ERR
)
724 printk("%s: PCI streaming byte hole error asserted.\n",
726 if (csr_error_bits
& PSYCHO_PCICTRL_SERR
)
727 printk("%s: PCI SERR signal asserted.\n", pbm
->name
);
730 pci_read_config_word(pbm
->pci_bus
->self
, PCI_STATUS
, &stat
);
731 if (stat
& (PCI_STATUS_PARITY
|
732 PCI_STATUS_SIG_TARGET_ABORT
|
733 PCI_STATUS_REC_TARGET_ABORT
|
734 PCI_STATUS_REC_MASTER_ABORT
|
735 PCI_STATUS_SIG_SYSTEM_ERROR
)) {
736 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
738 pci_write_config_word(pbm
->pci_bus
->self
, PCI_STATUS
, 0xffff);
744 static irqreturn_t
psycho_pcierr_intr(int irq
, void *dev_id
)
746 struct pci_pbm_info
*pbm
= dev_id
;
747 struct pci_controller_info
*p
= pbm
->parent
;
748 unsigned long afsr_reg
, afar_reg
;
749 unsigned long afsr
, afar
, error_bits
;
750 int is_pbm_a
, reported
;
752 is_pbm_a
= (pbm
== &pbm
->parent
->pbm_A
);
754 afsr_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_PCI_AFSR_A
;
755 afar_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_PCI_AFAR_A
;
757 afsr_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_PCI_AFSR_B
;
758 afar_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_PCI_AFAR_B
;
761 /* Latch error status. */
762 afar
= psycho_read(afar_reg
);
763 afsr
= psycho_read(afsr_reg
);
765 /* Clear primary/secondary error status bits. */
767 (PSYCHO_PCIAFSR_PMA
| PSYCHO_PCIAFSR_PTA
|
768 PSYCHO_PCIAFSR_PRTRY
| PSYCHO_PCIAFSR_PPERR
|
769 PSYCHO_PCIAFSR_SMA
| PSYCHO_PCIAFSR_STA
|
770 PSYCHO_PCIAFSR_SRTRY
| PSYCHO_PCIAFSR_SPERR
);
772 return psycho_pcierr_intr_other(pbm
, is_pbm_a
);
773 psycho_write(afsr_reg
, error_bits
);
776 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
777 p
->index
, (is_pbm_a
? 'A' : 'B'),
778 (((error_bits
& PSYCHO_PCIAFSR_PMA
) ?
780 ((error_bits
& PSYCHO_PCIAFSR_PTA
) ?
782 ((error_bits
& PSYCHO_PCIAFSR_PRTRY
) ?
783 "Excessive Retries" :
784 ((error_bits
& PSYCHO_PCIAFSR_PPERR
) ?
785 "Parity Error" : "???"))))));
786 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
787 p
->index
, (is_pbm_a
? 'A' : 'B'),
788 (afsr
& PSYCHO_PCIAFSR_BMSK
) >> 32UL,
789 (afsr
& PSYCHO_PCIAFSR_MID
) >> 25UL,
790 (afsr
& PSYCHO_PCIAFSR_BLK
) ? 1 : 0);
791 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
792 p
->index
, (is_pbm_a
? 'A' : 'B'), afar
);
793 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
794 p
->index
, (is_pbm_a
? 'A' : 'B'));
796 if (afsr
& PSYCHO_PCIAFSR_SMA
) {
798 printk("(Master Abort)");
800 if (afsr
& PSYCHO_PCIAFSR_STA
) {
802 printk("(Target Abort)");
804 if (afsr
& PSYCHO_PCIAFSR_SRTRY
) {
806 printk("(Excessive Retries)");
808 if (afsr
& PSYCHO_PCIAFSR_SPERR
) {
810 printk("(Parity Error)");
816 /* For the error types shown, scan PBM's PCI bus for devices
817 * which have logged that error type.
820 /* If we see a Target Abort, this could be the result of an
821 * IOMMU translation error of some sort. It is extremely
822 * useful to log this information as usually it indicates
823 * a bug in the IOMMU support code or a PCI device driver.
825 if (error_bits
& (PSYCHO_PCIAFSR_PTA
| PSYCHO_PCIAFSR_STA
)) {
826 psycho_check_iommu_error(p
, afsr
, afar
, PCI_ERR
);
827 pci_scan_for_target_abort(p
, pbm
, pbm
->pci_bus
);
829 if (error_bits
& (PSYCHO_PCIAFSR_PMA
| PSYCHO_PCIAFSR_SMA
))
830 pci_scan_for_master_abort(p
, pbm
, pbm
->pci_bus
);
832 /* For excessive retries, PSYCHO/PBM will abort the device
833 * and there is no way to specifically check for excessive
834 * retries in the config space status registers. So what
835 * we hope is that we'll catch it via the master/target
839 if (error_bits
& (PSYCHO_PCIAFSR_PPERR
| PSYCHO_PCIAFSR_SPERR
))
840 pci_scan_for_parity_error(p
, pbm
, pbm
->pci_bus
);
845 /* XXX What about PowerFail/PowerManagement??? -DaveM */
846 #define PSYCHO_ECC_CTRL 0x0020
847 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
848 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
849 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
850 static void psycho_register_error_handlers(struct pci_controller_info
*p
)
852 struct pci_pbm_info
*pbm
= &p
->pbm_A
; /* arbitrary */
853 struct of_device
*op
= of_find_device_by_node(pbm
->prom_node
);
854 unsigned long base
= p
->pbm_A
.controller_regs
;
860 /* Psycho interrupt property order is:
861 * 0: PCIERR PBM B INO
866 * 5: PCIERR PBM A INO
869 if (op
->num_irqs
< 6)
872 request_irq(op
->irqs
[1], psycho_ue_intr
, IRQF_SHARED
, "PSYCHO UE", p
);
873 request_irq(op
->irqs
[2], psycho_ce_intr
, IRQF_SHARED
, "PSYCHO CE", p
);
874 request_irq(op
->irqs
[5], psycho_pcierr_intr
, IRQF_SHARED
,
875 "PSYCHO PCIERR-A", &p
->pbm_A
);
876 request_irq(op
->irqs
[0], psycho_pcierr_intr
, IRQF_SHARED
,
877 "PSYCHO PCIERR-B", &p
->pbm_B
);
879 /* Enable UE and CE interrupts for controller. */
880 psycho_write(base
+ PSYCHO_ECC_CTRL
,
885 /* Enable PCI Error interrupts and clear error
888 tmp
= psycho_read(base
+ PSYCHO_PCIA_CTRL
);
889 tmp
|= (PSYCHO_PCICTRL_SERR
|
890 PSYCHO_PCICTRL_SBH_ERR
|
892 tmp
&= ~(PSYCHO_PCICTRL_SBH_INT
);
893 psycho_write(base
+ PSYCHO_PCIA_CTRL
, tmp
);
895 tmp
= psycho_read(base
+ PSYCHO_PCIB_CTRL
);
896 tmp
|= (PSYCHO_PCICTRL_SERR
|
897 PSYCHO_PCICTRL_SBH_ERR
|
899 tmp
&= ~(PSYCHO_PCICTRL_SBH_INT
);
900 psycho_write(base
+ PSYCHO_PCIB_CTRL
, tmp
);
903 /* PSYCHO boot time probing and initialization. */
904 static void pbm_config_busmastering(struct pci_pbm_info
*pbm
)
908 /* Set cache-line size to 64 bytes, this is actually
909 * a nop but I do it for completeness.
911 addr
= psycho_pci_config_mkaddr(pbm
, pbm
->pci_first_busno
,
912 0, PCI_CACHE_LINE_SIZE
);
913 pci_config_write8(addr
, 64 / sizeof(u32
));
915 /* Set PBM latency timer to 64 PCI clocks. */
916 addr
= psycho_pci_config_mkaddr(pbm
, pbm
->pci_first_busno
,
917 0, PCI_LATENCY_TIMER
);
918 pci_config_write8(addr
, 64);
921 static void pbm_scan_bus(struct pci_controller_info
*p
,
922 struct pci_pbm_info
*pbm
)
924 pbm
->pci_bus
= pci_scan_one_pbm(pbm
);
927 static void psycho_scan_bus(struct pci_controller_info
*p
)
929 pbm_config_busmastering(&p
->pbm_B
);
930 p
->pbm_B
.is_66mhz_capable
= 0;
931 pbm_config_busmastering(&p
->pbm_A
);
932 p
->pbm_A
.is_66mhz_capable
= 1;
933 pbm_scan_bus(p
, &p
->pbm_B
);
934 pbm_scan_bus(p
, &p
->pbm_A
);
936 /* After the PCI bus scan is complete, we can register
937 * the error interrupt handlers.
939 psycho_register_error_handlers(p
);
942 static void psycho_iommu_init(struct pci_controller_info
*p
)
944 struct iommu
*iommu
= p
->pbm_A
.iommu
;
948 /* Register addresses. */
949 iommu
->iommu_control
= p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_CONTROL
;
950 iommu
->iommu_tsbbase
= p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_TSBBASE
;
951 iommu
->iommu_flush
= p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_FLUSH
;
952 /* PSYCHO's IOMMU lacks ctx flushing. */
953 iommu
->iommu_ctxflush
= 0;
955 /* We use the main control register of PSYCHO as the write
956 * completion register.
958 iommu
->write_complete_reg
= p
->pbm_A
.controller_regs
+ PSYCHO_CONTROL
;
961 * Invalidate TLB Entries.
963 control
= psycho_read(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_CONTROL
);
964 control
|= PSYCHO_IOMMU_CTRL_DENAB
;
965 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_CONTROL
, control
);
966 for(i
= 0; i
< 16; i
++) {
967 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_TAG
+ (i
* 8UL), 0);
968 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_DATA
+ (i
* 8UL), 0);
971 /* Leave diag mode enabled for full-flushing done
974 pci_iommu_table_init(iommu
, IO_TSB_SIZE
, 0xc0000000, 0xffffffff);
976 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_TSBBASE
,
977 __pa(iommu
->page_table
));
979 control
= psycho_read(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_CONTROL
);
980 control
&= ~(PSYCHO_IOMMU_CTRL_TSBSZ
| PSYCHO_IOMMU_CTRL_TBWSZ
);
981 control
|= (PSYCHO_IOMMU_TSBSZ_128K
| PSYCHO_IOMMU_CTRL_ENAB
);
982 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_IOMMU_CONTROL
, control
);
984 /* If necessary, hook us up for starfire IRQ translations. */
985 if (this_is_starfire
)
986 starfire_hookup(p
->pbm_A
.portid
);
989 #define PSYCHO_IRQ_RETRY 0x1a00UL
990 #define PSYCHO_PCIA_DIAG 0x2020UL
991 #define PSYCHO_PCIB_DIAG 0x4020UL
992 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
993 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
994 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
995 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
996 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
997 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
998 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
999 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1001 static void psycho_controller_hwinit(struct pci_controller_info
*p
)
1005 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_IRQ_RETRY
, 5);
1007 /* Enable arbiter for all PCI slots. */
1008 tmp
= psycho_read(p
->pbm_A
.controller_regs
+ PSYCHO_PCIA_CTRL
);
1009 tmp
|= PSYCHO_PCICTRL_AEN
;
1010 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_PCIA_CTRL
, tmp
);
1012 tmp
= psycho_read(p
->pbm_A
.controller_regs
+ PSYCHO_PCIB_CTRL
);
1013 tmp
|= PSYCHO_PCICTRL_AEN
;
1014 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_PCIB_CTRL
, tmp
);
1016 /* Disable DMA write / PIO read synchronization on
1017 * both PCI bus segments.
1018 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1020 tmp
= psycho_read(p
->pbm_A
.controller_regs
+ PSYCHO_PCIA_DIAG
);
1021 tmp
|= PSYCHO_PCIDIAG_DDWSYNC
;
1022 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_PCIA_DIAG
, tmp
);
1024 tmp
= psycho_read(p
->pbm_A
.controller_regs
+ PSYCHO_PCIB_DIAG
);
1025 tmp
|= PSYCHO_PCIDIAG_DDWSYNC
;
1026 psycho_write(p
->pbm_A
.controller_regs
+ PSYCHO_PCIB_DIAG
, tmp
);
1029 static void psycho_pbm_strbuf_init(struct pci_controller_info
*p
,
1030 struct pci_pbm_info
*pbm
,
1033 unsigned long base
= pbm
->controller_regs
;
1037 pbm
->stc
.strbuf_control
= base
+ PSYCHO_STRBUF_CONTROL_A
;
1038 pbm
->stc
.strbuf_pflush
= base
+ PSYCHO_STRBUF_FLUSH_A
;
1039 pbm
->stc
.strbuf_fsync
= base
+ PSYCHO_STRBUF_FSYNC_A
;
1041 pbm
->stc
.strbuf_control
= base
+ PSYCHO_STRBUF_CONTROL_B
;
1042 pbm
->stc
.strbuf_pflush
= base
+ PSYCHO_STRBUF_FLUSH_B
;
1043 pbm
->stc
.strbuf_fsync
= base
+ PSYCHO_STRBUF_FSYNC_B
;
1045 /* PSYCHO's streaming buffer lacks ctx flushing. */
1046 pbm
->stc
.strbuf_ctxflush
= 0;
1047 pbm
->stc
.strbuf_ctxmatch_base
= 0;
1049 pbm
->stc
.strbuf_flushflag
= (volatile unsigned long *)
1050 ((((unsigned long)&pbm
->stc
.__flushflag_buf
[0])
1053 pbm
->stc
.strbuf_flushflag_pa
= (unsigned long)
1054 __pa(pbm
->stc
.strbuf_flushflag
);
1056 /* Enable the streaming buffer. We have to be careful
1057 * just in case OBP left it with LRU locking enabled.
1059 * It is possible to control if PBM will be rerun on
1060 * line misses. Currently I just retain whatever setting
1061 * OBP left us with. All checks so far show it having
1064 #undef PSYCHO_STRBUF_RERUN_ENABLE
1065 #undef PSYCHO_STRBUF_RERUN_DISABLE
1066 control
= psycho_read(pbm
->stc
.strbuf_control
);
1067 control
|= PSYCHO_STRBUF_CTRL_ENAB
;
1068 control
&= ~(PSYCHO_STRBUF_CTRL_LENAB
| PSYCHO_STRBUF_CTRL_LPTR
);
1069 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1070 control
&= ~(PSYCHO_STRBUF_CTRL_RRDIS
);
1072 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1073 control
|= PSYCHO_STRBUF_CTRL_RRDIS
;
1076 psycho_write(pbm
->stc
.strbuf_control
, control
);
1078 pbm
->stc
.strbuf_enabled
= 1;
1081 #define PSYCHO_IOSPACE_A 0x002000000UL
1082 #define PSYCHO_IOSPACE_B 0x002010000UL
1083 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1084 #define PSYCHO_MEMSPACE_A 0x100000000UL
1085 #define PSYCHO_MEMSPACE_B 0x180000000UL
1086 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1088 static void psycho_pbm_init(struct pci_controller_info
*p
,
1089 struct device_node
*dp
, int is_pbm_a
)
1091 unsigned int *busrange
;
1092 struct property
*prop
;
1093 struct pci_pbm_info
*pbm
;
1100 pbm
->chip_type
= PBM_CHIP_TYPE_PSYCHO
;
1101 pbm
->chip_version
= 0;
1102 prop
= of_find_property(dp
, "version#", NULL
);
1104 pbm
->chip_version
= *(int *) prop
->value
;
1105 pbm
->chip_revision
= 0;
1106 prop
= of_find_property(dp
, "module-revision#", NULL
);
1108 pbm
->chip_revision
= *(int *) prop
->value
;
1111 pbm
->prom_node
= dp
;
1112 pbm
->name
= dp
->full_name
;
1114 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1116 pbm
->chip_version
, pbm
->chip_revision
);
1118 pci_determine_mem_io_space(pbm
);
1120 prop
= of_find_property(dp
, "bus-range", NULL
);
1121 busrange
= prop
->value
;
1122 pbm
->pci_first_busno
= busrange
[0];
1123 pbm
->pci_last_busno
= busrange
[1];
1125 psycho_pbm_strbuf_init(p
, pbm
, is_pbm_a
);
1128 #define PSYCHO_CONFIGSPACE 0x001000000UL
1130 void psycho_init(struct device_node
*dp
, char *model_name
)
1132 struct linux_prom64_registers
*pr_regs
;
1133 struct pci_controller_info
*p
;
1134 struct iommu
*iommu
;
1135 struct property
*prop
;
1140 prop
= of_find_property(dp
, "upa-portid", NULL
);
1142 upa_portid
= *(u32
*) prop
->value
;
1144 for(p
= pci_controller_root
; p
; p
= p
->next
) {
1145 if (p
->pbm_A
.portid
== upa_portid
) {
1146 is_pbm_a
= (p
->pbm_A
.prom_node
== NULL
);
1147 psycho_pbm_init(p
, dp
, is_pbm_a
);
1152 p
= kzalloc(sizeof(struct pci_controller_info
), GFP_ATOMIC
);
1154 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1157 iommu
= kzalloc(sizeof(struct iommu
), GFP_ATOMIC
);
1159 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1162 p
->pbm_A
.iommu
= p
->pbm_B
.iommu
= iommu
;
1164 p
->next
= pci_controller_root
;
1165 pci_controller_root
= p
;
1167 p
->pbm_A
.portid
= upa_portid
;
1168 p
->pbm_B
.portid
= upa_portid
;
1169 p
->index
= pci_num_controllers
++;
1170 p
->scan_bus
= psycho_scan_bus
;
1171 p
->pci_ops
= &psycho_ops
;
1173 prop
= of_find_property(dp
, "reg", NULL
);
1174 pr_regs
= prop
->value
;
1176 p
->pbm_A
.controller_regs
= pr_regs
[2].phys_addr
;
1177 p
->pbm_B
.controller_regs
= pr_regs
[2].phys_addr
;
1179 p
->pbm_A
.config_space
= p
->pbm_B
.config_space
=
1180 (pr_regs
[2].phys_addr
+ PSYCHO_CONFIGSPACE
);
1183 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1184 * we need to adjust our MEM space mask.
1186 pci_memspace_mask
= 0x7fffffffUL
;
1188 psycho_controller_hwinit(p
);
1190 psycho_iommu_init(p
);
1192 is_pbm_a
= ((pr_regs
[0].phys_addr
& 0x6000) == 0x2000);
1193 psycho_pbm_init(p
, dp
, is_pbm_a
);