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[deliverable/linux.git] / arch / sparc64 / kernel / pci_sabre.c
1 /* pci_sabre.c: Sabre specific PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/apb.h>
16 #include <asm/pbm.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/smp.h>
20 #include <asm/oplib.h>
21 #include <asm/prom.h>
22
23 #include "pci_impl.h"
24 #include "iommu_common.h"
25
26 /* All SABRE registers are 64-bits. The following accessor
27 * routines are how they are accessed. The REG parameter
28 * is a physical address.
29 */
30 #define sabre_read(__reg) \
31 ({ u64 __ret; \
32 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "=r" (__ret) \
34 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35 : "memory"); \
36 __ret; \
37 })
38 #define sabre_write(__reg, __val) \
39 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : /* no outputs */ \
41 : "r" (__val), "r" (__reg), \
42 "i" (ASI_PHYS_BYPASS_EC_E) \
43 : "memory")
44
45 /* SABRE PCI controller register offsets and definitions. */
46 #define SABRE_UE_AFSR 0x0030UL
47 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
48 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
49 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
50 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
51 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
52 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
53 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
54 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
55 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
56 #define SABRE_UECE_AFAR 0x0038UL
57 #define SABRE_CE_AFSR 0x0040UL
58 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
59 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
60 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
61 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
62 #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
63 #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
64 #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
65 #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
66 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
67 #define SABRE_IOMMU_CONTROL 0x0200UL
68 #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
69 #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
70 #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
71 #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
72 #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
73 #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
74 #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
75 #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
76 #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
77 #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
78 #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
79 #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
80 #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
81 #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
82 #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
83 #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
84 #define SABRE_IOMMU_TSBBASE 0x0208UL
85 #define SABRE_IOMMU_FLUSH 0x0210UL
86 #define SABRE_IMAP_A_SLOT0 0x0c00UL
87 #define SABRE_IMAP_B_SLOT0 0x0c20UL
88 #define SABRE_IMAP_SCSI 0x1000UL
89 #define SABRE_IMAP_ETH 0x1008UL
90 #define SABRE_IMAP_BPP 0x1010UL
91 #define SABRE_IMAP_AU_REC 0x1018UL
92 #define SABRE_IMAP_AU_PLAY 0x1020UL
93 #define SABRE_IMAP_PFAIL 0x1028UL
94 #define SABRE_IMAP_KMS 0x1030UL
95 #define SABRE_IMAP_FLPY 0x1038UL
96 #define SABRE_IMAP_SHW 0x1040UL
97 #define SABRE_IMAP_KBD 0x1048UL
98 #define SABRE_IMAP_MS 0x1050UL
99 #define SABRE_IMAP_SER 0x1058UL
100 #define SABRE_IMAP_UE 0x1070UL
101 #define SABRE_IMAP_CE 0x1078UL
102 #define SABRE_IMAP_PCIERR 0x1080UL
103 #define SABRE_IMAP_GFX 0x1098UL
104 #define SABRE_IMAP_EUPA 0x10a0UL
105 #define SABRE_ICLR_A_SLOT0 0x1400UL
106 #define SABRE_ICLR_B_SLOT0 0x1480UL
107 #define SABRE_ICLR_SCSI 0x1800UL
108 #define SABRE_ICLR_ETH 0x1808UL
109 #define SABRE_ICLR_BPP 0x1810UL
110 #define SABRE_ICLR_AU_REC 0x1818UL
111 #define SABRE_ICLR_AU_PLAY 0x1820UL
112 #define SABRE_ICLR_PFAIL 0x1828UL
113 #define SABRE_ICLR_KMS 0x1830UL
114 #define SABRE_ICLR_FLPY 0x1838UL
115 #define SABRE_ICLR_SHW 0x1840UL
116 #define SABRE_ICLR_KBD 0x1848UL
117 #define SABRE_ICLR_MS 0x1850UL
118 #define SABRE_ICLR_SER 0x1858UL
119 #define SABRE_ICLR_UE 0x1870UL
120 #define SABRE_ICLR_CE 0x1878UL
121 #define SABRE_ICLR_PCIERR 0x1880UL
122 #define SABRE_WRSYNC 0x1c20UL
123 #define SABRE_PCICTRL 0x2000UL
124 #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
125 #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
126 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
127 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
128 #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
129 #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
130 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
131 #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
132 #define SABRE_PIOAFSR 0x2010UL
133 #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
134 #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
135 #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
136 #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
137 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
138 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
139 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
140 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
141 #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
142 #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
143 #define SABRE_PIOAFAR 0x2018UL
144 #define SABRE_PCIDIAG 0x2020UL
145 #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
146 #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
147 #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
148 #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
149 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
150 #define SABRE_PCITASR 0x2028UL
151 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
152 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
153 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
154 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
155 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
156 #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
157 #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
158 #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
159 #define SABRE_PIOBUF_DIAG 0x5000UL
160 #define SABRE_DMABUF_DIAGLO 0x5100UL
161 #define SABRE_DMABUF_DIAGHI 0x51c0UL
162 #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
163 #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
164 #define SABRE_IOMMU_VADIAG 0xa400UL
165 #define SABRE_IOMMU_TCDIAG 0xa408UL
166 #define SABRE_IOMMU_TAG 0xa580UL
167 #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
168 #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
169 #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
170 #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
171 #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
172 #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
173 #define SABRE_IOMMU_DATA 0xa600UL
174 #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
175 #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
176 #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
177 #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
178 #define SABRE_PCI_IRQSTATE 0xa800UL
179 #define SABRE_OBIO_IRQSTATE 0xa808UL
180 #define SABRE_FFBCFG 0xf000UL
181 #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
182 #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
183 #define SABRE_MCCTRL0 0xf010UL
184 #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
185 #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
186 #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
187 #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
188 #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
189 #define SABRE_MCCTRL1 0xf018UL
190 #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
191 #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
192 #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
193 #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
194 #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
195 #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
196 #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
197 #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
198 #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
199 #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
200 #define SABRE_RESETCTRL 0xf020UL
201
202 #define SABRE_CONFIGSPACE 0x001000000UL
203 #define SABRE_IOSPACE 0x002000000UL
204 #define SABRE_IOSPACE_SIZE 0x000ffffffUL
205 #define SABRE_MEMSPACE 0x100000000UL
206 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
207
208 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
209 * configuration space address format:
210 *
211 * 32 24 23 16 15 11 10 8 7 2 1 0
212 * ---------------------------------------------------------
213 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
214 * ---------------------------------------------------------
215 */
216 #define SABRE_CONFIG_BASE(PBM) \
217 ((PBM)->config_space | (1UL << 24))
218 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
219 (((unsigned long)(BUS) << 16) | \
220 ((unsigned long)(DEVFN) << 8) | \
221 ((unsigned long)(REG)))
222
223 static int hummingbird_p;
224 static struct pci_bus *sabre_root_bus;
225
226 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
227 unsigned char bus,
228 unsigned int devfn,
229 int where)
230 {
231 if (!pbm)
232 return NULL;
233 return (void *)
234 (SABRE_CONFIG_BASE(pbm) |
235 SABRE_CONFIG_ENCODE(bus, devfn, where));
236 }
237
238 static int sabre_out_of_range(unsigned char devfn)
239 {
240 if (hummingbird_p)
241 return 0;
242
243 return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
244 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
245 (PCI_SLOT(devfn) > 1));
246 }
247
248 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
249 unsigned char bus,
250 unsigned char devfn)
251 {
252 if (hummingbird_p)
253 return 0;
254
255 return ((pbm->parent == 0) ||
256 ((pbm == &pbm->parent->pbm_A) &&
257 (bus == pbm->pci_first_busno) &&
258 PCI_SLOT(devfn) > 8));
259 }
260
261 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
262 int where, int size, u32 *value)
263 {
264 struct pci_pbm_info *pbm = bus_dev->sysdata;
265 unsigned char bus = bus_dev->number;
266 u32 *addr;
267 u16 tmp16;
268 u8 tmp8;
269
270 switch (size) {
271 case 1:
272 *value = 0xff;
273 break;
274 case 2:
275 *value = 0xffff;
276 break;
277 case 4:
278 *value = 0xffffffff;
279 break;
280 }
281
282 addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
283 if (!addr)
284 return PCIBIOS_SUCCESSFUL;
285
286 if (__sabre_out_of_range(pbm, bus, devfn))
287 return PCIBIOS_SUCCESSFUL;
288
289 switch (size) {
290 case 1:
291 pci_config_read8((u8 *) addr, &tmp8);
292 *value = tmp8;
293 break;
294
295 case 2:
296 if (where & 0x01) {
297 printk("pci_read_config_word: misaligned reg [%x]\n",
298 where);
299 return PCIBIOS_SUCCESSFUL;
300 }
301 pci_config_read16((u16 *) addr, &tmp16);
302 *value = tmp16;
303 break;
304
305 case 4:
306 if (where & 0x03) {
307 printk("pci_read_config_dword: misaligned reg [%x]\n",
308 where);
309 return PCIBIOS_SUCCESSFUL;
310 }
311 pci_config_read32(addr, value);
312 break;
313 }
314
315 return PCIBIOS_SUCCESSFUL;
316 }
317
318 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
319 int where, int size, u32 *value)
320 {
321 struct pci_pbm_info *pbm = bus->sysdata;
322
323 if (bus == pbm->pci_bus && devfn == 0x00)
324 return pci_host_bridge_read_pci_cfg(bus, devfn, where,
325 size, value);
326
327 if (!bus->number && sabre_out_of_range(devfn)) {
328 switch (size) {
329 case 1:
330 *value = 0xff;
331 break;
332 case 2:
333 *value = 0xffff;
334 break;
335 case 4:
336 *value = 0xffffffff;
337 break;
338 }
339 return PCIBIOS_SUCCESSFUL;
340 }
341
342 if (bus->number || PCI_SLOT(devfn))
343 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
344
345 /* When accessing PCI config space of the PCI controller itself (bus
346 * 0, device slot 0, function 0) there are restrictions. Each
347 * register must be accessed as it's natural size. Thus, for example
348 * the Vendor ID must be accessed as a 16-bit quantity.
349 */
350
351 switch (size) {
352 case 1:
353 if (where < 8) {
354 u32 tmp32;
355 u16 tmp16;
356
357 __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
358 tmp16 = (u16) tmp32;
359 if (where & 1)
360 *value = tmp16 >> 8;
361 else
362 *value = tmp16 & 0xff;
363 } else
364 return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
365 break;
366
367 case 2:
368 if (where < 8)
369 return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
370 else {
371 u32 tmp32;
372 u8 tmp8;
373
374 __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
375 tmp8 = (u8) tmp32;
376 *value = tmp8;
377 __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
378 tmp8 = (u8) tmp32;
379 *value |= tmp8 << 8;
380 }
381 break;
382
383 case 4: {
384 u32 tmp32;
385 u16 tmp16;
386
387 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
388 tmp16 = (u16) tmp32;
389 *value = tmp16;
390 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
391 tmp16 = (u16) tmp32;
392 *value |= tmp16 << 16;
393 break;
394 }
395 }
396 return PCIBIOS_SUCCESSFUL;
397 }
398
399 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
400 int where, int size, u32 value)
401 {
402 struct pci_pbm_info *pbm = bus_dev->sysdata;
403 unsigned char bus = bus_dev->number;
404 u32 *addr;
405
406 addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
407 if (!addr)
408 return PCIBIOS_SUCCESSFUL;
409
410 if (__sabre_out_of_range(pbm, bus, devfn))
411 return PCIBIOS_SUCCESSFUL;
412
413 switch (size) {
414 case 1:
415 pci_config_write8((u8 *) addr, value);
416 break;
417
418 case 2:
419 if (where & 0x01) {
420 printk("pci_write_config_word: misaligned reg [%x]\n",
421 where);
422 return PCIBIOS_SUCCESSFUL;
423 }
424 pci_config_write16((u16 *) addr, value);
425 break;
426
427 case 4:
428 if (where & 0x03) {
429 printk("pci_write_config_dword: misaligned reg [%x]\n",
430 where);
431 return PCIBIOS_SUCCESSFUL;
432 }
433 pci_config_write32(addr, value);
434 break;
435 }
436
437 return PCIBIOS_SUCCESSFUL;
438 }
439
440 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
441 int where, int size, u32 value)
442 {
443 struct pci_pbm_info *pbm = bus->sysdata;
444
445 if (bus == pbm->pci_bus && devfn == 0x00)
446 return pci_host_bridge_write_pci_cfg(bus, devfn, where,
447 size, value);
448
449 if (bus->number)
450 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
451
452 if (sabre_out_of_range(devfn))
453 return PCIBIOS_SUCCESSFUL;
454
455 switch (size) {
456 case 1:
457 if (where < 8) {
458 u32 tmp32;
459 u16 tmp16;
460
461 __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
462 tmp16 = (u16) tmp32;
463 if (where & 1) {
464 value &= 0x00ff;
465 value |= tmp16 << 8;
466 } else {
467 value &= 0xff00;
468 value |= tmp16;
469 }
470 tmp32 = (u32) tmp16;
471 return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
472 } else
473 return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
474 break;
475 case 2:
476 if (where < 8)
477 return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
478 else {
479 __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
480 __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
481 }
482 break;
483 case 4:
484 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
485 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
486 break;
487 }
488 return PCIBIOS_SUCCESSFUL;
489 }
490
491 static struct pci_ops sabre_ops = {
492 .read = sabre_read_pci_cfg,
493 .write = sabre_write_pci_cfg,
494 };
495
496 /* SABRE error handling support. */
497 static void sabre_check_iommu_error(struct pci_controller_info *p,
498 unsigned long afsr,
499 unsigned long afar)
500 {
501 struct iommu *iommu = p->pbm_A.iommu;
502 unsigned long iommu_tag[16];
503 unsigned long iommu_data[16];
504 unsigned long flags;
505 u64 control;
506 int i;
507
508 spin_lock_irqsave(&iommu->lock, flags);
509 control = sabre_read(iommu->iommu_control);
510 if (control & SABRE_IOMMUCTRL_ERR) {
511 char *type_string;
512
513 /* Clear the error encountered bit.
514 * NOTE: On Sabre this is write 1 to clear,
515 * which is different from Psycho.
516 */
517 sabre_write(iommu->iommu_control, control);
518 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
519 case 1:
520 type_string = "Invalid Error";
521 break;
522 case 3:
523 type_string = "ECC Error";
524 break;
525 default:
526 type_string = "Unknown";
527 break;
528 };
529 printk("SABRE%d: IOMMU Error, type[%s]\n",
530 p->index, type_string);
531
532 /* Enter diagnostic mode and probe for error'd
533 * entries in the IOTLB.
534 */
535 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
536 sabre_write(iommu->iommu_control,
537 (control | SABRE_IOMMUCTRL_DENAB));
538 for (i = 0; i < 16; i++) {
539 unsigned long base = p->pbm_A.controller_regs;
540
541 iommu_tag[i] =
542 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
543 iommu_data[i] =
544 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
545 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
546 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
547 }
548 sabre_write(iommu->iommu_control, control);
549
550 for (i = 0; i < 16; i++) {
551 unsigned long tag, data;
552
553 tag = iommu_tag[i];
554 if (!(tag & SABRE_IOMMUTAG_ERR))
555 continue;
556
557 data = iommu_data[i];
558 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
559 case 1:
560 type_string = "Invalid Error";
561 break;
562 case 3:
563 type_string = "ECC Error";
564 break;
565 default:
566 type_string = "Unknown";
567 break;
568 };
569 printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
570 p->index, i, tag, type_string,
571 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
572 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
573 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
574 printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
575 p->index, i, data,
576 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
577 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
578 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
579 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
580 }
581 }
582 spin_unlock_irqrestore(&iommu->lock, flags);
583 }
584
585 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
586 {
587 struct pci_controller_info *p = dev_id;
588 unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
589 unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
590 unsigned long afsr, afar, error_bits;
591 int reported;
592
593 /* Latch uncorrectable error status. */
594 afar = sabre_read(afar_reg);
595 afsr = sabre_read(afsr_reg);
596
597 /* Clear the primary/secondary error status bits. */
598 error_bits = afsr &
599 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
600 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
601 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
602 if (!error_bits)
603 return IRQ_NONE;
604 sabre_write(afsr_reg, error_bits);
605
606 /* Log the error. */
607 printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
608 p->index,
609 ((error_bits & SABRE_UEAFSR_PDRD) ?
610 "DMA Read" :
611 ((error_bits & SABRE_UEAFSR_PDWR) ?
612 "DMA Write" : "???")),
613 ((error_bits & SABRE_UEAFSR_PDTE) ?
614 ":Translation Error" : ""));
615 printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
616 p->index,
617 (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
618 (afsr & SABRE_UEAFSR_OFF) >> 29UL,
619 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
620 printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
621 printk("SABRE%d: UE Secondary errors [", p->index);
622 reported = 0;
623 if (afsr & SABRE_UEAFSR_SDRD) {
624 reported++;
625 printk("(DMA Read)");
626 }
627 if (afsr & SABRE_UEAFSR_SDWR) {
628 reported++;
629 printk("(DMA Write)");
630 }
631 if (afsr & SABRE_UEAFSR_SDTE) {
632 reported++;
633 printk("(Translation Error)");
634 }
635 if (!reported)
636 printk("(none)");
637 printk("]\n");
638
639 /* Interrogate IOMMU for error status. */
640 sabre_check_iommu_error(p, afsr, afar);
641
642 return IRQ_HANDLED;
643 }
644
645 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
646 {
647 struct pci_controller_info *p = dev_id;
648 unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
649 unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
650 unsigned long afsr, afar, error_bits;
651 int reported;
652
653 /* Latch error status. */
654 afar = sabre_read(afar_reg);
655 afsr = sabre_read(afsr_reg);
656
657 /* Clear primary/secondary error status bits. */
658 error_bits = afsr &
659 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
660 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
661 if (!error_bits)
662 return IRQ_NONE;
663 sabre_write(afsr_reg, error_bits);
664
665 /* Log the error. */
666 printk("SABRE%d: Correctable Error, primary error type[%s]\n",
667 p->index,
668 ((error_bits & SABRE_CEAFSR_PDRD) ?
669 "DMA Read" :
670 ((error_bits & SABRE_CEAFSR_PDWR) ?
671 "DMA Write" : "???")));
672
673 /* XXX Use syndrome and afar to print out module string just like
674 * XXX UDB CE trap handler does... -DaveM
675 */
676 printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
677 "was_block(%d)\n",
678 p->index,
679 (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
680 (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
681 (afsr & SABRE_CEAFSR_OFF) >> 29UL,
682 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
683 printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
684 printk("SABRE%d: CE Secondary errors [", p->index);
685 reported = 0;
686 if (afsr & SABRE_CEAFSR_SDRD) {
687 reported++;
688 printk("(DMA Read)");
689 }
690 if (afsr & SABRE_CEAFSR_SDWR) {
691 reported++;
692 printk("(DMA Write)");
693 }
694 if (!reported)
695 printk("(none)");
696 printk("]\n");
697
698 return IRQ_HANDLED;
699 }
700
701 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
702 {
703 unsigned long csr_reg, csr, csr_error_bits;
704 irqreturn_t ret = IRQ_NONE;
705 u16 stat;
706
707 csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
708 csr = sabre_read(csr_reg);
709 csr_error_bits =
710 csr & SABRE_PCICTRL_SERR;
711 if (csr_error_bits) {
712 /* Clear the errors. */
713 sabre_write(csr_reg, csr);
714
715 /* Log 'em. */
716 if (csr_error_bits & SABRE_PCICTRL_SERR)
717 printk("SABRE%d: PCI SERR signal asserted.\n",
718 p->index);
719 ret = IRQ_HANDLED;
720 }
721 pci_bus_read_config_word(sabre_root_bus, 0,
722 PCI_STATUS, &stat);
723 if (stat & (PCI_STATUS_PARITY |
724 PCI_STATUS_SIG_TARGET_ABORT |
725 PCI_STATUS_REC_TARGET_ABORT |
726 PCI_STATUS_REC_MASTER_ABORT |
727 PCI_STATUS_SIG_SYSTEM_ERROR)) {
728 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
729 p->index, stat);
730 pci_bus_write_config_word(sabre_root_bus, 0,
731 PCI_STATUS, 0xffff);
732 ret = IRQ_HANDLED;
733 }
734 return ret;
735 }
736
737 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
738 {
739 struct pci_controller_info *p = dev_id;
740 unsigned long afsr_reg, afar_reg;
741 unsigned long afsr, afar, error_bits;
742 int reported;
743
744 afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
745 afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
746
747 /* Latch error status. */
748 afar = sabre_read(afar_reg);
749 afsr = sabre_read(afsr_reg);
750
751 /* Clear primary/secondary error status bits. */
752 error_bits = afsr &
753 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
754 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
755 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
756 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
757 if (!error_bits)
758 return sabre_pcierr_intr_other(p);
759 sabre_write(afsr_reg, error_bits);
760
761 /* Log the error. */
762 printk("SABRE%d: PCI Error, primary error type[%s]\n",
763 p->index,
764 (((error_bits & SABRE_PIOAFSR_PMA) ?
765 "Master Abort" :
766 ((error_bits & SABRE_PIOAFSR_PTA) ?
767 "Target Abort" :
768 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
769 "Excessive Retries" :
770 ((error_bits & SABRE_PIOAFSR_PPERR) ?
771 "Parity Error" : "???"))))));
772 printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
773 p->index,
774 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
775 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
776 printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
777 printk("SABRE%d: PCI Secondary errors [", p->index);
778 reported = 0;
779 if (afsr & SABRE_PIOAFSR_SMA) {
780 reported++;
781 printk("(Master Abort)");
782 }
783 if (afsr & SABRE_PIOAFSR_STA) {
784 reported++;
785 printk("(Target Abort)");
786 }
787 if (afsr & SABRE_PIOAFSR_SRTRY) {
788 reported++;
789 printk("(Excessive Retries)");
790 }
791 if (afsr & SABRE_PIOAFSR_SPERR) {
792 reported++;
793 printk("(Parity Error)");
794 }
795 if (!reported)
796 printk("(none)");
797 printk("]\n");
798
799 /* For the error types shown, scan both PCI buses for devices
800 * which have logged that error type.
801 */
802
803 /* If we see a Target Abort, this could be the result of an
804 * IOMMU translation error of some sort. It is extremely
805 * useful to log this information as usually it indicates
806 * a bug in the IOMMU support code or a PCI device driver.
807 */
808 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
809 sabre_check_iommu_error(p, afsr, afar);
810 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
811 }
812 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
813 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
814
815 /* For excessive retries, SABRE/PBM will abort the device
816 * and there is no way to specifically check for excessive
817 * retries in the config space status registers. So what
818 * we hope is that we'll catch it via the master/target
819 * abort events.
820 */
821
822 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
823 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
824
825 return IRQ_HANDLED;
826 }
827
828 static void sabre_register_error_handlers(struct pci_controller_info *p)
829 {
830 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
831 struct device_node *dp = pbm->prom_node;
832 struct of_device *op;
833 unsigned long base = pbm->controller_regs;
834 u64 tmp;
835
836 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
837 dp = dp->parent;
838
839 op = of_find_device_by_node(dp);
840 if (!op)
841 return;
842
843 /* Sabre/Hummingbird IRQ property layout is:
844 * 0: PCI ERR
845 * 1: UE ERR
846 * 2: CE ERR
847 * 3: POWER FAIL
848 */
849 if (op->num_irqs < 4)
850 return;
851
852 /* We clear the error bits in the appropriate AFSR before
853 * registering the handler so that we don't get spurious
854 * interrupts.
855 */
856 sabre_write(base + SABRE_UE_AFSR,
857 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
858 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
859 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
860
861 request_irq(op->irqs[1], sabre_ue_intr, IRQF_SHARED, "SABRE UE", p);
862
863 sabre_write(base + SABRE_CE_AFSR,
864 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
865 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
866
867 request_irq(op->irqs[2], sabre_ce_intr, IRQF_SHARED, "SABRE CE", p);
868 request_irq(op->irqs[0], sabre_pcierr_intr, IRQF_SHARED,
869 "SABRE PCIERR", p);
870
871 tmp = sabre_read(base + SABRE_PCICTRL);
872 tmp |= SABRE_PCICTRL_ERREN;
873 sabre_write(base + SABRE_PCICTRL, tmp);
874 }
875
876 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
877 {
878 struct pci_dev *pdev;
879
880 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
881 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
882 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
883 u16 word16;
884
885 pci_read_config_word(pdev, PCI_COMMAND, &word16);
886 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
887 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
888 PCI_COMMAND_IO;
889 pci_write_config_word(pdev, PCI_COMMAND, word16);
890
891 /* Status register bits are "write 1 to clear". */
892 pci_write_config_word(pdev, PCI_STATUS, 0xffff);
893 pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
894
895 /* Use a primary/seconday latency timer value
896 * of 64.
897 */
898 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
899 pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
900
901 /* Enable reporting/forwarding of master aborts,
902 * parity, and SERR.
903 */
904 pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
905 (PCI_BRIDGE_CTL_PARITY |
906 PCI_BRIDGE_CTL_SERR |
907 PCI_BRIDGE_CTL_MASTER_ABORT));
908 }
909 }
910 }
911
912 static void sabre_scan_bus(struct pci_controller_info *p)
913 {
914 static int once;
915 struct pci_bus *pbus;
916
917 /* The APB bridge speaks to the Sabre host PCI bridge
918 * at 66Mhz, but the front side of APB runs at 33Mhz
919 * for both segments.
920 */
921 p->pbm_A.is_66mhz_capable = 0;
922
923 /* This driver has not been verified to handle
924 * multiple SABREs yet, so trap this.
925 *
926 * Also note that the SABRE host bridge is hardwired
927 * to live at bus 0.
928 */
929 if (once != 0) {
930 prom_printf("SABRE: Multiple controllers unsupported.\n");
931 prom_halt();
932 }
933 once++;
934
935 pbus = pci_scan_one_pbm(&p->pbm_A);
936 if (!pbus)
937 return;
938
939 sabre_root_bus = pbus;
940
941 apb_init(p, pbus);
942
943 sabre_register_error_handlers(p);
944 }
945
946 static void sabre_iommu_init(struct pci_controller_info *p,
947 int tsbsize, unsigned long dvma_offset,
948 u32 dma_mask)
949 {
950 struct iommu *iommu = p->pbm_A.iommu;
951 unsigned long i;
952 u64 control;
953
954 /* Register addresses. */
955 iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
956 iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
957 iommu->iommu_flush = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
958 iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
959 /* Sabre's IOMMU lacks ctx flushing. */
960 iommu->iommu_ctxflush = 0;
961
962 /* Invalidate TLB Entries. */
963 control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
964 control |= SABRE_IOMMUCTRL_DENAB;
965 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
966
967 for(i = 0; i < 16; i++) {
968 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
969 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
970 }
971
972 /* Leave diag mode enabled for full-flushing done
973 * in pci_iommu.c
974 */
975 pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
976
977 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
978 __pa(iommu->page_table));
979
980 control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
981 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
982 control |= SABRE_IOMMUCTRL_ENAB;
983 switch(tsbsize) {
984 case 64:
985 control |= SABRE_IOMMU_TSBSZ_64K;
986 break;
987 case 128:
988 control |= SABRE_IOMMU_TSBSZ_128K;
989 break;
990 default:
991 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
992 prom_halt();
993 break;
994 }
995 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
996 }
997
998 static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp)
999 {
1000 struct pci_pbm_info *pbm;
1001
1002 pbm = &p->pbm_A;
1003 pbm->name = dp->full_name;
1004 printk("%s: SABRE PCI Bus Module\n", pbm->name);
1005
1006 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1007 pbm->parent = p;
1008 pbm->prom_node = dp;
1009 pbm->pci_first_busno = p->pci_first_busno;
1010 pbm->pci_last_busno = p->pci_last_busno;
1011
1012 pci_determine_mem_io_space(pbm);
1013 }
1014
1015 void sabre_init(struct device_node *dp, char *model_name)
1016 {
1017 const struct linux_prom64_registers *pr_regs;
1018 struct pci_controller_info *p;
1019 struct iommu *iommu;
1020 int tsbsize;
1021 const u32 *busrange;
1022 const u32 *vdma;
1023 u32 upa_portid, dma_mask;
1024 u64 clear_irq;
1025
1026 hummingbird_p = 0;
1027 if (!strcmp(model_name, "pci108e,a001"))
1028 hummingbird_p = 1;
1029 else if (!strcmp(model_name, "SUNW,sabre")) {
1030 const char *compat = of_get_property(dp, "compatible", NULL);
1031 if (compat && !strcmp(compat, "pci108e,a001"))
1032 hummingbird_p = 1;
1033 if (!hummingbird_p) {
1034 struct device_node *dp;
1035
1036 /* Of course, Sun has to encode things a thousand
1037 * different ways, inconsistently.
1038 */
1039 cpu_find_by_instance(0, &dp, NULL);
1040 if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
1041 hummingbird_p = 1;
1042 }
1043 }
1044
1045 p = kzalloc(sizeof(*p), GFP_ATOMIC);
1046 if (!p) {
1047 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1048 prom_halt();
1049 }
1050
1051 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1052 if (!iommu) {
1053 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1054 prom_halt();
1055 }
1056 p->pbm_A.iommu = iommu;
1057
1058 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1059
1060 p->next = pci_controller_root;
1061 pci_controller_root = p;
1062
1063 p->pbm_A.portid = upa_portid;
1064 p->index = pci_num_controllers++;
1065 p->scan_bus = sabre_scan_bus;
1066 p->pci_ops = &sabre_ops;
1067
1068 /*
1069 * Map in SABRE register set and report the presence of this SABRE.
1070 */
1071
1072 pr_regs = of_get_property(dp, "reg", NULL);
1073
1074 /*
1075 * First REG in property is base of entire SABRE register space.
1076 */
1077 p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1078
1079 /* Clear interrupts */
1080
1081 /* PCI first */
1082 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1083 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1084
1085 /* Then OBIO */
1086 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1087 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1088
1089 /* Error interrupts are enabled later after the bus scan. */
1090 sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1091 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
1092 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1093
1094 /* Now map in PCI config space for entire SABRE. */
1095 p->pbm_A.config_space =
1096 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1097
1098 vdma = of_get_property(dp, "virtual-dma", NULL);
1099
1100 dma_mask = vdma[0];
1101 switch(vdma[1]) {
1102 case 0x20000000:
1103 dma_mask |= 0x1fffffff;
1104 tsbsize = 64;
1105 break;
1106 case 0x40000000:
1107 dma_mask |= 0x3fffffff;
1108 tsbsize = 128;
1109 break;
1110
1111 case 0x80000000:
1112 dma_mask |= 0x7fffffff;
1113 tsbsize = 128;
1114 break;
1115 default:
1116 prom_printf("SABRE: strange virtual-dma size.\n");
1117 prom_halt();
1118 }
1119
1120 sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1121
1122 busrange = of_get_property(dp, "bus-range", NULL);
1123 p->pci_first_busno = busrange[0];
1124 p->pci_last_busno = busrange[1];
1125
1126 /*
1127 * Look for APB underneath.
1128 */
1129 sabre_pbm_init(p, dp);
1130 }
Linux kernel - Deliverables
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