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[SPARC64]: Fix new context version SMP handling.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_sabre.c
1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
2 * pci_sabre.c: Sabre specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
15
16 #include <asm/apb.h>
17 #include <asm/pbm.h>
18 #include <asm/iommu.h>
19 #include <asm/irq.h>
20 #include <asm/smp.h>
21 #include <asm/oplib.h>
22
23 #include "pci_impl.h"
24 #include "iommu_common.h"
25
26 /* All SABRE registers are 64-bits. The following accessor
27 * routines are how they are accessed. The REG parameter
28 * is a physical address.
29 */
30 #define sabre_read(__reg) \
31 ({ u64 __ret; \
32 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "=r" (__ret) \
34 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35 : "memory"); \
36 __ret; \
37 })
38 #define sabre_write(__reg, __val) \
39 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : /* no outputs */ \
41 : "r" (__val), "r" (__reg), \
42 "i" (ASI_PHYS_BYPASS_EC_E) \
43 : "memory")
44
45 /* SABRE PCI controller register offsets and definitions. */
46 #define SABRE_UE_AFSR 0x0030UL
47 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
48 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
49 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
50 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
51 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
52 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
53 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
54 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
55 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
56 #define SABRE_UECE_AFAR 0x0038UL
57 #define SABRE_CE_AFSR 0x0040UL
58 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
59 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
60 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
61 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
62 #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
63 #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
64 #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
65 #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
66 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
67 #define SABRE_IOMMU_CONTROL 0x0200UL
68 #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
69 #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
70 #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
71 #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
72 #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
73 #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
74 #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
75 #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
76 #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
77 #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
78 #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
79 #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
80 #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
81 #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
82 #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
83 #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
84 #define SABRE_IOMMU_TSBBASE 0x0208UL
85 #define SABRE_IOMMU_FLUSH 0x0210UL
86 #define SABRE_IMAP_A_SLOT0 0x0c00UL
87 #define SABRE_IMAP_B_SLOT0 0x0c20UL
88 #define SABRE_IMAP_SCSI 0x1000UL
89 #define SABRE_IMAP_ETH 0x1008UL
90 #define SABRE_IMAP_BPP 0x1010UL
91 #define SABRE_IMAP_AU_REC 0x1018UL
92 #define SABRE_IMAP_AU_PLAY 0x1020UL
93 #define SABRE_IMAP_PFAIL 0x1028UL
94 #define SABRE_IMAP_KMS 0x1030UL
95 #define SABRE_IMAP_FLPY 0x1038UL
96 #define SABRE_IMAP_SHW 0x1040UL
97 #define SABRE_IMAP_KBD 0x1048UL
98 #define SABRE_IMAP_MS 0x1050UL
99 #define SABRE_IMAP_SER 0x1058UL
100 #define SABRE_IMAP_UE 0x1070UL
101 #define SABRE_IMAP_CE 0x1078UL
102 #define SABRE_IMAP_PCIERR 0x1080UL
103 #define SABRE_IMAP_GFX 0x1098UL
104 #define SABRE_IMAP_EUPA 0x10a0UL
105 #define SABRE_ICLR_A_SLOT0 0x1400UL
106 #define SABRE_ICLR_B_SLOT0 0x1480UL
107 #define SABRE_ICLR_SCSI 0x1800UL
108 #define SABRE_ICLR_ETH 0x1808UL
109 #define SABRE_ICLR_BPP 0x1810UL
110 #define SABRE_ICLR_AU_REC 0x1818UL
111 #define SABRE_ICLR_AU_PLAY 0x1820UL
112 #define SABRE_ICLR_PFAIL 0x1828UL
113 #define SABRE_ICLR_KMS 0x1830UL
114 #define SABRE_ICLR_FLPY 0x1838UL
115 #define SABRE_ICLR_SHW 0x1840UL
116 #define SABRE_ICLR_KBD 0x1848UL
117 #define SABRE_ICLR_MS 0x1850UL
118 #define SABRE_ICLR_SER 0x1858UL
119 #define SABRE_ICLR_UE 0x1870UL
120 #define SABRE_ICLR_CE 0x1878UL
121 #define SABRE_ICLR_PCIERR 0x1880UL
122 #define SABRE_WRSYNC 0x1c20UL
123 #define SABRE_PCICTRL 0x2000UL
124 #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
125 #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
126 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
127 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
128 #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
129 #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
130 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
131 #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
132 #define SABRE_PIOAFSR 0x2010UL
133 #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
134 #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
135 #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
136 #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
137 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
138 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
139 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
140 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
141 #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
142 #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
143 #define SABRE_PIOAFAR 0x2018UL
144 #define SABRE_PCIDIAG 0x2020UL
145 #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
146 #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
147 #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
148 #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
149 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
150 #define SABRE_PCITASR 0x2028UL
151 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
152 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
153 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
154 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
155 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
156 #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
157 #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
158 #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
159 #define SABRE_PIOBUF_DIAG 0x5000UL
160 #define SABRE_DMABUF_DIAGLO 0x5100UL
161 #define SABRE_DMABUF_DIAGHI 0x51c0UL
162 #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
163 #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
164 #define SABRE_IOMMU_VADIAG 0xa400UL
165 #define SABRE_IOMMU_TCDIAG 0xa408UL
166 #define SABRE_IOMMU_TAG 0xa580UL
167 #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
168 #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
169 #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
170 #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
171 #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
172 #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
173 #define SABRE_IOMMU_DATA 0xa600UL
174 #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
175 #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
176 #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
177 #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
178 #define SABRE_PCI_IRQSTATE 0xa800UL
179 #define SABRE_OBIO_IRQSTATE 0xa808UL
180 #define SABRE_FFBCFG 0xf000UL
181 #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
182 #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
183 #define SABRE_MCCTRL0 0xf010UL
184 #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
185 #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
186 #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
187 #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
188 #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
189 #define SABRE_MCCTRL1 0xf018UL
190 #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
191 #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
192 #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
193 #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
194 #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
195 #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
196 #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
197 #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
198 #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
199 #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
200 #define SABRE_RESETCTRL 0xf020UL
201
202 #define SABRE_CONFIGSPACE 0x001000000UL
203 #define SABRE_IOSPACE 0x002000000UL
204 #define SABRE_IOSPACE_SIZE 0x000ffffffUL
205 #define SABRE_MEMSPACE 0x100000000UL
206 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
207
208 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
209 * configuration space address format:
210 *
211 * 32 24 23 16 15 11 10 8 7 2 1 0
212 * ---------------------------------------------------------
213 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
214 * ---------------------------------------------------------
215 */
216 #define SABRE_CONFIG_BASE(PBM) \
217 ((PBM)->config_space | (1UL << 24))
218 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
219 (((unsigned long)(BUS) << 16) | \
220 ((unsigned long)(DEVFN) << 8) | \
221 ((unsigned long)(REG)))
222
223 static int hummingbird_p;
224 static struct pci_bus *sabre_root_bus;
225
226 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
227 unsigned char bus,
228 unsigned int devfn,
229 int where)
230 {
231 if (!pbm)
232 return NULL;
233 return (void *)
234 (SABRE_CONFIG_BASE(pbm) |
235 SABRE_CONFIG_ENCODE(bus, devfn, where));
236 }
237
238 static int sabre_out_of_range(unsigned char devfn)
239 {
240 if (hummingbird_p)
241 return 0;
242
243 return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
244 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
245 (PCI_SLOT(devfn) > 1));
246 }
247
248 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
249 unsigned char bus,
250 unsigned char devfn)
251 {
252 if (hummingbird_p)
253 return 0;
254
255 return ((pbm->parent == 0) ||
256 ((pbm == &pbm->parent->pbm_B) &&
257 (bus == pbm->pci_first_busno) &&
258 PCI_SLOT(devfn) > 8) ||
259 ((pbm == &pbm->parent->pbm_A) &&
260 (bus == pbm->pci_first_busno) &&
261 PCI_SLOT(devfn) > 8));
262 }
263
264 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
265 int where, int size, u32 *value)
266 {
267 struct pci_pbm_info *pbm = bus_dev->sysdata;
268 unsigned char bus = bus_dev->number;
269 u32 *addr;
270 u16 tmp16;
271 u8 tmp8;
272
273 switch (size) {
274 case 1:
275 *value = 0xff;
276 break;
277 case 2:
278 *value = 0xffff;
279 break;
280 case 4:
281 *value = 0xffffffff;
282 break;
283 }
284
285 addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
286 if (!addr)
287 return PCIBIOS_SUCCESSFUL;
288
289 if (__sabre_out_of_range(pbm, bus, devfn))
290 return PCIBIOS_SUCCESSFUL;
291
292 switch (size) {
293 case 1:
294 pci_config_read8((u8 *) addr, &tmp8);
295 *value = tmp8;
296 break;
297
298 case 2:
299 if (where & 0x01) {
300 printk("pci_read_config_word: misaligned reg [%x]\n",
301 where);
302 return PCIBIOS_SUCCESSFUL;
303 }
304 pci_config_read16((u16 *) addr, &tmp16);
305 *value = tmp16;
306 break;
307
308 case 4:
309 if (where & 0x03) {
310 printk("pci_read_config_dword: misaligned reg [%x]\n",
311 where);
312 return PCIBIOS_SUCCESSFUL;
313 }
314 pci_config_read32(addr, value);
315 break;
316 }
317
318 return PCIBIOS_SUCCESSFUL;
319 }
320
321 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
322 int where, int size, u32 *value)
323 {
324 if (!bus->number && sabre_out_of_range(devfn)) {
325 switch (size) {
326 case 1:
327 *value = 0xff;
328 break;
329 case 2:
330 *value = 0xffff;
331 break;
332 case 4:
333 *value = 0xffffffff;
334 break;
335 }
336 return PCIBIOS_SUCCESSFUL;
337 }
338
339 if (bus->number || PCI_SLOT(devfn))
340 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
341
342 /* When accessing PCI config space of the PCI controller itself (bus
343 * 0, device slot 0, function 0) there are restrictions. Each
344 * register must be accessed as it's natural size. Thus, for example
345 * the Vendor ID must be accessed as a 16-bit quantity.
346 */
347
348 switch (size) {
349 case 1:
350 if (where < 8) {
351 u32 tmp32;
352 u16 tmp16;
353
354 __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
355 tmp16 = (u16) tmp32;
356 if (where & 1)
357 *value = tmp16 >> 8;
358 else
359 *value = tmp16 & 0xff;
360 } else
361 return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
362 break;
363
364 case 2:
365 if (where < 8)
366 return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
367 else {
368 u32 tmp32;
369 u8 tmp8;
370
371 __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
372 tmp8 = (u8) tmp32;
373 *value = tmp8;
374 __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
375 tmp8 = (u8) tmp32;
376 *value |= tmp8 << 8;
377 }
378 break;
379
380 case 4: {
381 u32 tmp32;
382 u16 tmp16;
383
384 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
385 tmp16 = (u16) tmp32;
386 *value = tmp16;
387 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
388 tmp16 = (u16) tmp32;
389 *value |= tmp16 << 16;
390 break;
391 }
392 }
393 return PCIBIOS_SUCCESSFUL;
394 }
395
396 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
397 int where, int size, u32 value)
398 {
399 struct pci_pbm_info *pbm = bus_dev->sysdata;
400 unsigned char bus = bus_dev->number;
401 u32 *addr;
402
403 addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
404 if (!addr)
405 return PCIBIOS_SUCCESSFUL;
406
407 if (__sabre_out_of_range(pbm, bus, devfn))
408 return PCIBIOS_SUCCESSFUL;
409
410 switch (size) {
411 case 1:
412 pci_config_write8((u8 *) addr, value);
413 break;
414
415 case 2:
416 if (where & 0x01) {
417 printk("pci_write_config_word: misaligned reg [%x]\n",
418 where);
419 return PCIBIOS_SUCCESSFUL;
420 }
421 pci_config_write16((u16 *) addr, value);
422 break;
423
424 case 4:
425 if (where & 0x03) {
426 printk("pci_write_config_dword: misaligned reg [%x]\n",
427 where);
428 return PCIBIOS_SUCCESSFUL;
429 }
430 pci_config_write32(addr, value);
431 break;
432 }
433
434 return PCIBIOS_SUCCESSFUL;
435 }
436
437 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
438 int where, int size, u32 value)
439 {
440 if (bus->number)
441 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
442
443 if (sabre_out_of_range(devfn))
444 return PCIBIOS_SUCCESSFUL;
445
446 switch (size) {
447 case 1:
448 if (where < 8) {
449 u32 tmp32;
450 u16 tmp16;
451
452 __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
453 tmp16 = (u16) tmp32;
454 if (where & 1) {
455 value &= 0x00ff;
456 value |= tmp16 << 8;
457 } else {
458 value &= 0xff00;
459 value |= tmp16;
460 }
461 tmp32 = (u32) tmp16;
462 return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
463 } else
464 return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
465 break;
466 case 2:
467 if (where < 8)
468 return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
469 else {
470 __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
471 __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
472 }
473 break;
474 case 4:
475 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
476 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
477 break;
478 }
479 return PCIBIOS_SUCCESSFUL;
480 }
481
482 static struct pci_ops sabre_ops = {
483 .read = sabre_read_pci_cfg,
484 .write = sabre_write_pci_cfg,
485 };
486
487 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
488 {
489 unsigned int bus = (ino & 0x10) >> 4;
490 unsigned int slot = (ino & 0x0c) >> 2;
491
492 if (bus == 0)
493 return SABRE_IMAP_A_SLOT0 + (slot * 8);
494 else
495 return SABRE_IMAP_B_SLOT0 + (slot * 8);
496 }
497
498 static unsigned long __onboard_imap_off[] = {
499 /*0x20*/ SABRE_IMAP_SCSI,
500 /*0x21*/ SABRE_IMAP_ETH,
501 /*0x22*/ SABRE_IMAP_BPP,
502 /*0x23*/ SABRE_IMAP_AU_REC,
503 /*0x24*/ SABRE_IMAP_AU_PLAY,
504 /*0x25*/ SABRE_IMAP_PFAIL,
505 /*0x26*/ SABRE_IMAP_KMS,
506 /*0x27*/ SABRE_IMAP_FLPY,
507 /*0x28*/ SABRE_IMAP_SHW,
508 /*0x29*/ SABRE_IMAP_KBD,
509 /*0x2a*/ SABRE_IMAP_MS,
510 /*0x2b*/ SABRE_IMAP_SER,
511 /*0x2c*/ 0 /* reserved */,
512 /*0x2d*/ 0 /* reserved */,
513 /*0x2e*/ SABRE_IMAP_UE,
514 /*0x2f*/ SABRE_IMAP_CE,
515 /*0x30*/ SABRE_IMAP_PCIERR,
516 };
517 #define SABRE_ONBOARD_IRQ_BASE 0x20
518 #define SABRE_ONBOARD_IRQ_LAST 0x30
519 #define sabre_onboard_imap_offset(__ino) \
520 __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
521
522 #define sabre_iclr_offset(ino) \
523 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
524 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
525
526 /* PCI SABRE INO number to Sparc PIL level. */
527 static unsigned char sabre_pil_table[] = {
528 /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
529 /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
530 /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
531 /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
532 /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
533 /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
534 /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
535 /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
536 /*0x20*/5, /* SCSI */
537 /*0x21*/5, /* Ethernet */
538 /*0x22*/8, /* Parallel Port */
539 /*0x23*/13, /* Audio Record */
540 /*0x24*/14, /* Audio Playback */
541 /*0x25*/15, /* PowerFail */
542 /*0x26*/5, /* second SCSI */
543 /*0x27*/11, /* Floppy */
544 /*0x28*/5, /* Spare Hardware */
545 /*0x29*/9, /* Keyboard */
546 /*0x2a*/5, /* Mouse */
547 /*0x2b*/12, /* Serial */
548 /*0x2c*/10, /* Timer 0 */
549 /*0x2d*/11, /* Timer 1 */
550 /*0x2e*/15, /* Uncorrectable ECC */
551 /*0x2f*/15, /* Correctable ECC */
552 /*0x30*/15, /* PCI Bus A Error */
553 /*0x31*/15, /* PCI Bus B Error */
554 /*0x32*/15, /* Power Management */
555 };
556
557 static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
558 {
559 int ret;
560
561 if (pdev &&
562 pdev->vendor == PCI_VENDOR_ID_SUN &&
563 pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
564 return 9;
565
566 ret = sabre_pil_table[ino];
567 if (ret == 0 && pdev == NULL) {
568 ret = 5;
569 } else if (ret == 0) {
570 switch ((pdev->class >> 16) & 0xff) {
571 case PCI_BASE_CLASS_STORAGE:
572 ret = 5;
573 break;
574
575 case PCI_BASE_CLASS_NETWORK:
576 ret = 6;
577 break;
578
579 case PCI_BASE_CLASS_DISPLAY:
580 ret = 9;
581 break;
582
583 case PCI_BASE_CLASS_MULTIMEDIA:
584 case PCI_BASE_CLASS_MEMORY:
585 case PCI_BASE_CLASS_BRIDGE:
586 case PCI_BASE_CLASS_SERIAL:
587 ret = 10;
588 break;
589
590 default:
591 ret = 5;
592 break;
593 };
594 }
595 return ret;
596 }
597
598 /* When a device lives behind a bridge deeper in the PCI bus topology
599 * than APB, a special sequence must run to make sure all pending DMA
600 * transfers at the time of IRQ delivery are visible in the coherency
601 * domain by the cpu. This sequence is to perform a read on the far
602 * side of the non-APB bridge, then perform a read of Sabre's DMA
603 * write-sync register.
604 */
605 static void sabre_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
606 {
607 struct pci_dev *pdev = _arg1;
608 unsigned long sync_reg = (unsigned long) _arg2;
609 u16 _unused;
610
611 pci_read_config_word(pdev, PCI_VENDOR_ID, &_unused);
612 sabre_read(sync_reg);
613 }
614
615 static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
616 struct pci_dev *pdev,
617 unsigned int ino)
618 {
619 struct ino_bucket *bucket;
620 unsigned long imap, iclr;
621 unsigned long imap_off, iclr_off;
622 int pil, inofixup = 0;
623
624 ino &= PCI_IRQ_INO;
625 if (ino < SABRE_ONBOARD_IRQ_BASE) {
626 /* PCI slot */
627 imap_off = sabre_pcislot_imap_offset(ino);
628 } else {
629 /* onboard device */
630 if (ino > SABRE_ONBOARD_IRQ_LAST) {
631 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
632 prom_halt();
633 }
634 imap_off = sabre_onboard_imap_offset(ino);
635 }
636
637 /* Now build the IRQ bucket. */
638 pil = sabre_ino_to_pil(pdev, ino);
639
640 if (PIL_RESERVED(pil))
641 BUG();
642
643 imap = pbm->controller_regs + imap_off;
644 imap += 4;
645
646 iclr_off = sabre_iclr_offset(ino);
647 iclr = pbm->controller_regs + iclr_off;
648 iclr += 4;
649
650 if ((ino & 0x20) == 0)
651 inofixup = ino & 0x03;
652
653 bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
654 bucket->flags |= IBF_PCI;
655
656 if (pdev) {
657 struct pcidev_cookie *pcp = pdev->sysdata;
658
659 if (pdev->bus->number != pcp->pbm->pci_first_busno) {
660 struct pci_controller_info *p = pcp->pbm->parent;
661 struct irq_desc *d = bucket->irq_info;
662
663 d->pre_handler = sabre_wsync_handler;
664 d->pre_handler_arg1 = pdev;
665 d->pre_handler_arg2 = (void *)
666 p->pbm_A.controller_regs + SABRE_WRSYNC;
667 }
668 }
669 return __irq(bucket);
670 }
671
672 /* SABRE error handling support. */
673 static void sabre_check_iommu_error(struct pci_controller_info *p,
674 unsigned long afsr,
675 unsigned long afar)
676 {
677 struct pci_iommu *iommu = p->pbm_A.iommu;
678 unsigned long iommu_tag[16];
679 unsigned long iommu_data[16];
680 unsigned long flags;
681 u64 control;
682 int i;
683
684 spin_lock_irqsave(&iommu->lock, flags);
685 control = sabre_read(iommu->iommu_control);
686 if (control & SABRE_IOMMUCTRL_ERR) {
687 char *type_string;
688
689 /* Clear the error encountered bit.
690 * NOTE: On Sabre this is write 1 to clear,
691 * which is different from Psycho.
692 */
693 sabre_write(iommu->iommu_control, control);
694 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
695 case 1:
696 type_string = "Invalid Error";
697 break;
698 case 3:
699 type_string = "ECC Error";
700 break;
701 default:
702 type_string = "Unknown";
703 break;
704 };
705 printk("SABRE%d: IOMMU Error, type[%s]\n",
706 p->index, type_string);
707
708 /* Enter diagnostic mode and probe for error'd
709 * entries in the IOTLB.
710 */
711 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
712 sabre_write(iommu->iommu_control,
713 (control | SABRE_IOMMUCTRL_DENAB));
714 for (i = 0; i < 16; i++) {
715 unsigned long base = p->pbm_A.controller_regs;
716
717 iommu_tag[i] =
718 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
719 iommu_data[i] =
720 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
721 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
722 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
723 }
724 sabre_write(iommu->iommu_control, control);
725
726 for (i = 0; i < 16; i++) {
727 unsigned long tag, data;
728
729 tag = iommu_tag[i];
730 if (!(tag & SABRE_IOMMUTAG_ERR))
731 continue;
732
733 data = iommu_data[i];
734 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
735 case 1:
736 type_string = "Invalid Error";
737 break;
738 case 3:
739 type_string = "ECC Error";
740 break;
741 default:
742 type_string = "Unknown";
743 break;
744 };
745 printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
746 p->index, i, tag, type_string,
747 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
748 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
749 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
750 printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
751 p->index, i, data,
752 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
753 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
754 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
755 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
756 }
757 }
758 spin_unlock_irqrestore(&iommu->lock, flags);
759 }
760
761 static irqreturn_t sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
762 {
763 struct pci_controller_info *p = dev_id;
764 unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
765 unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
766 unsigned long afsr, afar, error_bits;
767 int reported;
768
769 /* Latch uncorrectable error status. */
770 afar = sabre_read(afar_reg);
771 afsr = sabre_read(afsr_reg);
772
773 /* Clear the primary/secondary error status bits. */
774 error_bits = afsr &
775 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
776 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
777 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
778 if (!error_bits)
779 return IRQ_NONE;
780 sabre_write(afsr_reg, error_bits);
781
782 /* Log the error. */
783 printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
784 p->index,
785 ((error_bits & SABRE_UEAFSR_PDRD) ?
786 "DMA Read" :
787 ((error_bits & SABRE_UEAFSR_PDWR) ?
788 "DMA Write" : "???")),
789 ((error_bits & SABRE_UEAFSR_PDTE) ?
790 ":Translation Error" : ""));
791 printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
792 p->index,
793 (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
794 (afsr & SABRE_UEAFSR_OFF) >> 29UL,
795 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
796 printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
797 printk("SABRE%d: UE Secondary errors [", p->index);
798 reported = 0;
799 if (afsr & SABRE_UEAFSR_SDRD) {
800 reported++;
801 printk("(DMA Read)");
802 }
803 if (afsr & SABRE_UEAFSR_SDWR) {
804 reported++;
805 printk("(DMA Write)");
806 }
807 if (afsr & SABRE_UEAFSR_SDTE) {
808 reported++;
809 printk("(Translation Error)");
810 }
811 if (!reported)
812 printk("(none)");
813 printk("]\n");
814
815 /* Interrogate IOMMU for error status. */
816 sabre_check_iommu_error(p, afsr, afar);
817
818 return IRQ_HANDLED;
819 }
820
821 static irqreturn_t sabre_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
822 {
823 struct pci_controller_info *p = dev_id;
824 unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
825 unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
826 unsigned long afsr, afar, error_bits;
827 int reported;
828
829 /* Latch error status. */
830 afar = sabre_read(afar_reg);
831 afsr = sabre_read(afsr_reg);
832
833 /* Clear primary/secondary error status bits. */
834 error_bits = afsr &
835 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
836 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
837 if (!error_bits)
838 return IRQ_NONE;
839 sabre_write(afsr_reg, error_bits);
840
841 /* Log the error. */
842 printk("SABRE%d: Correctable Error, primary error type[%s]\n",
843 p->index,
844 ((error_bits & SABRE_CEAFSR_PDRD) ?
845 "DMA Read" :
846 ((error_bits & SABRE_CEAFSR_PDWR) ?
847 "DMA Write" : "???")));
848
849 /* XXX Use syndrome and afar to print out module string just like
850 * XXX UDB CE trap handler does... -DaveM
851 */
852 printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
853 "was_block(%d)\n",
854 p->index,
855 (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
856 (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
857 (afsr & SABRE_CEAFSR_OFF) >> 29UL,
858 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
859 printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
860 printk("SABRE%d: CE Secondary errors [", p->index);
861 reported = 0;
862 if (afsr & SABRE_CEAFSR_SDRD) {
863 reported++;
864 printk("(DMA Read)");
865 }
866 if (afsr & SABRE_CEAFSR_SDWR) {
867 reported++;
868 printk("(DMA Write)");
869 }
870 if (!reported)
871 printk("(none)");
872 printk("]\n");
873
874 return IRQ_HANDLED;
875 }
876
877 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
878 {
879 unsigned long csr_reg, csr, csr_error_bits;
880 irqreturn_t ret = IRQ_NONE;
881 u16 stat;
882
883 csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
884 csr = sabre_read(csr_reg);
885 csr_error_bits =
886 csr & SABRE_PCICTRL_SERR;
887 if (csr_error_bits) {
888 /* Clear the errors. */
889 sabre_write(csr_reg, csr);
890
891 /* Log 'em. */
892 if (csr_error_bits & SABRE_PCICTRL_SERR)
893 printk("SABRE%d: PCI SERR signal asserted.\n",
894 p->index);
895 ret = IRQ_HANDLED;
896 }
897 pci_read_config_word(sabre_root_bus->self,
898 PCI_STATUS, &stat);
899 if (stat & (PCI_STATUS_PARITY |
900 PCI_STATUS_SIG_TARGET_ABORT |
901 PCI_STATUS_REC_TARGET_ABORT |
902 PCI_STATUS_REC_MASTER_ABORT |
903 PCI_STATUS_SIG_SYSTEM_ERROR)) {
904 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
905 p->index, stat);
906 pci_write_config_word(sabre_root_bus->self,
907 PCI_STATUS, 0xffff);
908 ret = IRQ_HANDLED;
909 }
910 return ret;
911 }
912
913 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
914 {
915 struct pci_controller_info *p = dev_id;
916 unsigned long afsr_reg, afar_reg;
917 unsigned long afsr, afar, error_bits;
918 int reported;
919
920 afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
921 afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
922
923 /* Latch error status. */
924 afar = sabre_read(afar_reg);
925 afsr = sabre_read(afsr_reg);
926
927 /* Clear primary/secondary error status bits. */
928 error_bits = afsr &
929 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
930 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
931 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
932 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
933 if (!error_bits)
934 return sabre_pcierr_intr_other(p);
935 sabre_write(afsr_reg, error_bits);
936
937 /* Log the error. */
938 printk("SABRE%d: PCI Error, primary error type[%s]\n",
939 p->index,
940 (((error_bits & SABRE_PIOAFSR_PMA) ?
941 "Master Abort" :
942 ((error_bits & SABRE_PIOAFSR_PTA) ?
943 "Target Abort" :
944 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
945 "Excessive Retries" :
946 ((error_bits & SABRE_PIOAFSR_PPERR) ?
947 "Parity Error" : "???"))))));
948 printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
949 p->index,
950 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
951 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
952 printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
953 printk("SABRE%d: PCI Secondary errors [", p->index);
954 reported = 0;
955 if (afsr & SABRE_PIOAFSR_SMA) {
956 reported++;
957 printk("(Master Abort)");
958 }
959 if (afsr & SABRE_PIOAFSR_STA) {
960 reported++;
961 printk("(Target Abort)");
962 }
963 if (afsr & SABRE_PIOAFSR_SRTRY) {
964 reported++;
965 printk("(Excessive Retries)");
966 }
967 if (afsr & SABRE_PIOAFSR_SPERR) {
968 reported++;
969 printk("(Parity Error)");
970 }
971 if (!reported)
972 printk("(none)");
973 printk("]\n");
974
975 /* For the error types shown, scan both PCI buses for devices
976 * which have logged that error type.
977 */
978
979 /* If we see a Target Abort, this could be the result of an
980 * IOMMU translation error of some sort. It is extremely
981 * useful to log this information as usually it indicates
982 * a bug in the IOMMU support code or a PCI device driver.
983 */
984 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
985 sabre_check_iommu_error(p, afsr, afar);
986 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
987 pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
988 }
989 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
990 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
991 pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
992 }
993 /* For excessive retries, SABRE/PBM will abort the device
994 * and there is no way to specifically check for excessive
995 * retries in the config space status registers. So what
996 * we hope is that we'll catch it via the master/target
997 * abort events.
998 */
999
1000 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
1001 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
1002 pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
1003 }
1004
1005 return IRQ_HANDLED;
1006 }
1007
1008 /* XXX What about PowerFail/PowerManagement??? -DaveM */
1009 #define SABRE_UE_INO 0x2e
1010 #define SABRE_CE_INO 0x2f
1011 #define SABRE_PCIERR_INO 0x30
1012 static void sabre_register_error_handlers(struct pci_controller_info *p)
1013 {
1014 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
1015 unsigned long base = pbm->controller_regs;
1016 unsigned long irq, portid = pbm->portid;
1017 u64 tmp;
1018
1019 /* We clear the error bits in the appropriate AFSR before
1020 * registering the handler so that we don't get spurious
1021 * interrupts.
1022 */
1023 sabre_write(base + SABRE_UE_AFSR,
1024 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
1025 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
1026 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
1027 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_UE_INO);
1028 if (request_irq(irq, sabre_ue_intr,
1029 SA_SHIRQ, "SABRE UE", p) < 0) {
1030 prom_printf("SABRE%d: Cannot register UE interrupt.\n",
1031 p->index);
1032 prom_halt();
1033 }
1034
1035 sabre_write(base + SABRE_CE_AFSR,
1036 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
1037 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
1038 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_CE_INO);
1039 if (request_irq(irq, sabre_ce_intr,
1040 SA_SHIRQ, "SABRE CE", p) < 0) {
1041 prom_printf("SABRE%d: Cannot register CE interrupt.\n",
1042 p->index);
1043 prom_halt();
1044 }
1045
1046 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_PCIERR_INO);
1047 if (request_irq(irq, sabre_pcierr_intr,
1048 SA_SHIRQ, "SABRE PCIERR", p) < 0) {
1049 prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",
1050 p->index);
1051 prom_halt();
1052 }
1053
1054 tmp = sabre_read(base + SABRE_PCICTRL);
1055 tmp |= SABRE_PCICTRL_ERREN;
1056 sabre_write(base + SABRE_PCICTRL, tmp);
1057 }
1058
1059 static void sabre_resource_adjust(struct pci_dev *pdev,
1060 struct resource *res,
1061 struct resource *root)
1062 {
1063 struct pci_pbm_info *pbm = pdev->bus->sysdata;
1064 unsigned long base;
1065
1066 if (res->flags & IORESOURCE_IO)
1067 base = pbm->controller_regs + SABRE_IOSPACE;
1068 else
1069 base = pbm->controller_regs + SABRE_MEMSPACE;
1070
1071 res->start += base;
1072 res->end += base;
1073 }
1074
1075 static void sabre_base_address_update(struct pci_dev *pdev, int resource)
1076 {
1077 struct pcidev_cookie *pcp = pdev->sysdata;
1078 struct pci_pbm_info *pbm = pcp->pbm;
1079 struct resource *res;
1080 unsigned long base;
1081 u32 reg;
1082 int where, size, is_64bit;
1083
1084 res = &pdev->resource[resource];
1085 if (resource < 6) {
1086 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1087 } else if (resource == PCI_ROM_RESOURCE) {
1088 where = pdev->rom_base_reg;
1089 } else {
1090 /* Somebody might have asked allocation of a non-standard resource */
1091 return;
1092 }
1093
1094 is_64bit = 0;
1095 if (res->flags & IORESOURCE_IO)
1096 base = pbm->controller_regs + SABRE_IOSPACE;
1097 else {
1098 base = pbm->controller_regs + SABRE_MEMSPACE;
1099 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1100 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1101 is_64bit = 1;
1102 }
1103
1104 size = res->end - res->start;
1105 pci_read_config_dword(pdev, where, &reg);
1106 reg = ((reg & size) |
1107 (((u32)(res->start - base)) & ~size));
1108 if (resource == PCI_ROM_RESOURCE) {
1109 reg |= PCI_ROM_ADDRESS_ENABLE;
1110 res->flags |= IORESOURCE_ROM_ENABLE;
1111 }
1112 pci_write_config_dword(pdev, where, reg);
1113
1114 /* This knows that the upper 32-bits of the address
1115 * must be zero. Our PCI common layer enforces this.
1116 */
1117 if (is_64bit)
1118 pci_write_config_dword(pdev, where + 4, 0);
1119 }
1120
1121 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
1122 {
1123 struct pci_dev *pdev;
1124
1125 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
1126
1127 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1128 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
1129 u32 word32;
1130 u16 word16;
1131
1132 sabre_read_pci_cfg(pdev->bus, pdev->devfn,
1133 PCI_COMMAND, 2, &word32);
1134 word16 = (u16) word32;
1135 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
1136 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
1137 PCI_COMMAND_IO;
1138 word32 = (u32) word16;
1139 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1140 PCI_COMMAND, 2, word32);
1141
1142 /* Status register bits are "write 1 to clear". */
1143 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1144 PCI_STATUS, 2, 0xffff);
1145 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1146 PCI_SEC_STATUS, 2, 0xffff);
1147
1148 /* Use a primary/seconday latency timer value
1149 * of 64.
1150 */
1151 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1152 PCI_LATENCY_TIMER, 1, 64);
1153 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1154 PCI_SEC_LATENCY_TIMER, 1, 64);
1155
1156 /* Enable reporting/forwarding of master aborts,
1157 * parity, and SERR.
1158 */
1159 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1160 PCI_BRIDGE_CONTROL, 1,
1161 (PCI_BRIDGE_CTL_PARITY |
1162 PCI_BRIDGE_CTL_SERR |
1163 PCI_BRIDGE_CTL_MASTER_ABORT));
1164 }
1165 }
1166 }
1167
1168 static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
1169 {
1170 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1171
1172 if (!cookie) {
1173 prom_printf("SABRE: Critical allocation failure.\n");
1174 prom_halt();
1175 }
1176
1177 /* All we care about is the PBM. */
1178 cookie->pbm = pbm;
1179
1180 return cookie;
1181 }
1182
1183 static void sabre_scan_bus(struct pci_controller_info *p)
1184 {
1185 static int once;
1186 struct pci_bus *sabre_bus, *pbus;
1187 struct pci_pbm_info *pbm;
1188 struct pcidev_cookie *cookie;
1189 int sabres_scanned;
1190
1191 /* The APB bridge speaks to the Sabre host PCI bridge
1192 * at 66Mhz, but the front side of APB runs at 33Mhz
1193 * for both segments.
1194 */
1195 p->pbm_A.is_66mhz_capable = 0;
1196 p->pbm_B.is_66mhz_capable = 0;
1197
1198 /* This driver has not been verified to handle
1199 * multiple SABREs yet, so trap this.
1200 *
1201 * Also note that the SABRE host bridge is hardwired
1202 * to live at bus 0.
1203 */
1204 if (once != 0) {
1205 prom_printf("SABRE: Multiple controllers unsupported.\n");
1206 prom_halt();
1207 }
1208 once++;
1209
1210 cookie = alloc_bridge_cookie(&p->pbm_A);
1211
1212 sabre_bus = pci_scan_bus(p->pci_first_busno,
1213 p->pci_ops,
1214 &p->pbm_A);
1215 pci_fixup_host_bridge_self(sabre_bus);
1216 sabre_bus->self->sysdata = cookie;
1217
1218 sabre_root_bus = sabre_bus;
1219
1220 apb_init(p, sabre_bus);
1221
1222 sabres_scanned = 0;
1223
1224 list_for_each_entry(pbus, &sabre_bus->children, node) {
1225
1226 if (pbus->number == p->pbm_A.pci_first_busno) {
1227 pbm = &p->pbm_A;
1228 } else if (pbus->number == p->pbm_B.pci_first_busno) {
1229 pbm = &p->pbm_B;
1230 } else
1231 continue;
1232
1233 cookie = alloc_bridge_cookie(pbm);
1234 pbus->self->sysdata = cookie;
1235
1236 sabres_scanned++;
1237
1238 pbus->sysdata = pbm;
1239 pbm->pci_bus = pbus;
1240 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1241 pci_record_assignments(pbm, pbus);
1242 pci_assign_unassigned(pbm, pbus);
1243 pci_fixup_irq(pbm, pbus);
1244 pci_determine_66mhz_disposition(pbm, pbus);
1245 pci_setup_busmastering(pbm, pbus);
1246 }
1247
1248 if (!sabres_scanned) {
1249 /* Hummingbird, no APBs. */
1250 pbm = &p->pbm_A;
1251 sabre_bus->sysdata = pbm;
1252 pbm->pci_bus = sabre_bus;
1253 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1254 pci_record_assignments(pbm, sabre_bus);
1255 pci_assign_unassigned(pbm, sabre_bus);
1256 pci_fixup_irq(pbm, sabre_bus);
1257 pci_determine_66mhz_disposition(pbm, sabre_bus);
1258 pci_setup_busmastering(pbm, sabre_bus);
1259 }
1260
1261 sabre_register_error_handlers(p);
1262 }
1263
1264 static void sabre_iommu_init(struct pci_controller_info *p,
1265 int tsbsize, unsigned long dvma_offset,
1266 u32 dma_mask)
1267 {
1268 struct pci_iommu *iommu = p->pbm_A.iommu;
1269 unsigned long i;
1270 u64 control;
1271
1272 /* Register addresses. */
1273 iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
1274 iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
1275 iommu->iommu_flush = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
1276 iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
1277 /* Sabre's IOMMU lacks ctx flushing. */
1278 iommu->iommu_ctxflush = 0;
1279
1280 /* Invalidate TLB Entries. */
1281 control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1282 control |= SABRE_IOMMUCTRL_DENAB;
1283 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1284
1285 for(i = 0; i < 16; i++) {
1286 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
1287 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1288 }
1289
1290 /* Leave diag mode enabled for full-flushing done
1291 * in pci_iommu.c
1292 */
1293 pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
1294
1295 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
1296 __pa(iommu->page_table));
1297
1298 control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1299 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
1300 control |= SABRE_IOMMUCTRL_ENAB;
1301 switch(tsbsize) {
1302 case 64:
1303 control |= SABRE_IOMMU_TSBSZ_64K;
1304 break;
1305 case 128:
1306 control |= SABRE_IOMMU_TSBSZ_128K;
1307 break;
1308 default:
1309 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1310 prom_halt();
1311 break;
1312 }
1313 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1314 }
1315
1316 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1317 struct pci_pbm_info *pbm)
1318 {
1319 char *name = pbm->name;
1320 unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
1321 unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1322 unsigned int devfn;
1323 unsigned long first, last, i;
1324 u8 *addr, map;
1325
1326 sprintf(name, "SABRE%d PBM%c",
1327 p->index,
1328 (pbm == &p->pbm_A ? 'A' : 'B'));
1329 pbm->io_space.name = pbm->mem_space.name = name;
1330
1331 devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
1332 addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
1333 map = 0;
1334 pci_config_read8(addr, &map);
1335
1336 first = 8;
1337 last = 0;
1338 for (i = 0; i < 8; i++) {
1339 if ((map & (1 << i)) != 0) {
1340 if (first > i)
1341 first = i;
1342 if (last < i)
1343 last = i;
1344 }
1345 }
1346 pbm->io_space.start = ibase + (first << 21UL);
1347 pbm->io_space.end = ibase + (last << 21UL) + ((1 << 21UL) - 1);
1348 pbm->io_space.flags = IORESOURCE_IO;
1349
1350 addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
1351 map = 0;
1352 pci_config_read8(addr, &map);
1353
1354 first = 8;
1355 last = 0;
1356 for (i = 0; i < 8; i++) {
1357 if ((map & (1 << i)) != 0) {
1358 if (first > i)
1359 first = i;
1360 if (last < i)
1361 last = i;
1362 }
1363 }
1364 pbm->mem_space.start = mbase + (first << 29UL);
1365 pbm->mem_space.end = mbase + (last << 29UL) + ((1 << 29UL) - 1);
1366 pbm->mem_space.flags = IORESOURCE_MEM;
1367
1368 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1369 prom_printf("Cannot register PBM-%c's IO space.\n",
1370 (pbm == &p->pbm_A ? 'A' : 'B'));
1371 prom_halt();
1372 }
1373 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1374 prom_printf("Cannot register PBM-%c's MEM space.\n",
1375 (pbm == &p->pbm_A ? 'A' : 'B'));
1376 prom_halt();
1377 }
1378
1379 /* Register legacy regions if this PBM covers that area. */
1380 if (pbm->io_space.start == ibase &&
1381 pbm->mem_space.start == mbase)
1382 pci_register_legacy_regions(&pbm->io_space,
1383 &pbm->mem_space);
1384 }
1385
1386 static void sabre_pbm_init(struct pci_controller_info *p, int sabre_node, u32 dma_begin)
1387 {
1388 struct pci_pbm_info *pbm;
1389 char namebuf[128];
1390 u32 busrange[2];
1391 int node, simbas_found;
1392
1393 simbas_found = 0;
1394 node = prom_getchild(sabre_node);
1395 while ((node = prom_searchsiblings(node, "pci")) != 0) {
1396 int err;
1397
1398 err = prom_getproperty(node, "model", namebuf, sizeof(namebuf));
1399 if ((err <= 0) || strncmp(namebuf, "SUNW,simba", err))
1400 goto next_pci;
1401
1402 err = prom_getproperty(node, "bus-range",
1403 (char *)&busrange[0], sizeof(busrange));
1404 if (err == 0 || err == -1) {
1405 prom_printf("APB: Error, cannot get PCI bus-range.\n");
1406 prom_halt();
1407 }
1408
1409 simbas_found++;
1410 if (busrange[0] == 1)
1411 pbm = &p->pbm_B;
1412 else
1413 pbm = &p->pbm_A;
1414 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1415 pbm->parent = p;
1416 pbm->prom_node = node;
1417 pbm->pci_first_slot = 1;
1418 pbm->pci_first_busno = busrange[0];
1419 pbm->pci_last_busno = busrange[1];
1420
1421 prom_getstring(node, "name", pbm->prom_name, sizeof(pbm->prom_name));
1422 err = prom_getproperty(node, "ranges",
1423 (char *)pbm->pbm_ranges,
1424 sizeof(pbm->pbm_ranges));
1425 if (err != -1)
1426 pbm->num_pbm_ranges =
1427 (err / sizeof(struct linux_prom_pci_ranges));
1428 else
1429 pbm->num_pbm_ranges = 0;
1430
1431 err = prom_getproperty(node, "interrupt-map",
1432 (char *)pbm->pbm_intmap,
1433 sizeof(pbm->pbm_intmap));
1434 if (err != -1) {
1435 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1436 err = prom_getproperty(node, "interrupt-map-mask",
1437 (char *)&pbm->pbm_intmask,
1438 sizeof(pbm->pbm_intmask));
1439 if (err == -1) {
1440 prom_printf("APB: Fatal error, no interrupt-map-mask.\n");
1441 prom_halt();
1442 }
1443 } else {
1444 pbm->num_pbm_intmap = 0;
1445 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1446 }
1447
1448 pbm_register_toplevel_resources(p, pbm);
1449
1450 next_pci:
1451 node = prom_getsibling(node);
1452 if (!node)
1453 break;
1454 }
1455 if (simbas_found == 0) {
1456 int err;
1457
1458 /* No APBs underneath, probably this is a hummingbird
1459 * system.
1460 */
1461 pbm = &p->pbm_A;
1462 pbm->parent = p;
1463 pbm->prom_node = sabre_node;
1464 pbm->pci_first_busno = p->pci_first_busno;
1465 pbm->pci_last_busno = p->pci_last_busno;
1466
1467 prom_getstring(sabre_node, "name", pbm->prom_name, sizeof(pbm->prom_name));
1468 err = prom_getproperty(sabre_node, "ranges",
1469 (char *) pbm->pbm_ranges,
1470 sizeof(pbm->pbm_ranges));
1471 if (err != -1)
1472 pbm->num_pbm_ranges =
1473 (err / sizeof(struct linux_prom_pci_ranges));
1474 else
1475 pbm->num_pbm_ranges = 0;
1476
1477 err = prom_getproperty(sabre_node, "interrupt-map",
1478 (char *) pbm->pbm_intmap,
1479 sizeof(pbm->pbm_intmap));
1480
1481 if (err != -1) {
1482 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1483 err = prom_getproperty(sabre_node, "interrupt-map-mask",
1484 (char *)&pbm->pbm_intmask,
1485 sizeof(pbm->pbm_intmask));
1486 if (err == -1) {
1487 prom_printf("Hummingbird: Fatal error, no interrupt-map-mask.\n");
1488 prom_halt();
1489 }
1490 } else {
1491 pbm->num_pbm_intmap = 0;
1492 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1493 }
1494
1495
1496 sprintf(pbm->name, "SABRE%d PBM%c", p->index,
1497 (pbm == &p->pbm_A ? 'A' : 'B'));
1498 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1499
1500 /* Hack up top-level resources. */
1501 pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
1502 pbm->io_space.end = pbm->io_space.start + (1UL << 24) - 1UL;
1503 pbm->io_space.flags = IORESOURCE_IO;
1504
1505 pbm->mem_space.start = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1506 pbm->mem_space.end = pbm->mem_space.start + (unsigned long)dma_begin - 1UL;
1507 pbm->mem_space.flags = IORESOURCE_MEM;
1508
1509 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1510 prom_printf("Cannot register Hummingbird's IO space.\n");
1511 prom_halt();
1512 }
1513 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1514 prom_printf("Cannot register Hummingbird's MEM space.\n");
1515 prom_halt();
1516 }
1517
1518 pci_register_legacy_regions(&pbm->io_space,
1519 &pbm->mem_space);
1520 }
1521 }
1522
1523 void sabre_init(int pnode, char *model_name)
1524 {
1525 struct linux_prom64_registers pr_regs[2];
1526 struct pci_controller_info *p;
1527 struct pci_iommu *iommu;
1528 int tsbsize, err;
1529 u32 busrange[2];
1530 u32 vdma[2];
1531 u32 upa_portid, dma_mask;
1532 u64 clear_irq;
1533
1534 hummingbird_p = 0;
1535 if (!strcmp(model_name, "pci108e,a001"))
1536 hummingbird_p = 1;
1537 else if (!strcmp(model_name, "SUNW,sabre")) {
1538 char compat[64];
1539
1540 if (prom_getproperty(pnode, "compatible",
1541 compat, sizeof(compat)) > 0 &&
1542 !strcmp(compat, "pci108e,a001")) {
1543 hummingbird_p = 1;
1544 } else {
1545 int cpu_node;
1546
1547 /* Of course, Sun has to encode things a thousand
1548 * different ways, inconsistently.
1549 */
1550 cpu_find_by_instance(0, &cpu_node, NULL);
1551 if (prom_getproperty(cpu_node, "name",
1552 compat, sizeof(compat)) > 0 &&
1553 !strcmp(compat, "SUNW,UltraSPARC-IIe"))
1554 hummingbird_p = 1;
1555 }
1556 }
1557
1558 p = kzalloc(sizeof(*p), GFP_ATOMIC);
1559 if (!p) {
1560 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1561 prom_halt();
1562 }
1563
1564 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1565 if (!iommu) {
1566 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1567 prom_halt();
1568 }
1569 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1570
1571 upa_portid = prom_getintdefault(pnode, "upa-portid", 0xff);
1572
1573 p->next = pci_controller_root;
1574 pci_controller_root = p;
1575
1576 p->pbm_A.portid = upa_portid;
1577 p->pbm_B.portid = upa_portid;
1578 p->index = pci_num_controllers++;
1579 p->pbms_same_domain = 1;
1580 p->scan_bus = sabre_scan_bus;
1581 p->irq_build = sabre_irq_build;
1582 p->base_address_update = sabre_base_address_update;
1583 p->resource_adjust = sabre_resource_adjust;
1584 p->pci_ops = &sabre_ops;
1585
1586 /*
1587 * Map in SABRE register set and report the presence of this SABRE.
1588 */
1589 err = prom_getproperty(pnode, "reg",
1590 (char *)&pr_regs[0], sizeof(pr_regs));
1591 if(err == 0 || err == -1) {
1592 prom_printf("SABRE: Error, cannot get U2P registers "
1593 "from PROM.\n");
1594 prom_halt();
1595 }
1596
1597 /*
1598 * First REG in property is base of entire SABRE register space.
1599 */
1600 p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1601 p->pbm_B.controller_regs = pr_regs[0].phys_addr;
1602
1603 printk("PCI: Found SABRE, main regs at %016lx\n",
1604 p->pbm_A.controller_regs);
1605
1606 /* Clear interrupts */
1607
1608 /* PCI first */
1609 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1610 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1611
1612 /* Then OBIO */
1613 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1614 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1615
1616 /* Error interrupts are enabled later after the bus scan. */
1617 sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1618 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
1619 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1620
1621 /* Now map in PCI config space for entire SABRE. */
1622 p->pbm_A.config_space = p->pbm_B.config_space =
1623 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1624 printk("SABRE: Shared PCI config space at %016lx\n",
1625 p->pbm_A.config_space);
1626
1627 err = prom_getproperty(pnode, "virtual-dma",
1628 (char *)&vdma[0], sizeof(vdma));
1629 if(err == 0 || err == -1) {
1630 prom_printf("SABRE: Error, cannot get virtual-dma property "
1631 "from PROM.\n");
1632 prom_halt();
1633 }
1634
1635 dma_mask = vdma[0];
1636 switch(vdma[1]) {
1637 case 0x20000000:
1638 dma_mask |= 0x1fffffff;
1639 tsbsize = 64;
1640 break;
1641 case 0x40000000:
1642 dma_mask |= 0x3fffffff;
1643 tsbsize = 128;
1644 break;
1645
1646 case 0x80000000:
1647 dma_mask |= 0x7fffffff;
1648 tsbsize = 128;
1649 break;
1650 default:
1651 prom_printf("SABRE: strange virtual-dma size.\n");
1652 prom_halt();
1653 }
1654
1655 sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1656
1657 printk("SABRE: DVMA at %08x [%08x]\n", vdma[0], vdma[1]);
1658
1659 err = prom_getproperty(pnode, "bus-range",
1660 (char *)&busrange[0], sizeof(busrange));
1661 if(err == 0 || err == -1) {
1662 prom_printf("SABRE: Error, cannot get PCI bus-range "
1663 " from PROM.\n");
1664 prom_halt();
1665 }
1666
1667 p->pci_first_busno = busrange[0];
1668 p->pci_last_busno = busrange[1];
1669
1670 /*
1671 * Look for APB underneath.
1672 */
1673 sabre_pbm_init(p, pnode, vdma[0]);
1674 }
Linux kernel - Deliverables
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