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[SPARC64]: Kill ino_bucket->pil
[deliverable/linux.git] / arch / sparc64 / kernel / sbus.c
1 /* $Id: sbus.c,v 1.19 2002/01/23 11:27:32 davem Exp $
2 * sbus.c: UltraSparc SBUS controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/mm.h>
10 #include <linux/spinlock.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/page.h>
16 #include <asm/sbus.h>
17 #include <asm/io.h>
18 #include <asm/upa.h>
19 #include <asm/cache.h>
20 #include <asm/dma.h>
21 #include <asm/irq.h>
22 #include <asm/starfire.h>
23
24 #include "iommu_common.h"
25
26 /* These should be allocated on an SMP_CACHE_BYTES
27 * aligned boundary for optimal performance.
28 *
29 * On SYSIO, using an 8K page size we have 1GB of SBUS
30 * DMA space mapped. We divide this space into equally
31 * sized clusters. We allocate a DMA mapping from the
32 * cluster that matches the order of the allocation, or
33 * if the order is greater than the number of clusters,
34 * we try to allocate from the last cluster.
35 */
36
37 #define NCLUSTERS 8UL
38 #define ONE_GIG (1UL * 1024UL * 1024UL * 1024UL)
39 #define CLUSTER_SIZE (ONE_GIG / NCLUSTERS)
40 #define CLUSTER_MASK (CLUSTER_SIZE - 1)
41 #define CLUSTER_NPAGES (CLUSTER_SIZE >> IO_PAGE_SHIFT)
42 #define MAP_BASE ((u32)0xc0000000)
43
44 struct sbus_iommu {
45 /*0x00*/spinlock_t lock;
46
47 /*0x08*/iopte_t *page_table;
48 /*0x10*/unsigned long strbuf_regs;
49 /*0x18*/unsigned long iommu_regs;
50 /*0x20*/unsigned long sbus_control_reg;
51
52 /*0x28*/volatile unsigned long strbuf_flushflag;
53
54 /* If NCLUSTERS is ever decresed to 4 or lower,
55 * you must increase the size of the type of
56 * these counters. You have been duly warned. -DaveM
57 */
58 /*0x30*/struct {
59 u16 next;
60 u16 flush;
61 } alloc_info[NCLUSTERS];
62
63 /* The lowest used consistent mapping entry. Since
64 * we allocate consistent maps out of cluster 0 this
65 * is relative to the beginning of closter 0.
66 */
67 /*0x50*/u32 lowest_consistent_map;
68 };
69
70 /* Offsets from iommu_regs */
71 #define SYSIO_IOMMUREG_BASE 0x2400UL
72 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
73 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
74 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
75 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
76 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
77 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
78 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
79 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
80
81 #define IOMMU_DRAM_VALID (1UL << 30UL)
82
83 static void __iommu_flushall(struct sbus_iommu *iommu)
84 {
85 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
86 int entry;
87
88 for (entry = 0; entry < 16; entry++) {
89 upa_writeq(0, tag);
90 tag += 8UL;
91 }
92 upa_readq(iommu->sbus_control_reg);
93
94 for (entry = 0; entry < NCLUSTERS; entry++) {
95 iommu->alloc_info[entry].flush =
96 iommu->alloc_info[entry].next;
97 }
98 }
99
100 static void iommu_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
101 {
102 while (npages--)
103 upa_writeq(base + (npages << IO_PAGE_SHIFT),
104 iommu->iommu_regs + IOMMU_FLUSH);
105 upa_readq(iommu->sbus_control_reg);
106 }
107
108 /* Offsets from strbuf_regs */
109 #define SYSIO_STRBUFREG_BASE 0x2800UL
110 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
111 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
112 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
113 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
114 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
115 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
116 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
117
118 #define STRBUF_TAG_VALID 0x02UL
119
120 static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages, int direction)
121 {
122 unsigned long n;
123 int limit;
124
125 n = npages;
126 while (n--)
127 upa_writeq(base + (n << IO_PAGE_SHIFT),
128 iommu->strbuf_regs + STRBUF_PFLUSH);
129
130 /* If the device could not have possibly put dirty data into
131 * the streaming cache, no flush-flag synchronization needs
132 * to be performed.
133 */
134 if (direction == SBUS_DMA_TODEVICE)
135 return;
136
137 iommu->strbuf_flushflag = 0UL;
138
139 /* Whoopee cushion! */
140 upa_writeq(__pa(&iommu->strbuf_flushflag),
141 iommu->strbuf_regs + STRBUF_FSYNC);
142 upa_readq(iommu->sbus_control_reg);
143
144 limit = 100000;
145 while (iommu->strbuf_flushflag == 0UL) {
146 limit--;
147 if (!limit)
148 break;
149 udelay(1);
150 rmb();
151 }
152 if (!limit)
153 printk(KERN_WARNING "sbus_strbuf_flush: flushflag timeout "
154 "vaddr[%08x] npages[%ld]\n",
155 base, npages);
156 }
157
158 static iopte_t *alloc_streaming_cluster(struct sbus_iommu *iommu, unsigned long npages)
159 {
160 iopte_t *iopte, *limit, *first, *cluster;
161 unsigned long cnum, ent, nent, flush_point, found;
162
163 cnum = 0;
164 nent = 1;
165 while ((1UL << cnum) < npages)
166 cnum++;
167 if(cnum >= NCLUSTERS) {
168 nent = 1UL << (cnum - NCLUSTERS);
169 cnum = NCLUSTERS - 1;
170 }
171 iopte = iommu->page_table + (cnum * CLUSTER_NPAGES);
172
173 if (cnum == 0)
174 limit = (iommu->page_table +
175 iommu->lowest_consistent_map);
176 else
177 limit = (iopte + CLUSTER_NPAGES);
178
179 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
180 flush_point = iommu->alloc_info[cnum].flush;
181
182 first = iopte;
183 cluster = NULL;
184 found = 0;
185 for (;;) {
186 if (iopte_val(*iopte) == 0UL) {
187 found++;
188 if (!cluster)
189 cluster = iopte;
190 } else {
191 /* Used cluster in the way */
192 cluster = NULL;
193 found = 0;
194 }
195
196 if (found == nent)
197 break;
198
199 iopte += (1 << cnum);
200 ent++;
201 if (iopte >= limit) {
202 iopte = (iommu->page_table + (cnum * CLUSTER_NPAGES));
203 ent = 0;
204
205 /* Multiple cluster allocations must not wrap */
206 cluster = NULL;
207 found = 0;
208 }
209 if (ent == flush_point)
210 __iommu_flushall(iommu);
211 if (iopte == first)
212 goto bad;
213 }
214
215 /* ent/iopte points to the last cluster entry we're going to use,
216 * so save our place for the next allocation.
217 */
218 if ((iopte + (1 << cnum)) >= limit)
219 ent = 0;
220 else
221 ent = ent + 1;
222 iommu->alloc_info[cnum].next = ent;
223 if (ent == flush_point)
224 __iommu_flushall(iommu);
225
226 /* I've got your streaming cluster right here buddy boy... */
227 return cluster;
228
229 bad:
230 printk(KERN_EMERG "sbus: alloc_streaming_cluster of npages(%ld) failed!\n",
231 npages);
232 return NULL;
233 }
234
235 static void free_streaming_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
236 {
237 unsigned long cnum, ent, nent;
238 iopte_t *iopte;
239
240 cnum = 0;
241 nent = 1;
242 while ((1UL << cnum) < npages)
243 cnum++;
244 if(cnum >= NCLUSTERS) {
245 nent = 1UL << (cnum - NCLUSTERS);
246 cnum = NCLUSTERS - 1;
247 }
248 ent = (base & CLUSTER_MASK) >> (IO_PAGE_SHIFT + cnum);
249 iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
250 do {
251 iopte_val(*iopte) = 0UL;
252 iopte += 1 << cnum;
253 } while(--nent);
254
255 /* If the global flush might not have caught this entry,
256 * adjust the flush point such that we will flush before
257 * ever trying to reuse it.
258 */
259 #define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
260 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
261 iommu->alloc_info[cnum].flush = ent;
262 #undef between
263 }
264
265 /* We allocate consistent mappings from the end of cluster zero. */
266 static iopte_t *alloc_consistent_cluster(struct sbus_iommu *iommu, unsigned long npages)
267 {
268 iopte_t *iopte;
269
270 iopte = iommu->page_table + (1 * CLUSTER_NPAGES);
271 while (iopte > iommu->page_table) {
272 iopte--;
273 if (!(iopte_val(*iopte) & IOPTE_VALID)) {
274 unsigned long tmp = npages;
275
276 while (--tmp) {
277 iopte--;
278 if (iopte_val(*iopte) & IOPTE_VALID)
279 break;
280 }
281 if (tmp == 0) {
282 u32 entry = (iopte - iommu->page_table);
283
284 if (entry < iommu->lowest_consistent_map)
285 iommu->lowest_consistent_map = entry;
286 return iopte;
287 }
288 }
289 }
290 return NULL;
291 }
292
293 static void free_consistent_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
294 {
295 iopte_t *iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
296
297 if ((iopte - iommu->page_table) == iommu->lowest_consistent_map) {
298 iopte_t *walk = iopte + npages;
299 iopte_t *limit;
300
301 limit = iommu->page_table + CLUSTER_NPAGES;
302 while (walk < limit) {
303 if (iopte_val(*walk) != 0UL)
304 break;
305 walk++;
306 }
307 iommu->lowest_consistent_map =
308 (walk - iommu->page_table);
309 }
310
311 while (npages--)
312 *iopte++ = __iopte(0UL);
313 }
314
315 void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
316 {
317 unsigned long order, first_page, flags;
318 struct sbus_iommu *iommu;
319 iopte_t *iopte;
320 void *ret;
321 int npages;
322
323 if (size <= 0 || sdev == NULL || dvma_addr == NULL)
324 return NULL;
325
326 size = IO_PAGE_ALIGN(size);
327 order = get_order(size);
328 if (order >= 10)
329 return NULL;
330 first_page = __get_free_pages(GFP_KERNEL|__GFP_COMP, order);
331 if (first_page == 0UL)
332 return NULL;
333 memset((char *)first_page, 0, PAGE_SIZE << order);
334
335 iommu = sdev->bus->iommu;
336
337 spin_lock_irqsave(&iommu->lock, flags);
338 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
339 if (iopte == NULL) {
340 spin_unlock_irqrestore(&iommu->lock, flags);
341 free_pages(first_page, order);
342 return NULL;
343 }
344
345 /* Ok, we're committed at this point. */
346 *dvma_addr = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
347 ret = (void *) first_page;
348 npages = size >> IO_PAGE_SHIFT;
349 while (npages--) {
350 *iopte++ = __iopte(IOPTE_VALID | IOPTE_CACHE | IOPTE_WRITE |
351 (__pa(first_page) & IOPTE_PAGE));
352 first_page += IO_PAGE_SIZE;
353 }
354 iommu_flush(iommu, *dvma_addr, size >> IO_PAGE_SHIFT);
355 spin_unlock_irqrestore(&iommu->lock, flags);
356
357 return ret;
358 }
359
360 void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
361 {
362 unsigned long order, npages;
363 struct sbus_iommu *iommu;
364
365 if (size <= 0 || sdev == NULL || cpu == NULL)
366 return;
367
368 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
369 iommu = sdev->bus->iommu;
370
371 spin_lock_irq(&iommu->lock);
372 free_consistent_cluster(iommu, dvma, npages);
373 iommu_flush(iommu, dvma, npages);
374 spin_unlock_irq(&iommu->lock);
375
376 order = get_order(size);
377 if (order < 10)
378 free_pages((unsigned long)cpu, order);
379 }
380
381 dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t size, int dir)
382 {
383 struct sbus_iommu *iommu = sdev->bus->iommu;
384 unsigned long npages, pbase, flags;
385 iopte_t *iopte;
386 u32 dma_base, offset;
387 unsigned long iopte_bits;
388
389 if (dir == SBUS_DMA_NONE)
390 BUG();
391
392 pbase = (unsigned long) ptr;
393 offset = (u32) (pbase & ~IO_PAGE_MASK);
394 size = (IO_PAGE_ALIGN(pbase + size) - (pbase & IO_PAGE_MASK));
395 pbase = (unsigned long) __pa(pbase & IO_PAGE_MASK);
396
397 spin_lock_irqsave(&iommu->lock, flags);
398 npages = size >> IO_PAGE_SHIFT;
399 iopte = alloc_streaming_cluster(iommu, npages);
400 if (iopte == NULL)
401 goto bad;
402 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
403 npages = size >> IO_PAGE_SHIFT;
404 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
405 if (dir != SBUS_DMA_TODEVICE)
406 iopte_bits |= IOPTE_WRITE;
407 while (npages--) {
408 *iopte++ = __iopte(iopte_bits | (pbase & IOPTE_PAGE));
409 pbase += IO_PAGE_SIZE;
410 }
411 npages = size >> IO_PAGE_SHIFT;
412 spin_unlock_irqrestore(&iommu->lock, flags);
413
414 return (dma_base | offset);
415
416 bad:
417 spin_unlock_irqrestore(&iommu->lock, flags);
418 BUG();
419 return 0;
420 }
421
422 void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t dma_addr, size_t size, int direction)
423 {
424 struct sbus_iommu *iommu = sdev->bus->iommu;
425 u32 dma_base = dma_addr & IO_PAGE_MASK;
426 unsigned long flags;
427
428 size = (IO_PAGE_ALIGN(dma_addr + size) - dma_base);
429
430 spin_lock_irqsave(&iommu->lock, flags);
431 free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
432 sbus_strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT, direction);
433 spin_unlock_irqrestore(&iommu->lock, flags);
434 }
435
436 #define SG_ENT_PHYS_ADDRESS(SG) \
437 (__pa(page_address((SG)->page)) + (SG)->offset)
438
439 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, int nelems, unsigned long iopte_bits)
440 {
441 struct scatterlist *dma_sg = sg;
442 struct scatterlist *sg_end = sg + nelems;
443 int i;
444
445 for (i = 0; i < nused; i++) {
446 unsigned long pteval = ~0UL;
447 u32 dma_npages;
448
449 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
450 dma_sg->dma_length +
451 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
452 do {
453 unsigned long offset;
454 signed int len;
455
456 /* If we are here, we know we have at least one
457 * more page to map. So walk forward until we
458 * hit a page crossing, and begin creating new
459 * mappings from that spot.
460 */
461 for (;;) {
462 unsigned long tmp;
463
464 tmp = (unsigned long) SG_ENT_PHYS_ADDRESS(sg);
465 len = sg->length;
466 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
467 pteval = tmp & IO_PAGE_MASK;
468 offset = tmp & (IO_PAGE_SIZE - 1UL);
469 break;
470 }
471 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
472 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
473 offset = 0UL;
474 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
475 break;
476 }
477 sg++;
478 }
479
480 pteval = ((pteval & IOPTE_PAGE) | iopte_bits);
481 while (len > 0) {
482 *iopte++ = __iopte(pteval);
483 pteval += IO_PAGE_SIZE;
484 len -= (IO_PAGE_SIZE - offset);
485 offset = 0;
486 dma_npages--;
487 }
488
489 pteval = (pteval & IOPTE_PAGE) + len;
490 sg++;
491
492 /* Skip over any tail mappings we've fully mapped,
493 * adjusting pteval along the way. Stop when we
494 * detect a page crossing event.
495 */
496 while (sg < sg_end &&
497 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
498 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
499 ((pteval ^
500 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
501 pteval += sg->length;
502 sg++;
503 }
504 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
505 pteval = ~0UL;
506 } while (dma_npages != 0);
507 dma_sg++;
508 }
509 }
510
511 int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int dir)
512 {
513 struct sbus_iommu *iommu = sdev->bus->iommu;
514 unsigned long flags, npages;
515 iopte_t *iopte;
516 u32 dma_base;
517 struct scatterlist *sgtmp;
518 int used;
519 unsigned long iopte_bits;
520
521 if (dir == SBUS_DMA_NONE)
522 BUG();
523
524 /* Fast path single entry scatterlists. */
525 if (nents == 1) {
526 sg->dma_address =
527 sbus_map_single(sdev,
528 (page_address(sg->page) + sg->offset),
529 sg->length, dir);
530 sg->dma_length = sg->length;
531 return 1;
532 }
533
534 npages = prepare_sg(sg, nents);
535
536 spin_lock_irqsave(&iommu->lock, flags);
537 iopte = alloc_streaming_cluster(iommu, npages);
538 if (iopte == NULL)
539 goto bad;
540 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
541
542 /* Normalize DVMA addresses. */
543 sgtmp = sg;
544 used = nents;
545
546 while (used && sgtmp->dma_length) {
547 sgtmp->dma_address += dma_base;
548 sgtmp++;
549 used--;
550 }
551 used = nents - used;
552
553 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
554 if (dir != SBUS_DMA_TODEVICE)
555 iopte_bits |= IOPTE_WRITE;
556
557 fill_sg(iopte, sg, used, nents, iopte_bits);
558 #ifdef VERIFY_SG
559 verify_sglist(sg, nents, iopte, npages);
560 #endif
561 spin_unlock_irqrestore(&iommu->lock, flags);
562
563 return used;
564
565 bad:
566 spin_unlock_irqrestore(&iommu->lock, flags);
567 BUG();
568 return 0;
569 }
570
571 void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
572 {
573 unsigned long size, flags;
574 struct sbus_iommu *iommu;
575 u32 dvma_base;
576 int i;
577
578 /* Fast path single entry scatterlists. */
579 if (nents == 1) {
580 sbus_unmap_single(sdev, sg->dma_address, sg->dma_length, direction);
581 return;
582 }
583
584 dvma_base = sg[0].dma_address & IO_PAGE_MASK;
585 for (i = 0; i < nents; i++) {
586 if (sg[i].dma_length == 0)
587 break;
588 }
589 i--;
590 size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - dvma_base;
591
592 iommu = sdev->bus->iommu;
593 spin_lock_irqsave(&iommu->lock, flags);
594 free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
595 sbus_strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT, direction);
596 spin_unlock_irqrestore(&iommu->lock, flags);
597 }
598
599 void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
600 {
601 struct sbus_iommu *iommu = sdev->bus->iommu;
602 unsigned long flags;
603
604 size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
605
606 spin_lock_irqsave(&iommu->lock, flags);
607 sbus_strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT, direction);
608 spin_unlock_irqrestore(&iommu->lock, flags);
609 }
610
611 void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
612 {
613 }
614
615 void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
616 {
617 struct sbus_iommu *iommu = sdev->bus->iommu;
618 unsigned long flags, size;
619 u32 base;
620 int i;
621
622 base = sg[0].dma_address & IO_PAGE_MASK;
623 for (i = 0; i < nents; i++) {
624 if (sg[i].dma_length == 0)
625 break;
626 }
627 i--;
628 size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - base;
629
630 spin_lock_irqsave(&iommu->lock, flags);
631 sbus_strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT, direction);
632 spin_unlock_irqrestore(&iommu->lock, flags);
633 }
634
635 void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
636 {
637 }
638
639 /* Enable 64-bit DVMA mode for the given device. */
640 void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
641 {
642 struct sbus_iommu *iommu = sdev->bus->iommu;
643 int slot = sdev->slot;
644 unsigned long cfg_reg;
645 u64 val;
646
647 cfg_reg = iommu->sbus_control_reg;
648 switch (slot) {
649 case 0:
650 cfg_reg += 0x20UL;
651 break;
652 case 1:
653 cfg_reg += 0x28UL;
654 break;
655 case 2:
656 cfg_reg += 0x30UL;
657 break;
658 case 3:
659 cfg_reg += 0x38UL;
660 break;
661 case 13:
662 cfg_reg += 0x40UL;
663 break;
664 case 14:
665 cfg_reg += 0x48UL;
666 break;
667 case 15:
668 cfg_reg += 0x50UL;
669 break;
670
671 default:
672 return;
673 };
674
675 val = upa_readq(cfg_reg);
676 if (val & (1UL << 14UL)) {
677 /* Extended transfer mode already enabled. */
678 return;
679 }
680
681 val |= (1UL << 14UL);
682
683 if (bursts & DMA_BURST8)
684 val |= (1UL << 1UL);
685 if (bursts & DMA_BURST16)
686 val |= (1UL << 2UL);
687 if (bursts & DMA_BURST32)
688 val |= (1UL << 3UL);
689 if (bursts & DMA_BURST64)
690 val |= (1UL << 4UL);
691 upa_writeq(val, cfg_reg);
692 }
693
694 /* INO number to IMAP register offset for SYSIO external IRQ's.
695 * This should conform to both Sunfire/Wildfire server and Fusion
696 * desktop designs.
697 */
698 #define SYSIO_IMAP_SLOT0 0x2c04UL
699 #define SYSIO_IMAP_SLOT1 0x2c0cUL
700 #define SYSIO_IMAP_SLOT2 0x2c14UL
701 #define SYSIO_IMAP_SLOT3 0x2c1cUL
702 #define SYSIO_IMAP_SCSI 0x3004UL
703 #define SYSIO_IMAP_ETH 0x300cUL
704 #define SYSIO_IMAP_BPP 0x3014UL
705 #define SYSIO_IMAP_AUDIO 0x301cUL
706 #define SYSIO_IMAP_PFAIL 0x3024UL
707 #define SYSIO_IMAP_KMS 0x302cUL
708 #define SYSIO_IMAP_FLPY 0x3034UL
709 #define SYSIO_IMAP_SHW 0x303cUL
710 #define SYSIO_IMAP_KBD 0x3044UL
711 #define SYSIO_IMAP_MS 0x304cUL
712 #define SYSIO_IMAP_SER 0x3054UL
713 #define SYSIO_IMAP_TIM0 0x3064UL
714 #define SYSIO_IMAP_TIM1 0x306cUL
715 #define SYSIO_IMAP_UE 0x3074UL
716 #define SYSIO_IMAP_CE 0x307cUL
717 #define SYSIO_IMAP_SBERR 0x3084UL
718 #define SYSIO_IMAP_PMGMT 0x308cUL
719 #define SYSIO_IMAP_GFX 0x3094UL
720 #define SYSIO_IMAP_EUPA 0x309cUL
721
722 #define bogon ((unsigned long) -1)
723 static unsigned long sysio_irq_offsets[] = {
724 /* SBUS Slot 0 --> 3, level 1 --> 7 */
725 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
726 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
727 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
728 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
729 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
730 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
731 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
732 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
733
734 /* Onboard devices (not relevant/used on SunFire). */
735 SYSIO_IMAP_SCSI,
736 SYSIO_IMAP_ETH,
737 SYSIO_IMAP_BPP,
738 bogon,
739 SYSIO_IMAP_AUDIO,
740 SYSIO_IMAP_PFAIL,
741 bogon,
742 bogon,
743 SYSIO_IMAP_KMS,
744 SYSIO_IMAP_FLPY,
745 SYSIO_IMAP_SHW,
746 SYSIO_IMAP_KBD,
747 SYSIO_IMAP_MS,
748 SYSIO_IMAP_SER,
749 bogon,
750 bogon,
751 SYSIO_IMAP_TIM0,
752 SYSIO_IMAP_TIM1,
753 bogon,
754 bogon,
755 SYSIO_IMAP_UE,
756 SYSIO_IMAP_CE,
757 SYSIO_IMAP_SBERR,
758 SYSIO_IMAP_PMGMT,
759 };
760
761 #undef bogon
762
763 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
764
765 /* Convert Interrupt Mapping register pointer to associated
766 * Interrupt Clear register pointer, SYSIO specific version.
767 */
768 #define SYSIO_ICLR_UNUSED0 0x3400UL
769 #define SYSIO_ICLR_SLOT0 0x340cUL
770 #define SYSIO_ICLR_SLOT1 0x344cUL
771 #define SYSIO_ICLR_SLOT2 0x348cUL
772 #define SYSIO_ICLR_SLOT3 0x34ccUL
773 static unsigned long sysio_imap_to_iclr(unsigned long imap)
774 {
775 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
776 return imap + diff;
777 }
778
779 unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
780 {
781 struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
782 struct sbus_iommu *iommu = sbus->iommu;
783 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
784 unsigned long imap, iclr;
785 int sbus_level = 0;
786
787 imap = sysio_irq_offsets[ino];
788 if (imap == ((unsigned long)-1)) {
789 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
790 ino);
791 prom_halt();
792 }
793 imap += reg_base;
794
795 /* SYSIO inconsistency. For external SLOTS, we have to select
796 * the right ICLR register based upon the lower SBUS irq level
797 * bits.
798 */
799 if (ino >= 0x20) {
800 iclr = sysio_imap_to_iclr(imap);
801 } else {
802 int sbus_slot = (ino & 0x18)>>3;
803
804 sbus_level = ino & 0x7;
805
806 switch(sbus_slot) {
807 case 0:
808 iclr = reg_base + SYSIO_ICLR_SLOT0;
809 break;
810 case 1:
811 iclr = reg_base + SYSIO_ICLR_SLOT1;
812 break;
813 case 2:
814 iclr = reg_base + SYSIO_ICLR_SLOT2;
815 break;
816 default:
817 case 3:
818 iclr = reg_base + SYSIO_ICLR_SLOT3;
819 break;
820 };
821
822 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
823 }
824 return build_irq(sbus_level, iclr, imap);
825 }
826
827 /* Error interrupt handling. */
828 #define SYSIO_UE_AFSR 0x0030UL
829 #define SYSIO_UE_AFAR 0x0038UL
830 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
831 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
832 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
833 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
834 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
835 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
836 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
837 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
838 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
839 #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
840 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
841 static irqreturn_t sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
842 {
843 struct sbus_bus *sbus = dev_id;
844 struct sbus_iommu *iommu = sbus->iommu;
845 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
846 unsigned long afsr_reg, afar_reg;
847 unsigned long afsr, afar, error_bits;
848 int reported;
849
850 afsr_reg = reg_base + SYSIO_UE_AFSR;
851 afar_reg = reg_base + SYSIO_UE_AFAR;
852
853 /* Latch error status. */
854 afsr = upa_readq(afsr_reg);
855 afar = upa_readq(afar_reg);
856
857 /* Clear primary/secondary error status bits. */
858 error_bits = afsr &
859 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
860 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
861 upa_writeq(error_bits, afsr_reg);
862
863 /* Log the error. */
864 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
865 sbus->portid,
866 (((error_bits & SYSIO_UEAFSR_PPIO) ?
867 "PIO" :
868 ((error_bits & SYSIO_UEAFSR_PDRD) ?
869 "DVMA Read" :
870 ((error_bits & SYSIO_UEAFSR_PDWR) ?
871 "DVMA Write" : "???")))));
872 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
873 sbus->portid,
874 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
875 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
876 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
877 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
878 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
879 reported = 0;
880 if (afsr & SYSIO_UEAFSR_SPIO) {
881 reported++;
882 printk("(PIO)");
883 }
884 if (afsr & SYSIO_UEAFSR_SDRD) {
885 reported++;
886 printk("(DVMA Read)");
887 }
888 if (afsr & SYSIO_UEAFSR_SDWR) {
889 reported++;
890 printk("(DVMA Write)");
891 }
892 if (!reported)
893 printk("(none)");
894 printk("]\n");
895
896 return IRQ_HANDLED;
897 }
898
899 #define SYSIO_CE_AFSR 0x0040UL
900 #define SYSIO_CE_AFAR 0x0048UL
901 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
902 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
903 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
904 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
905 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
906 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
907 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
908 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
909 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
910 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
911 #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
912 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
913 static irqreturn_t sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
914 {
915 struct sbus_bus *sbus = dev_id;
916 struct sbus_iommu *iommu = sbus->iommu;
917 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
918 unsigned long afsr_reg, afar_reg;
919 unsigned long afsr, afar, error_bits;
920 int reported;
921
922 afsr_reg = reg_base + SYSIO_CE_AFSR;
923 afar_reg = reg_base + SYSIO_CE_AFAR;
924
925 /* Latch error status. */
926 afsr = upa_readq(afsr_reg);
927 afar = upa_readq(afar_reg);
928
929 /* Clear primary/secondary error status bits. */
930 error_bits = afsr &
931 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
932 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
933 upa_writeq(error_bits, afsr_reg);
934
935 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
936 sbus->portid,
937 (((error_bits & SYSIO_CEAFSR_PPIO) ?
938 "PIO" :
939 ((error_bits & SYSIO_CEAFSR_PDRD) ?
940 "DVMA Read" :
941 ((error_bits & SYSIO_CEAFSR_PDWR) ?
942 "DVMA Write" : "???")))));
943
944 /* XXX Use syndrome and afar to print out module string just like
945 * XXX UDB CE trap handler does... -DaveM
946 */
947 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
948 sbus->portid,
949 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
950 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
951 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
952 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
953 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
954
955 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
956 reported = 0;
957 if (afsr & SYSIO_CEAFSR_SPIO) {
958 reported++;
959 printk("(PIO)");
960 }
961 if (afsr & SYSIO_CEAFSR_SDRD) {
962 reported++;
963 printk("(DVMA Read)");
964 }
965 if (afsr & SYSIO_CEAFSR_SDWR) {
966 reported++;
967 printk("(DVMA Write)");
968 }
969 if (!reported)
970 printk("(none)");
971 printk("]\n");
972
973 return IRQ_HANDLED;
974 }
975
976 #define SYSIO_SBUS_AFSR 0x2010UL
977 #define SYSIO_SBUS_AFAR 0x2018UL
978 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
979 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
980 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
981 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
982 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
983 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
984 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
985 #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
986 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
987 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
988 #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
989 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
990 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id, struct pt_regs *regs)
991 {
992 struct sbus_bus *sbus = dev_id;
993 struct sbus_iommu *iommu = sbus->iommu;
994 unsigned long afsr_reg, afar_reg, reg_base;
995 unsigned long afsr, afar, error_bits;
996 int reported;
997
998 reg_base = iommu->sbus_control_reg - 0x2000UL;
999 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
1000 afar_reg = reg_base + SYSIO_SBUS_AFAR;
1001
1002 afsr = upa_readq(afsr_reg);
1003 afar = upa_readq(afar_reg);
1004
1005 /* Clear primary/secondary error status bits. */
1006 error_bits = afsr &
1007 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
1008 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
1009 upa_writeq(error_bits, afsr_reg);
1010
1011 /* Log the error. */
1012 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
1013 sbus->portid,
1014 (((error_bits & SYSIO_SBAFSR_PLE) ?
1015 "Late PIO Error" :
1016 ((error_bits & SYSIO_SBAFSR_PTO) ?
1017 "Time Out" :
1018 ((error_bits & SYSIO_SBAFSR_PBERR) ?
1019 "Error Ack" : "???")))),
1020 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
1021 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
1022 sbus->portid,
1023 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
1024 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
1025 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
1026 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
1027 reported = 0;
1028 if (afsr & SYSIO_SBAFSR_SLE) {
1029 reported++;
1030 printk("(Late PIO Error)");
1031 }
1032 if (afsr & SYSIO_SBAFSR_STO) {
1033 reported++;
1034 printk("(Time Out)");
1035 }
1036 if (afsr & SYSIO_SBAFSR_SBERR) {
1037 reported++;
1038 printk("(Error Ack)");
1039 }
1040 if (!reported)
1041 printk("(none)");
1042 printk("]\n");
1043
1044 /* XXX check iommu/strbuf for further error status XXX */
1045
1046 return IRQ_HANDLED;
1047 }
1048
1049 #define ECC_CONTROL 0x0020UL
1050 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
1051 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
1052 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
1053
1054 #define SYSIO_UE_INO 0x34
1055 #define SYSIO_CE_INO 0x35
1056 #define SYSIO_SBUSERR_INO 0x36
1057
1058 static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
1059 {
1060 struct sbus_iommu *iommu = sbus->iommu;
1061 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
1062 unsigned int irq;
1063 u64 control;
1064
1065 irq = sbus_build_irq(sbus, SYSIO_UE_INO);
1066 if (request_irq(irq, sysio_ue_handler,
1067 SA_SHIRQ, "SYSIO UE", sbus) < 0) {
1068 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
1069 sbus->portid);
1070 prom_halt();
1071 }
1072
1073 irq = sbus_build_irq(sbus, SYSIO_CE_INO);
1074 if (request_irq(irq, sysio_ce_handler,
1075 SA_SHIRQ, "SYSIO CE", sbus) < 0) {
1076 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
1077 sbus->portid);
1078 prom_halt();
1079 }
1080
1081 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
1082 if (request_irq(irq, sysio_sbus_error_handler,
1083 SA_SHIRQ, "SYSIO SBUS Error", sbus) < 0) {
1084 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
1085 sbus->portid);
1086 prom_halt();
1087 }
1088
1089 /* Now turn the error interrupts on and also enable ECC checking. */
1090 upa_writeq((SYSIO_ECNTRL_ECCEN |
1091 SYSIO_ECNTRL_UEEN |
1092 SYSIO_ECNTRL_CEEN),
1093 reg_base + ECC_CONTROL);
1094
1095 control = upa_readq(iommu->sbus_control_reg);
1096 control |= 0x100UL; /* SBUS Error Interrupt Enable */
1097 upa_writeq(control, iommu->sbus_control_reg);
1098 }
1099
1100 /* Boot time initialization. */
1101 void __init sbus_iommu_init(int prom_node, struct sbus_bus *sbus)
1102 {
1103 struct linux_prom64_registers rprop;
1104 struct sbus_iommu *iommu;
1105 unsigned long regs, tsb_base;
1106 u64 control;
1107 int err, i;
1108
1109 sbus->portid = prom_getintdefault(sbus->prom_node,
1110 "upa-portid", -1);
1111
1112 err = prom_getproperty(prom_node, "reg",
1113 (char *)&rprop, sizeof(rprop));
1114 if (err < 0) {
1115 prom_printf("sbus_iommu_init: Cannot map SYSIO control registers.\n");
1116 prom_halt();
1117 }
1118 regs = rprop.phys_addr;
1119
1120 iommu = kmalloc(sizeof(*iommu) + SMP_CACHE_BYTES, GFP_ATOMIC);
1121 if (iommu == NULL) {
1122 prom_printf("sbus_iommu_init: Fatal error, kmalloc(iommu) failed\n");
1123 prom_halt();
1124 }
1125
1126 /* Align on E$ line boundary. */
1127 iommu = (struct sbus_iommu *)
1128 (((unsigned long)iommu + (SMP_CACHE_BYTES - 1UL)) &
1129 ~(SMP_CACHE_BYTES - 1UL));
1130
1131 memset(iommu, 0, sizeof(*iommu));
1132
1133 /* We start with no consistent mappings. */
1134 iommu->lowest_consistent_map = CLUSTER_NPAGES;
1135
1136 for (i = 0; i < NCLUSTERS; i++) {
1137 iommu->alloc_info[i].flush = 0;
1138 iommu->alloc_info[i].next = 0;
1139 }
1140
1141 /* Setup spinlock. */
1142 spin_lock_init(&iommu->lock);
1143
1144 /* Init register offsets. */
1145 iommu->iommu_regs = regs + SYSIO_IOMMUREG_BASE;
1146 iommu->strbuf_regs = regs + SYSIO_STRBUFREG_BASE;
1147
1148 /* The SYSIO SBUS control register is used for dummy reads
1149 * in order to ensure write completion.
1150 */
1151 iommu->sbus_control_reg = regs + 0x2000UL;
1152
1153 /* Link into SYSIO software state. */
1154 sbus->iommu = iommu;
1155
1156 printk("SYSIO: UPA portID %x, at %016lx\n",
1157 sbus->portid, regs);
1158
1159 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
1160 control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
1161 control = ((7UL << 16UL) |
1162 (0UL << 2UL) |
1163 (1UL << 1UL) |
1164 (1UL << 0UL));
1165
1166 /* Using the above configuration we need 1MB iommu page
1167 * table (128K ioptes * 8 bytes per iopte). This is
1168 * page order 7 on UltraSparc.
1169 */
1170 tsb_base = __get_free_pages(GFP_ATOMIC, get_order(IO_TSB_SIZE));
1171 if (tsb_base == 0UL) {
1172 prom_printf("sbus_iommu_init: Fatal error, cannot alloc TSB table.\n");
1173 prom_halt();
1174 }
1175
1176 iommu->page_table = (iopte_t *) tsb_base;
1177 memset(iommu->page_table, 0, IO_TSB_SIZE);
1178
1179 upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
1180
1181 /* Clean out any cruft in the IOMMU using
1182 * diagnostic accesses.
1183 */
1184 for (i = 0; i < 16; i++) {
1185 unsigned long dram = iommu->iommu_regs + IOMMU_DRAMDIAG;
1186 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
1187
1188 dram += (unsigned long)i * 8UL;
1189 tag += (unsigned long)i * 8UL;
1190 upa_writeq(0, dram);
1191 upa_writeq(0, tag);
1192 }
1193 upa_readq(iommu->sbus_control_reg);
1194
1195 /* Give the TSB to SYSIO. */
1196 upa_writeq(__pa(tsb_base), iommu->iommu_regs + IOMMU_TSBBASE);
1197
1198 /* Setup streaming buffer, DE=1 SB_EN=1 */
1199 control = (1UL << 1UL) | (1UL << 0UL);
1200 upa_writeq(control, iommu->strbuf_regs + STRBUF_CONTROL);
1201
1202 /* Clear out the tags using diagnostics. */
1203 for (i = 0; i < 16; i++) {
1204 unsigned long ptag, ltag;
1205
1206 ptag = iommu->strbuf_regs + STRBUF_PTAGDIAG;
1207 ltag = iommu->strbuf_regs + STRBUF_LTAGDIAG;
1208 ptag += (unsigned long)i * 8UL;
1209 ltag += (unsigned long)i * 8UL;
1210
1211 upa_writeq(0UL, ptag);
1212 upa_writeq(0UL, ltag);
1213 }
1214
1215 /* Enable DVMA arbitration for all devices/slots. */
1216 control = upa_readq(iommu->sbus_control_reg);
1217 control |= 0x3fUL;
1218 upa_writeq(control, iommu->sbus_control_reg);
1219
1220 /* Now some Xfire specific grot... */
1221 if (this_is_starfire)
1222 sbus->starfire_cookie = starfire_hookup(sbus->portid);
1223 else
1224 sbus->starfire_cookie = NULL;
1225
1226 sysio_register_error_handlers(sbus);
1227 }
Linux kernel - Deliverables
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