1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
41 #include <asm/sections.h>
43 extern void calibrate_delay(void);
45 /* Please don't make this stuff initdata!!! --DaveM */
46 static unsigned char boot_cpu_id
;
48 cpumask_t cpu_online_map __read_mostly
= CPU_MASK_NONE
;
49 cpumask_t phys_cpu_present_map __read_mostly
= CPU_MASK_NONE
;
50 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
=
51 { [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
52 static cpumask_t smp_commenced_mask
;
53 static cpumask_t cpu_callout_map
;
55 void smp_info(struct seq_file
*m
)
59 seq_printf(m
, "State:\n");
60 for_each_online_cpu(i
)
61 seq_printf(m
, "CPU%d:\t\tonline\n", i
);
64 void smp_bogo(struct seq_file
*m
)
68 for_each_online_cpu(i
)
70 "Cpu%dBogo\t: %lu.%02lu\n"
71 "Cpu%dClkTck\t: %016lx\n",
72 i
, cpu_data(i
).udelay_val
/ (500000/HZ
),
73 (cpu_data(i
).udelay_val
/ (5000/HZ
)) % 100,
74 i
, cpu_data(i
).clock_tick
);
77 void __init
smp_store_cpu_info(int id
)
81 /* multiplier and counter set by
82 smp_setup_percpu_timer() */
83 cpu_data(id
).udelay_val
= loops_per_jiffy
;
85 cpu_find_by_mid(id
, &cpu_node
);
86 cpu_data(id
).clock_tick
= prom_getintdefault(cpu_node
,
87 "clock-frequency", 0);
89 def
= ((tlb_type
== hypervisor
) ? (8 * 1024) : (16 * 1024));
90 cpu_data(id
).dcache_size
= prom_getintdefault(cpu_node
, "dcache-size",
94 cpu_data(id
).dcache_line_size
=
95 prom_getintdefault(cpu_node
, "dcache-line-size", def
);
98 cpu_data(id
).icache_size
= prom_getintdefault(cpu_node
, "icache-size",
102 cpu_data(id
).icache_line_size
=
103 prom_getintdefault(cpu_node
, "icache-line-size", def
);
105 def
= ((tlb_type
== hypervisor
) ?
108 cpu_data(id
).ecache_size
= prom_getintdefault(cpu_node
, "ecache-size",
112 cpu_data(id
).ecache_line_size
=
113 prom_getintdefault(cpu_node
, "ecache-line-size", def
);
115 printk("CPU[%d]: Caches "
116 "D[sz(%d):line_sz(%d)] "
117 "I[sz(%d):line_sz(%d)] "
118 "E[sz(%d):line_sz(%d)]\n",
120 cpu_data(id
).dcache_size
, cpu_data(id
).dcache_line_size
,
121 cpu_data(id
).icache_size
, cpu_data(id
).icache_line_size
,
122 cpu_data(id
).ecache_size
, cpu_data(id
).ecache_line_size
);
125 static void smp_setup_percpu_timer(void);
127 static volatile unsigned long callin_flag
= 0;
129 void __init
smp_callin(void)
131 int cpuid
= hard_smp_processor_id();
133 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
135 if (tlb_type
== hypervisor
)
136 sun4v_ktsb_register();
140 smp_setup_percpu_timer();
142 if (cheetah_pcache_forced_on
)
143 cheetah_enable_pcache();
148 smp_store_cpu_info(cpuid
);
150 __asm__
__volatile__("membar #Sync\n\t"
151 "flush %%g6" : : : "memory");
153 /* Clear this or we will die instantly when we
154 * schedule back to this idler...
156 current_thread_info()->new_child
= 0;
158 /* Attach to the address space of init_task. */
159 atomic_inc(&init_mm
.mm_count
);
160 current
->active_mm
= &init_mm
;
162 while (!cpu_isset(cpuid
, smp_commenced_mask
))
165 cpu_set(cpuid
, cpu_online_map
);
167 /* idle thread is expected to have preempt disabled */
173 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
174 panic("SMP bolixed\n");
177 static unsigned long current_tick_offset __read_mostly
;
179 /* This tick register synchronization scheme is taken entirely from
180 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
182 * The only change I've made is to rework it so that the master
183 * initiates the synchonization instead of the slave. -DaveM
187 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
189 #define NUM_ROUNDS 64 /* magic value */
190 #define NUM_ITERS 5 /* likewise */
192 static DEFINE_SPINLOCK(itc_sync_lock
);
193 static unsigned long go
[SLAVE
+ 1];
195 #define DEBUG_TICK_SYNC 0
197 static inline long get_delta (long *rt
, long *master
)
199 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
200 unsigned long tcenter
, t0
, t1
, tm
;
203 for (i
= 0; i
< NUM_ITERS
; i
++) {
204 t0
= tick_ops
->get_tick();
207 while (!(tm
= go
[SLAVE
]))
211 t1
= tick_ops
->get_tick();
213 if (t1
- t0
< best_t1
- best_t0
)
214 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
217 *rt
= best_t1
- best_t0
;
218 *master
= best_tm
- best_t0
;
220 /* average best_t0 and best_t1 without overflow: */
221 tcenter
= (best_t0
/2 + best_t1
/2);
222 if (best_t0
% 2 + best_t1
% 2 == 2)
224 return tcenter
- best_tm
;
227 void smp_synchronize_tick_client(void)
229 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
230 unsigned long flags
, rt
, master_time_stamp
, bound
;
233 long rt
; /* roundtrip time */
234 long master
; /* master's timestamp */
235 long diff
; /* difference between midpoint and master's timestamp */
236 long lat
; /* estimate of itc adjustment latency */
245 local_irq_save(flags
);
247 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
248 delta
= get_delta(&rt
, &master_time_stamp
);
250 done
= 1; /* let's lock on to this... */
256 adjust_latency
+= -delta
;
257 adj
= -delta
+ adjust_latency
/4;
261 tick_ops
->add_tick(adj
, current_tick_offset
);
265 t
[i
].master
= master_time_stamp
;
267 t
[i
].lat
= adjust_latency
/4;
271 local_irq_restore(flags
);
274 for (i
= 0; i
< NUM_ROUNDS
; i
++)
275 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
276 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
279 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
280 "maxerr %lu cycles)\n", smp_processor_id(), delta
, rt
);
283 static void smp_start_sync_tick_client(int cpu
);
285 static void smp_synchronize_one_tick(int cpu
)
287 unsigned long flags
, i
;
291 smp_start_sync_tick_client(cpu
);
293 /* wait for client to be ready */
297 /* now let the client proceed into his loop */
301 spin_lock_irqsave(&itc_sync_lock
, flags
);
303 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
308 go
[SLAVE
] = tick_ops
->get_tick();
312 spin_unlock_irqrestore(&itc_sync_lock
, flags
);
315 extern void sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
);
317 extern unsigned long sparc64_cpu_startup
;
319 /* The OBP cpu startup callback truncates the 3rd arg cookie to
320 * 32-bits (I think) so to be safe we have it read the pointer
321 * contained here so we work on >4GB machines. -DaveM
323 static struct thread_info
*cpu_new_thread
= NULL
;
325 static int __devinit
smp_boot_one_cpu(unsigned int cpu
)
327 unsigned long entry
=
328 (unsigned long)(&sparc64_cpu_startup
);
329 unsigned long cookie
=
330 (unsigned long)(&cpu_new_thread
);
331 struct task_struct
*p
;
336 cpu_new_thread
= task_thread_info(p
);
337 cpu_set(cpu
, cpu_callout_map
);
339 if (tlb_type
== hypervisor
) {
340 /* Alloc the mondo queues, cpu will load them. */
341 sun4v_init_mondo_queues(0, cpu
, 1, 0);
343 prom_startcpu_cpuid(cpu
, entry
, cookie
);
347 cpu_find_by_mid(cpu
, &cpu_node
);
348 prom_startcpu(cpu_node
, entry
, cookie
);
351 for (timeout
= 0; timeout
< 5000000; timeout
++) {
360 printk("Processor %d is stuck.\n", cpu
);
361 cpu_clear(cpu
, cpu_callout_map
);
364 cpu_new_thread
= NULL
;
369 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
374 if (this_is_starfire
) {
375 /* map to real upaid */
376 cpu
= (((cpu
& 0x3c) << 1) |
377 ((cpu
& 0x40) >> 4) |
381 target
= (cpu
<< 14) | 0x70;
383 /* Ok, this is the real Spitfire Errata #54.
384 * One must read back from a UDB internal register
385 * after writes to the UDB interrupt dispatch, but
386 * before the membar Sync for that write.
387 * So we use the high UDB control register (ASI 0x7f,
388 * ADDR 0x20) for the dummy read. -DaveM
391 __asm__
__volatile__(
392 "wrpr %1, %2, %%pstate\n\t"
393 "stxa %4, [%0] %3\n\t"
394 "stxa %5, [%0+%8] %3\n\t"
396 "stxa %6, [%0+%8] %3\n\t"
398 "stxa %%g0, [%7] %3\n\t"
401 "ldxa [%%g1] 0x7f, %%g0\n\t"
404 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
405 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
406 "r" (0x10), "0" (tmp
)
409 /* NOTE: PSTATE_IE is still clear. */
412 __asm__
__volatile__("ldxa [%%g0] %1, %0"
414 : "i" (ASI_INTR_DISPATCH_STAT
));
416 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
423 } while (result
& 0x1);
424 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
427 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
428 smp_processor_id(), result
);
435 static __inline__
void spitfire_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
440 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
441 for_each_cpu_mask(i
, mask
)
442 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, i
);
445 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
446 * packet, but we have no use for that. However we do take advantage of
447 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
449 static void cheetah_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
452 int nack_busy_id
, is_jbus
;
454 if (cpus_empty(mask
))
457 /* Unfortunately, someone at Sun had the brilliant idea to make the
458 * busy/nack fields hard-coded by ITID number for this Ultra-III
459 * derivative processor.
461 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
462 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
463 (ver
>> 32) == __SERRANO_ID
);
465 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
468 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
469 : : "r" (pstate
), "i" (PSTATE_IE
));
471 /* Setup the dispatch data registers. */
472 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
473 "stxa %1, [%4] %6\n\t"
474 "stxa %2, [%5] %6\n\t"
477 : "r" (data0
), "r" (data1
), "r" (data2
),
478 "r" (0x40), "r" (0x50), "r" (0x60),
485 for_each_cpu_mask(i
, mask
) {
486 u64 target
= (i
<< 14) | 0x70;
489 target
|= (nack_busy_id
<< 24);
490 __asm__
__volatile__(
491 "stxa %%g0, [%0] %1\n\t"
494 : "r" (target
), "i" (ASI_INTR_W
));
499 /* Now, poll for completion. */
504 stuck
= 100000 * nack_busy_id
;
506 __asm__
__volatile__("ldxa [%%g0] %1, %0"
507 : "=r" (dispatch_stat
)
508 : "i" (ASI_INTR_DISPATCH_STAT
));
509 if (dispatch_stat
== 0UL) {
510 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
516 } while (dispatch_stat
& 0x5555555555555555UL
);
518 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
521 if ((dispatch_stat
& ~(0x5555555555555555UL
)) == 0) {
522 /* Busy bits will not clear, continue instead
523 * of freezing up on this cpu.
525 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
526 smp_processor_id(), dispatch_stat
);
528 int i
, this_busy_nack
= 0;
530 /* Delay some random time with interrupts enabled
531 * to prevent deadlock.
533 udelay(2 * nack_busy_id
);
535 /* Clear out the mask bits for cpus which did not
538 for_each_cpu_mask(i
, mask
) {
542 check_mask
= (0x2UL
<< (2*i
));
544 check_mask
= (0x2UL
<<
546 if ((dispatch_stat
& check_mask
) == 0)
556 /* Multi-cpu list version. */
557 static void hypervisor_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
559 struct trap_per_cpu
*tb
;
562 cpumask_t error_mask
;
563 unsigned long flags
, status
;
564 int cnt
, retries
, this_cpu
, prev_sent
, i
;
566 /* We have to do this whole thing with interrupts fully disabled.
567 * Otherwise if we send an xcall from interrupt context it will
568 * corrupt both our mondo block and cpu list state.
570 * One consequence of this is that we cannot use timeout mechanisms
571 * that depend upon interrupts being delivered locally. So, for
572 * example, we cannot sample jiffies and expect it to advance.
574 * Fortunately, udelay() uses %stick/%tick so we can use that.
576 local_irq_save(flags
);
578 this_cpu
= smp_processor_id();
579 tb
= &trap_block
[this_cpu
];
581 mondo
= __va(tb
->cpu_mondo_block_pa
);
587 cpu_list
= __va(tb
->cpu_list_pa
);
589 /* Setup the initial cpu list. */
591 for_each_cpu_mask(i
, mask
)
594 cpus_clear(error_mask
);
598 int forward_progress
, n_sent
;
600 status
= sun4v_cpu_mondo_send(cnt
,
602 tb
->cpu_mondo_block_pa
);
604 /* HV_EOK means all cpus received the xcall, we're done. */
605 if (likely(status
== HV_EOK
))
608 /* First, see if we made any forward progress.
610 * The hypervisor indicates successful sends by setting
611 * cpu list entries to the value 0xffff.
614 for (i
= 0; i
< cnt
; i
++) {
615 if (likely(cpu_list
[i
] == 0xffff))
619 forward_progress
= 0;
620 if (n_sent
> prev_sent
)
621 forward_progress
= 1;
625 /* If we get a HV_ECPUERROR, then one or more of the cpus
626 * in the list are in error state. Use the cpu_state()
627 * hypervisor call to find out which cpus are in error state.
629 if (unlikely(status
== HV_ECPUERROR
)) {
630 for (i
= 0; i
< cnt
; i
++) {
638 err
= sun4v_cpu_state(cpu
);
640 err
== HV_CPU_STATE_ERROR
) {
641 cpu_list
[i
] = 0xffff;
642 cpu_set(cpu
, error_mask
);
645 } else if (unlikely(status
!= HV_EWOULDBLOCK
))
646 goto fatal_mondo_error
;
648 /* Don't bother rewriting the CPU list, just leave the
649 * 0xffff and non-0xffff entries in there and the
650 * hypervisor will do the right thing.
652 * Only advance timeout state if we didn't make any
655 if (unlikely(!forward_progress
)) {
656 if (unlikely(++retries
> 10000))
657 goto fatal_mondo_timeout
;
659 /* Delay a little bit to let other cpus catch up
660 * on their cpu mondo queue work.
666 local_irq_restore(flags
);
668 if (unlikely(!cpus_empty(error_mask
)))
669 goto fatal_mondo_cpu_error
;
673 fatal_mondo_cpu_error
:
674 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo cpu error, some target cpus "
675 "were in error state\n",
677 printk(KERN_CRIT
"CPU[%d]: Error mask [ ", this_cpu
);
678 for_each_cpu_mask(i
, error_mask
)
684 local_irq_restore(flags
);
685 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo timeout, no forward "
686 " progress after %d retries.\n",
688 goto dump_cpu_list_and_out
;
691 local_irq_restore(flags
);
692 printk(KERN_CRIT
"CPU[%d]: Unexpected SUN4V mondo error %lu\n",
694 printk(KERN_CRIT
"CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
695 "mondo_block_pa(%lx)\n",
696 this_cpu
, cnt
, tb
->cpu_list_pa
, tb
->cpu_mondo_block_pa
);
698 dump_cpu_list_and_out
:
699 printk(KERN_CRIT
"CPU[%d]: CPU list [ ", this_cpu
);
700 for (i
= 0; i
< cnt
; i
++)
701 printk("%u ", cpu_list
[i
]);
705 /* Send cross call to all processors mentioned in MASK
708 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, cpumask_t mask
)
710 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
711 int this_cpu
= get_cpu();
713 cpus_and(mask
, mask
, cpu_online_map
);
714 cpu_clear(this_cpu
, mask
);
716 if (tlb_type
== spitfire
)
717 spitfire_xcall_deliver(data0
, data1
, data2
, mask
);
718 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
719 cheetah_xcall_deliver(data0
, data1
, data2
, mask
);
721 hypervisor_xcall_deliver(data0
, data1
, data2
, mask
);
722 /* NOTE: Caller runs local copy on master. */
727 extern unsigned long xcall_sync_tick
;
729 static void smp_start_sync_tick_client(int cpu
)
731 cpumask_t mask
= cpumask_of_cpu(cpu
);
733 smp_cross_call_masked(&xcall_sync_tick
,
737 /* Send cross call to all processors except self. */
738 #define smp_cross_call(func, ctx, data1, data2) \
739 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
741 struct call_data_struct
{
742 void (*func
) (void *info
);
748 static DEFINE_SPINLOCK(call_lock
);
749 static struct call_data_struct
*call_data
;
751 extern unsigned long xcall_call_function
;
754 * You must not call this function with disabled interrupts or from a
755 * hardware interrupt handler or from a bottom half handler.
757 static int smp_call_function_mask(void (*func
)(void *info
), void *info
,
758 int nonatomic
, int wait
, cpumask_t mask
)
760 struct call_data_struct data
;
764 /* Can deadlock when called with interrupts disabled */
765 WARN_ON(irqs_disabled());
769 atomic_set(&data
.finished
, 0);
772 spin_lock(&call_lock
);
774 cpu_clear(smp_processor_id(), mask
);
775 cpus
= cpus_weight(mask
);
781 smp_cross_call_masked(&xcall_call_function
, 0, 0, 0, mask
);
784 * Wait for other cpus to complete function or at
785 * least snap the call data.
788 while (atomic_read(&data
.finished
) != cpus
) {
796 spin_unlock(&call_lock
);
801 spin_unlock(&call_lock
);
802 printk("XCALL: Remote cpus not responding, ncpus=%d finished=%d\n",
803 cpus
, atomic_read(&data
.finished
));
807 int smp_call_function(void (*func
)(void *info
), void *info
,
808 int nonatomic
, int wait
)
810 return smp_call_function_mask(func
, info
, nonatomic
, wait
,
814 void smp_call_function_client(int irq
, struct pt_regs
*regs
)
816 void (*func
) (void *info
) = call_data
->func
;
817 void *info
= call_data
->info
;
819 clear_softint(1 << irq
);
820 if (call_data
->wait
) {
821 /* let initiator proceed only after completion */
823 atomic_inc(&call_data
->finished
);
825 /* let initiator proceed after getting data */
826 atomic_inc(&call_data
->finished
);
831 static void tsb_sync(void *info
)
833 struct trap_per_cpu
*tp
= &trap_block
[raw_smp_processor_id()];
834 struct mm_struct
*mm
= info
;
836 /* It is not valid to test "currrent->active_mm == mm" here.
838 * The value of "current" is not changed atomically with
839 * switch_mm(). But that's OK, we just need to check the
840 * current cpu's trap block PGD physical address.
842 if (tp
->pgd_paddr
== __pa(mm
->pgd
))
843 tsb_context_switch(mm
);
846 void smp_tsb_sync(struct mm_struct
*mm
)
848 smp_call_function_mask(tsb_sync
, mm
, 0, 1, mm
->cpu_vm_mask
);
851 extern unsigned long xcall_flush_tlb_mm
;
852 extern unsigned long xcall_flush_tlb_pending
;
853 extern unsigned long xcall_flush_tlb_kernel_range
;
854 extern unsigned long xcall_report_regs
;
855 extern unsigned long xcall_receive_signal
;
856 extern unsigned long xcall_new_mmu_context_version
;
858 #ifdef DCACHE_ALIASING_POSSIBLE
859 extern unsigned long xcall_flush_dcache_page_cheetah
;
861 extern unsigned long xcall_flush_dcache_page_spitfire
;
863 #ifdef CONFIG_DEBUG_DCFLUSH
864 extern atomic_t dcpage_flushes
;
865 extern atomic_t dcpage_flushes_xcall
;
868 static __inline__
void __local_flush_dcache_page(struct page
*page
)
870 #ifdef DCACHE_ALIASING_POSSIBLE
871 __flush_dcache_page(page_address(page
),
872 ((tlb_type
== spitfire
) &&
873 page_mapping(page
) != NULL
));
875 if (page_mapping(page
) != NULL
&&
876 tlb_type
== spitfire
)
877 __flush_icache_page(__pa(page_address(page
)));
881 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
883 cpumask_t mask
= cpumask_of_cpu(cpu
);
886 if (tlb_type
== hypervisor
)
889 #ifdef CONFIG_DEBUG_DCFLUSH
890 atomic_inc(&dcpage_flushes
);
893 this_cpu
= get_cpu();
895 if (cpu
== this_cpu
) {
896 __local_flush_dcache_page(page
);
897 } else if (cpu_online(cpu
)) {
898 void *pg_addr
= page_address(page
);
901 if (tlb_type
== spitfire
) {
903 ((u64
)&xcall_flush_dcache_page_spitfire
);
904 if (page_mapping(page
) != NULL
)
905 data0
|= ((u64
)1 << 32);
906 spitfire_xcall_deliver(data0
,
910 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
911 #ifdef DCACHE_ALIASING_POSSIBLE
913 ((u64
)&xcall_flush_dcache_page_cheetah
);
914 cheetah_xcall_deliver(data0
,
919 #ifdef CONFIG_DEBUG_DCFLUSH
920 atomic_inc(&dcpage_flushes_xcall
);
927 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
929 void *pg_addr
= page_address(page
);
930 cpumask_t mask
= cpu_online_map
;
934 if (tlb_type
== hypervisor
)
937 this_cpu
= get_cpu();
939 cpu_clear(this_cpu
, mask
);
941 #ifdef CONFIG_DEBUG_DCFLUSH
942 atomic_inc(&dcpage_flushes
);
944 if (cpus_empty(mask
))
946 if (tlb_type
== spitfire
) {
947 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
948 if (page_mapping(page
) != NULL
)
949 data0
|= ((u64
)1 << 32);
950 spitfire_xcall_deliver(data0
,
954 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
955 #ifdef DCACHE_ALIASING_POSSIBLE
956 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
957 cheetah_xcall_deliver(data0
,
962 #ifdef CONFIG_DEBUG_DCFLUSH
963 atomic_inc(&dcpage_flushes_xcall
);
966 __local_flush_dcache_page(page
);
971 static void __smp_receive_signal_mask(cpumask_t mask
)
973 smp_cross_call_masked(&xcall_receive_signal
, 0, 0, 0, mask
);
976 void smp_receive_signal(int cpu
)
978 cpumask_t mask
= cpumask_of_cpu(cpu
);
981 __smp_receive_signal_mask(mask
);
984 void smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
986 clear_softint(1 << irq
);
989 void smp_new_mmu_context_version_client(int irq
, struct pt_regs
*regs
)
991 struct mm_struct
*mm
;
994 clear_softint(1 << irq
);
996 /* See if we need to allocate a new TLB context because
997 * the version of the one we are using is now out of date.
999 mm
= current
->active_mm
;
1000 if (unlikely(!mm
|| (mm
== &init_mm
)))
1003 spin_lock_irqsave(&mm
->context
.lock
, flags
);
1005 if (unlikely(!CTX_VALID(mm
->context
)))
1006 get_new_mmu_context(mm
);
1008 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
1010 load_secondary_context(mm
);
1011 __flush_tlb_mm(CTX_HWBITS(mm
->context
),
1015 void smp_new_mmu_context_version(void)
1017 smp_cross_call(&xcall_new_mmu_context_version
, 0, 0, 0);
1020 void smp_report_regs(void)
1022 smp_cross_call(&xcall_report_regs
, 0, 0, 0);
1025 /* We know that the window frames of the user have been flushed
1026 * to the stack before we get here because all callers of us
1027 * are flush_tlb_*() routines, and these run after flush_cache_*()
1028 * which performs the flushw.
1030 * The SMP TLB coherency scheme we use works as follows:
1032 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1033 * space has (potentially) executed on, this is the heuristic
1034 * we use to avoid doing cross calls.
1036 * Also, for flushing from kswapd and also for clones, we
1037 * use cpu_vm_mask as the list of cpus to make run the TLB.
1039 * 2) TLB context numbers are shared globally across all processors
1040 * in the system, this allows us to play several games to avoid
1043 * One invariant is that when a cpu switches to a process, and
1044 * that processes tsk->active_mm->cpu_vm_mask does not have the
1045 * current cpu's bit set, that tlb context is flushed locally.
1047 * If the address space is non-shared (ie. mm->count == 1) we avoid
1048 * cross calls when we want to flush the currently running process's
1049 * tlb state. This is done by clearing all cpu bits except the current
1050 * processor's in current->active_mm->cpu_vm_mask and performing the
1051 * flush locally only. This will force any subsequent cpus which run
1052 * this task to flush the context from the local tlb if the process
1053 * migrates to another cpu (again).
1055 * 3) For shared address spaces (threads) and swapping we bite the
1056 * bullet for most cases and perform the cross call (but only to
1057 * the cpus listed in cpu_vm_mask).
1059 * The performance gain from "optimizing" away the cross call for threads is
1060 * questionable (in theory the big win for threads is the massive sharing of
1061 * address space state across processors).
1064 /* This currently is only used by the hugetlb arch pre-fault
1065 * hook on UltraSPARC-III+ and later when changing the pagesize
1066 * bits of the context register for an address space.
1068 void smp_flush_tlb_mm(struct mm_struct
*mm
)
1070 u32 ctx
= CTX_HWBITS(mm
->context
);
1071 int cpu
= get_cpu();
1073 if (atomic_read(&mm
->mm_users
) == 1) {
1074 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1075 goto local_flush_and_out
;
1078 smp_cross_call_masked(&xcall_flush_tlb_mm
,
1082 local_flush_and_out
:
1083 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
1088 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
1090 u32 ctx
= CTX_HWBITS(mm
->context
);
1091 int cpu
= get_cpu();
1093 if (mm
== current
->active_mm
&& atomic_read(&mm
->mm_users
) == 1)
1094 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1096 smp_cross_call_masked(&xcall_flush_tlb_pending
,
1097 ctx
, nr
, (unsigned long) vaddrs
,
1100 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1105 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1108 end
= PAGE_ALIGN(end
);
1110 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1113 __flush_tlb_kernel_range(start
, end
);
1118 /* #define CAPTURE_DEBUG */
1119 extern unsigned long xcall_capture
;
1121 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1122 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1123 static unsigned long penguins_are_doing_time
;
1125 void smp_capture(void)
1127 int result
= atomic_add_ret(1, &smp_capture_depth
);
1130 int ncpus
= num_online_cpus();
1132 #ifdef CAPTURE_DEBUG
1133 printk("CPU[%d]: Sending penguins to jail...",
1134 smp_processor_id());
1136 penguins_are_doing_time
= 1;
1137 membar_storestore_loadstore();
1138 atomic_inc(&smp_capture_registry
);
1139 smp_cross_call(&xcall_capture
, 0, 0, 0);
1140 while (atomic_read(&smp_capture_registry
) != ncpus
)
1142 #ifdef CAPTURE_DEBUG
1148 void smp_release(void)
1150 if (atomic_dec_and_test(&smp_capture_depth
)) {
1151 #ifdef CAPTURE_DEBUG
1152 printk("CPU[%d]: Giving pardon to "
1153 "imprisoned penguins\n",
1154 smp_processor_id());
1156 penguins_are_doing_time
= 0;
1157 membar_storeload_storestore();
1158 atomic_dec(&smp_capture_registry
);
1162 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1163 * can service tlb flush xcalls...
1165 extern void prom_world(int);
1167 void smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1169 clear_softint(1 << irq
);
1173 __asm__
__volatile__("flushw");
1175 atomic_inc(&smp_capture_registry
);
1176 membar_storeload_storestore();
1177 while (penguins_are_doing_time
)
1179 atomic_dec(&smp_capture_registry
);
1185 #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
1186 #define prof_counter(__cpu) cpu_data(__cpu).counter
1188 void smp_percpu_timer_interrupt(struct pt_regs
*regs
)
1190 unsigned long compare
, tick
, pstate
;
1191 int cpu
= smp_processor_id();
1192 int user
= user_mode(regs
);
1195 * Check for level 14 softint.
1198 unsigned long tick_mask
= tick_ops
->softint_mask
;
1200 if (!(get_softint() & tick_mask
)) {
1201 extern void handler_irq(int, struct pt_regs
*);
1203 handler_irq(14, regs
);
1206 clear_softint(tick_mask
);
1210 profile_tick(CPU_PROFILING
, regs
);
1211 if (!--prof_counter(cpu
)) {
1214 if (cpu
== boot_cpu_id
) {
1215 kstat_this_cpu
.irqs
[0]++;
1216 timer_tick_interrupt(regs
);
1219 update_process_times(user
);
1223 prof_counter(cpu
) = prof_multiplier(cpu
);
1226 /* Guarantee that the following sequences execute
1229 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
1230 "wrpr %0, %1, %%pstate"
1234 compare
= tick_ops
->add_compare(current_tick_offset
);
1235 tick
= tick_ops
->get_tick();
1237 /* Restore PSTATE_IE. */
1238 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
1241 } while (time_after_eq(tick
, compare
));
1244 static void __init
smp_setup_percpu_timer(void)
1246 int cpu
= smp_processor_id();
1247 unsigned long pstate
;
1249 prof_counter(cpu
) = prof_multiplier(cpu
) = 1;
1251 /* Guarantee that the following sequences execute
1254 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
1255 "wrpr %0, %1, %%pstate"
1259 tick_ops
->init_tick(current_tick_offset
);
1261 /* Restore PSTATE_IE. */
1262 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
1267 void __init
smp_tick_init(void)
1269 boot_cpu_id
= hard_smp_processor_id();
1270 current_tick_offset
= timer_tick_offset
;
1272 cpu_set(boot_cpu_id
, cpu_online_map
);
1273 prof_counter(boot_cpu_id
) = prof_multiplier(boot_cpu_id
) = 1;
1276 /* /proc/profile writes can call this, don't __init it please. */
1277 static DEFINE_SPINLOCK(prof_setup_lock
);
1279 int setup_profiling_timer(unsigned int multiplier
)
1281 unsigned long flags
;
1284 if ((!multiplier
) || (timer_tick_offset
/ multiplier
) < 1000)
1287 spin_lock_irqsave(&prof_setup_lock
, flags
);
1289 prof_multiplier(i
) = multiplier
;
1290 current_tick_offset
= (timer_tick_offset
/ multiplier
);
1291 spin_unlock_irqrestore(&prof_setup_lock
, flags
);
1296 /* Constrain the number of cpus to max_cpus. */
1297 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1301 if (num_possible_cpus() > max_cpus
) {
1305 while (!cpu_find_by_instance(instance
, NULL
, &mid
)) {
1306 if (mid
!= boot_cpu_id
) {
1307 cpu_clear(mid
, phys_cpu_present_map
);
1308 cpu_clear(mid
, cpu_present_map
);
1309 if (num_possible_cpus() <= max_cpus
)
1317 if (tlb_type
== hypervisor
) {
1320 /* XXX get this mapping from machine description */
1322 if ((j
>> 2) == (i
>> 2))
1323 cpu_set(j
, cpu_sibling_map
[i
]);
1326 cpu_set(i
, cpu_sibling_map
[i
]);
1330 smp_store_cpu_info(boot_cpu_id
);
1333 /* Set this up early so that things like the scheduler can init
1334 * properly. We use the same cpu mask for both the present and
1337 void __init
smp_setup_cpu_possible_map(void)
1342 while (!cpu_find_by_instance(instance
, NULL
, &mid
)) {
1343 if (mid
< NR_CPUS
) {
1344 cpu_set(mid
, phys_cpu_present_map
);
1345 cpu_set(mid
, cpu_present_map
);
1351 void __devinit
smp_prepare_boot_cpu(void)
1353 int cpu
= hard_smp_processor_id();
1355 if (cpu
>= NR_CPUS
) {
1356 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1360 current_thread_info()->cpu
= cpu
;
1361 __local_per_cpu_offset
= __per_cpu_offset(cpu
);
1363 cpu_set(smp_processor_id(), cpu_online_map
);
1364 cpu_set(smp_processor_id(), phys_cpu_present_map
);
1367 int __devinit
__cpu_up(unsigned int cpu
)
1369 int ret
= smp_boot_one_cpu(cpu
);
1372 cpu_set(cpu
, smp_commenced_mask
);
1373 while (!cpu_isset(cpu
, cpu_online_map
))
1375 if (!cpu_isset(cpu
, cpu_online_map
)) {
1378 /* On SUN4V, writes to %tick and %stick are
1381 if (tlb_type
!= hypervisor
)
1382 smp_synchronize_one_tick(cpu
);
1388 void __init
smp_cpus_done(unsigned int max_cpus
)
1390 unsigned long bogosum
= 0;
1393 for_each_online_cpu(i
)
1394 bogosum
+= cpu_data(i
).udelay_val
;
1395 printk("Total of %ld processors activated "
1396 "(%lu.%02lu BogoMIPS).\n",
1397 (long) num_online_cpus(),
1398 bogosum
/(500000/HZ
),
1399 (bogosum
/(5000/HZ
))%100);
1402 void smp_send_reschedule(int cpu
)
1404 smp_receive_signal(cpu
);
1407 /* This is a nop because we capture all other cpus
1408 * anyways when making the PROM active.
1410 void smp_send_stop(void)
1414 unsigned long __per_cpu_base __read_mostly
;
1415 unsigned long __per_cpu_shift __read_mostly
;
1417 EXPORT_SYMBOL(__per_cpu_base
);
1418 EXPORT_SYMBOL(__per_cpu_shift
);
1420 void __init
setup_per_cpu_areas(void)
1422 unsigned long goal
, size
, i
;
1425 /* Copy section for each CPU (we discard the original) */
1426 goal
= ALIGN(__per_cpu_end
- __per_cpu_start
, SMP_CACHE_BYTES
);
1427 #ifdef CONFIG_MODULES
1428 if (goal
< PERCPU_ENOUGH_ROOM
)
1429 goal
= PERCPU_ENOUGH_ROOM
;
1431 __per_cpu_shift
= 0;
1432 for (size
= 1UL; size
< goal
; size
<<= 1UL)
1435 ptr
= alloc_bootmem(size
* NR_CPUS
);
1437 __per_cpu_base
= ptr
- __per_cpu_start
;
1439 for (i
= 0; i
< NR_CPUS
; i
++, ptr
+= size
)
1440 memcpy(ptr
, __per_cpu_start
, __per_cpu_end
- __per_cpu_start
);