1 /* time.c: UltraSparc timer and TOD clock support.
3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Based largely on code which is:
8 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/smp_lock.h>
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/string.h>
19 #include <linux/interrupt.h>
20 #include <linux/time.h>
21 #include <linux/timex.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/delay.h>
26 #include <linux/profile.h>
27 #include <linux/bcd.h>
28 #include <linux/jiffies.h>
29 #include <linux/cpufreq.h>
30 #include <linux/percpu.h>
31 #include <linux/miscdevice.h>
32 #include <linux/rtc.h>
33 #include <linux/rtc/m48t59.h>
34 #include <linux/kernel_stat.h>
35 #include <linux/clockchips.h>
36 #include <linux/clocksource.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
40 #include <asm/oplib.h>
41 #include <asm/timer.h>
45 #include <asm/starfire.h>
47 #include <asm/sections.h>
48 #include <asm/cpudata.h>
49 #include <asm/uaccess.h>
50 #include <asm/irq_regs.h>
54 DEFINE_SPINLOCK(rtc_lock
);
56 #define TICK_PRIV_BIT (1UL << 63)
57 #define TICKCMP_IRQ_BIT (1UL << 63)
60 unsigned long profile_pc(struct pt_regs
*regs
)
62 unsigned long pc
= instruction_pointer(regs
);
64 if (in_lock_functions(pc
))
65 return regs
->u_regs
[UREG_RETPC
];
68 EXPORT_SYMBOL(profile_pc
);
71 static void tick_disable_protection(void)
73 /* Set things up so user can access tick register for profiling
74 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
75 * read back of %tick after writing it.
81 "1: rd %%tick, %%g2\n"
82 " add %%g2, 6, %%g2\n"
83 " andn %%g2, %0, %%g2\n"
84 " wrpr %%g2, 0, %%tick\n"
91 static void tick_disable_irq(void)
97 "1: wr %0, 0x0, %%tick_cmpr\n"
98 " rd %%tick_cmpr, %%g0"
100 : "r" (TICKCMP_IRQ_BIT
));
103 static void tick_init_tick(void)
105 tick_disable_protection();
109 static unsigned long tick_get_tick(void)
113 __asm__
__volatile__("rd %%tick, %0\n\t"
117 return ret
& ~TICK_PRIV_BIT
;
120 static int tick_add_compare(unsigned long adj
)
122 unsigned long orig_tick
, new_tick
, new_compare
;
124 __asm__
__volatile__("rd %%tick, %0"
127 orig_tick
&= ~TICKCMP_IRQ_BIT
;
129 /* Workaround for Spitfire Errata (#54 I think??), I discovered
130 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
133 * On Blackbird writes to %tick_cmpr can fail, the
134 * workaround seems to be to execute the wr instruction
135 * at the start of an I-cache line, and perform a dummy
136 * read back from %tick_cmpr right after writing to it. -DaveM
138 __asm__
__volatile__("ba,pt %%xcc, 1f\n\t"
139 " add %1, %2, %0\n\t"
142 "wr %0, 0, %%tick_cmpr\n\t"
143 "rd %%tick_cmpr, %%g0\n\t"
145 : "r" (orig_tick
), "r" (adj
));
147 __asm__
__volatile__("rd %%tick, %0"
149 new_tick
&= ~TICKCMP_IRQ_BIT
;
151 return ((long)(new_tick
- (orig_tick
+adj
))) > 0L;
154 static unsigned long tick_add_tick(unsigned long adj
)
156 unsigned long new_tick
;
158 /* Also need to handle Blackbird bug here too. */
159 __asm__
__volatile__("rd %%tick, %0\n\t"
161 "wrpr %0, 0, %%tick\n\t"
168 static struct sparc64_tick_ops tick_operations __read_mostly
= {
170 .init_tick
= tick_init_tick
,
171 .disable_irq
= tick_disable_irq
,
172 .get_tick
= tick_get_tick
,
173 .add_tick
= tick_add_tick
,
174 .add_compare
= tick_add_compare
,
175 .softint_mask
= 1UL << 0,
178 struct sparc64_tick_ops
*tick_ops __read_mostly
= &tick_operations
;
180 static void stick_disable_irq(void)
182 __asm__
__volatile__(
183 "wr %0, 0x0, %%asr25"
185 : "r" (TICKCMP_IRQ_BIT
));
188 static void stick_init_tick(void)
190 /* Writes to the %tick and %stick register are not
191 * allowed on sun4v. The Hypervisor controls that
194 if (tlb_type
!= hypervisor
) {
195 tick_disable_protection();
198 /* Let the user get at STICK too. */
199 __asm__
__volatile__(
200 " rd %%asr24, %%g2\n"
201 " andn %%g2, %0, %%g2\n"
202 " wr %%g2, 0, %%asr24"
204 : "r" (TICK_PRIV_BIT
)
211 static unsigned long stick_get_tick(void)
215 __asm__
__volatile__("rd %%asr24, %0"
218 return ret
& ~TICK_PRIV_BIT
;
221 static unsigned long stick_add_tick(unsigned long adj
)
223 unsigned long new_tick
;
225 __asm__
__volatile__("rd %%asr24, %0\n\t"
227 "wr %0, 0, %%asr24\n\t"
234 static int stick_add_compare(unsigned long adj
)
236 unsigned long orig_tick
, new_tick
;
238 __asm__
__volatile__("rd %%asr24, %0"
240 orig_tick
&= ~TICKCMP_IRQ_BIT
;
242 __asm__
__volatile__("wr %0, 0, %%asr25"
244 : "r" (orig_tick
+ adj
));
246 __asm__
__volatile__("rd %%asr24, %0"
248 new_tick
&= ~TICKCMP_IRQ_BIT
;
250 return ((long)(new_tick
- (orig_tick
+adj
))) > 0L;
253 static struct sparc64_tick_ops stick_operations __read_mostly
= {
255 .init_tick
= stick_init_tick
,
256 .disable_irq
= stick_disable_irq
,
257 .get_tick
= stick_get_tick
,
258 .add_tick
= stick_add_tick
,
259 .add_compare
= stick_add_compare
,
260 .softint_mask
= 1UL << 16,
263 /* On Hummingbird the STICK/STICK_CMPR register is implemented
264 * in I/O space. There are two 64-bit registers each, the
265 * first holds the low 32-bits of the value and the second holds
268 * Since STICK is constantly updating, we have to access it carefully.
270 * The sequence we use to read is:
273 * 3) read high again, if it rolled re-read both low and high again.
275 * Writing STICK safely is also tricky:
276 * 1) write low to zero
280 #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
281 #define HBIRD_STICK_ADDR 0x1fe0000f070UL
283 static unsigned long __hbird_read_stick(void)
285 unsigned long ret
, tmp1
, tmp2
, tmp3
;
286 unsigned long addr
= HBIRD_STICK_ADDR
+8;
288 __asm__
__volatile__("ldxa [%1] %5, %2\n"
290 "sub %1, 0x8, %1\n\t"
291 "ldxa [%1] %5, %3\n\t"
292 "add %1, 0x8, %1\n\t"
293 "ldxa [%1] %5, %4\n\t"
295 "bne,a,pn %%xcc, 1b\n\t"
297 "sllx %4, 32, %4\n\t"
299 : "=&r" (ret
), "=&r" (addr
),
300 "=&r" (tmp1
), "=&r" (tmp2
), "=&r" (tmp3
)
301 : "i" (ASI_PHYS_BYPASS_EC_E
), "1" (addr
));
306 static void __hbird_write_stick(unsigned long val
)
308 unsigned long low
= (val
& 0xffffffffUL
);
309 unsigned long high
= (val
>> 32UL);
310 unsigned long addr
= HBIRD_STICK_ADDR
;
312 __asm__
__volatile__("stxa %%g0, [%0] %4\n\t"
313 "add %0, 0x8, %0\n\t"
314 "stxa %3, [%0] %4\n\t"
315 "sub %0, 0x8, %0\n\t"
318 : "0" (addr
), "r" (low
), "r" (high
),
319 "i" (ASI_PHYS_BYPASS_EC_E
));
322 static void __hbird_write_compare(unsigned long val
)
324 unsigned long low
= (val
& 0xffffffffUL
);
325 unsigned long high
= (val
>> 32UL);
326 unsigned long addr
= HBIRD_STICKCMP_ADDR
+ 0x8UL
;
328 __asm__
__volatile__("stxa %3, [%0] %4\n\t"
329 "sub %0, 0x8, %0\n\t"
332 : "0" (addr
), "r" (low
), "r" (high
),
333 "i" (ASI_PHYS_BYPASS_EC_E
));
336 static void hbtick_disable_irq(void)
338 __hbird_write_compare(TICKCMP_IRQ_BIT
);
341 static void hbtick_init_tick(void)
343 tick_disable_protection();
345 /* XXX This seems to be necessary to 'jumpstart' Hummingbird
346 * XXX into actually sending STICK interrupts. I think because
347 * XXX of how we store %tick_cmpr in head.S this somehow resets the
348 * XXX {TICK + STICK} interrupt mux. -DaveM
350 __hbird_write_stick(__hbird_read_stick());
352 hbtick_disable_irq();
355 static unsigned long hbtick_get_tick(void)
357 return __hbird_read_stick() & ~TICK_PRIV_BIT
;
360 static unsigned long hbtick_add_tick(unsigned long adj
)
364 val
= __hbird_read_stick() + adj
;
365 __hbird_write_stick(val
);
370 static int hbtick_add_compare(unsigned long adj
)
372 unsigned long val
= __hbird_read_stick();
375 val
&= ~TICKCMP_IRQ_BIT
;
377 __hbird_write_compare(val
);
379 val2
= __hbird_read_stick() & ~TICKCMP_IRQ_BIT
;
381 return ((long)(val2
- val
)) > 0L;
384 static struct sparc64_tick_ops hbtick_operations __read_mostly
= {
386 .init_tick
= hbtick_init_tick
,
387 .disable_irq
= hbtick_disable_irq
,
388 .get_tick
= hbtick_get_tick
,
389 .add_tick
= hbtick_add_tick
,
390 .add_compare
= hbtick_add_compare
,
391 .softint_mask
= 1UL << 0,
394 static unsigned long timer_ticks_per_nsec_quotient __read_mostly
;
396 int update_persistent_clock(struct timespec now
)
398 struct rtc_device
*rtc
= rtc_class_open("rtc0");
401 return rtc_set_mmss(rtc
, now
.tv_sec
);
406 unsigned long cmos_regs
;
407 EXPORT_SYMBOL(cmos_regs
);
409 struct resource rtc_cmos_resource
;
411 static struct platform_device rtc_cmos_device
= {
414 .resource
= &rtc_cmos_resource
,
418 static int __devinit
rtc_probe(struct of_device
*op
, const struct of_device_id
*match
)
422 printk(KERN_INFO
"%s: RTC regs at 0x%lx\n",
423 op
->node
->full_name
, op
->resource
[0].start
);
425 /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons
426 * up a fake resource so that the probe works for all cases.
427 * When the RTC is behind an ISA bus it will have IORESOURCE_IO
428 * already, whereas when it's behind EBUS is will be IORESOURCE_MEM.
431 r
= &rtc_cmos_resource
;
432 r
->flags
= IORESOURCE_IO
;
433 r
->name
= op
->resource
[0].name
;
434 r
->start
= op
->resource
[0].start
;
435 r
->end
= op
->resource
[0].end
;
437 cmos_regs
= op
->resource
[0].start
;
438 return platform_device_register(&rtc_cmos_device
);
441 static struct of_device_id __initdata rtc_match
[] = {
444 .compatible
= "m5819",
448 .compatible
= "isa-m5819p",
452 .compatible
= "isa-m5823p",
456 .compatible
= "ds1287",
461 static struct of_platform_driver rtc_driver
= {
462 .match_table
= rtc_match
,
469 static struct platform_device rtc_bq4802_device
= {
470 .name
= "rtc-bq4802",
475 static int __devinit
bq4802_probe(struct of_device
*op
, const struct of_device_id
*match
)
478 printk(KERN_INFO
"%s: BQ4802 regs at 0x%lx\n",
479 op
->node
->full_name
, op
->resource
[0].start
);
481 rtc_bq4802_device
.resource
= &op
->resource
[0];
482 return platform_device_register(&rtc_bq4802_device
);
485 static struct of_device_id __initdata bq4802_match
[] = {
488 .compatible
= "bq4802",
492 static struct of_platform_driver bq4802_driver
= {
493 .match_table
= bq4802_match
,
494 .probe
= bq4802_probe
,
500 static unsigned char mostek_read_byte(struct device
*dev
, u32 ofs
)
502 struct platform_device
*pdev
= to_platform_device(dev
);
506 regs
= (void __iomem
*) pdev
->resource
[0].start
;
507 val
= readb(regs
+ ofs
);
509 /* the year 0 is 1968 */
510 if (ofs
== M48T59_YEAR
) {
518 static void mostek_write_byte(struct device
*dev
, u32 ofs
, u8 val
)
520 struct platform_device
*pdev
= to_platform_device(dev
);
523 regs
= (void __iomem
*) pdev
->resource
[0].start
;
524 if (ofs
== M48T59_YEAR
) {
531 if ((val
& 0xf0) > 0x9A)
534 writeb(val
, regs
+ ofs
);
537 static struct m48t59_plat_data m48t59_data
= {
538 .read_byte
= mostek_read_byte
,
539 .write_byte
= mostek_write_byte
,
542 static struct platform_device m48t59_rtc
= {
543 .name
= "rtc-m48t59",
547 .platform_data
= &m48t59_data
,
551 static int __devinit
mostek_probe(struct of_device
*op
, const struct of_device_id
*match
)
553 struct device_node
*dp
= op
->node
;
555 /* On an Enterprise system there can be multiple mostek clocks.
556 * We should only match the one that is on the central FHC bus.
558 if (!strcmp(dp
->parent
->name
, "fhc") &&
559 strcmp(dp
->parent
->parent
->name
, "central") != 0)
562 printk(KERN_INFO
"%s: Mostek regs at 0x%lx\n",
563 dp
->full_name
, op
->resource
[0].start
);
565 m48t59_rtc
.resource
= &op
->resource
[0];
566 return platform_device_register(&m48t59_rtc
);
569 static struct of_device_id __initdata mostek_match
[] = {
576 static struct of_platform_driver mostek_driver
= {
577 .match_table
= mostek_match
,
578 .probe
= mostek_probe
,
584 static struct platform_device rtc_sun4v_device
= {
589 static struct platform_device rtc_starfire_device
= {
590 .name
= "rtc-starfire",
594 static int __init
clock_init(void)
596 if (this_is_starfire
)
597 return platform_device_register(&rtc_starfire_device
);
599 if (tlb_type
== hypervisor
)
600 return platform_device_register(&rtc_sun4v_device
);
602 (void) of_register_driver(&rtc_driver
, &of_platform_bus_type
);
603 (void) of_register_driver(&mostek_driver
, &of_platform_bus_type
);
604 (void) of_register_driver(&bq4802_driver
, &of_platform_bus_type
);
609 /* Must be after subsys_initcall() so that busses are probed. Must
610 * be before device_initcall() because things like the RTC driver
611 * need to see the clock registers.
613 fs_initcall(clock_init
);
615 /* This is gets the master TICK_INT timer going. */
616 static unsigned long sparc64_init_timers(void)
618 struct device_node
*dp
;
621 dp
= of_find_node_by_path("/");
622 if (tlb_type
== spitfire
) {
623 unsigned long ver
, manuf
, impl
;
625 __asm__
__volatile__ ("rdpr %%ver, %0"
627 manuf
= ((ver
>> 48) & 0xffff);
628 impl
= ((ver
>> 32) & 0xffff);
629 if (manuf
== 0x17 && impl
== 0x13) {
630 /* Hummingbird, aka Ultra-IIe */
631 tick_ops
= &hbtick_operations
;
632 clock
= of_getintprop_default(dp
, "stick-frequency", 0);
634 tick_ops
= &tick_operations
;
635 clock
= local_cpu_data().clock_tick
;
638 tick_ops
= &stick_operations
;
639 clock
= of_getintprop_default(dp
, "stick-frequency", 0);
646 unsigned long clock_tick_ref
;
647 unsigned int ref_freq
;
649 static DEFINE_PER_CPU(struct freq_table
, sparc64_freq_table
) = { 0, 0 };
651 unsigned long sparc64_get_clock_tick(unsigned int cpu
)
653 struct freq_table
*ft
= &per_cpu(sparc64_freq_table
, cpu
);
655 if (ft
->clock_tick_ref
)
656 return ft
->clock_tick_ref
;
657 return cpu_data(cpu
).clock_tick
;
660 #ifdef CONFIG_CPU_FREQ
662 static int sparc64_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
665 struct cpufreq_freqs
*freq
= data
;
666 unsigned int cpu
= freq
->cpu
;
667 struct freq_table
*ft
= &per_cpu(sparc64_freq_table
, cpu
);
670 ft
->ref_freq
= freq
->old
;
671 ft
->clock_tick_ref
= cpu_data(cpu
).clock_tick
;
673 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
674 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new) ||
675 (val
== CPUFREQ_RESUMECHANGE
)) {
676 cpu_data(cpu
).clock_tick
=
677 cpufreq_scale(ft
->clock_tick_ref
,
685 static struct notifier_block sparc64_cpufreq_notifier_block
= {
686 .notifier_call
= sparc64_cpufreq_notifier
689 static int __init
register_sparc64_cpufreq_notifier(void)
692 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block
,
693 CPUFREQ_TRANSITION_NOTIFIER
);
697 core_initcall(register_sparc64_cpufreq_notifier
);
699 #endif /* CONFIG_CPU_FREQ */
701 static int sparc64_next_event(unsigned long delta
,
702 struct clock_event_device
*evt
)
704 return tick_ops
->add_compare(delta
) ? -ETIME
: 0;
707 static void sparc64_timer_setup(enum clock_event_mode mode
,
708 struct clock_event_device
*evt
)
711 case CLOCK_EVT_MODE_ONESHOT
:
712 case CLOCK_EVT_MODE_RESUME
:
715 case CLOCK_EVT_MODE_SHUTDOWN
:
716 tick_ops
->disable_irq();
719 case CLOCK_EVT_MODE_PERIODIC
:
720 case CLOCK_EVT_MODE_UNUSED
:
726 static struct clock_event_device sparc64_clockevent
= {
727 .features
= CLOCK_EVT_FEAT_ONESHOT
,
728 .set_mode
= sparc64_timer_setup
,
729 .set_next_event
= sparc64_next_event
,
734 static DEFINE_PER_CPU(struct clock_event_device
, sparc64_events
);
736 void timer_interrupt(int irq
, struct pt_regs
*regs
)
738 struct pt_regs
*old_regs
= set_irq_regs(regs
);
739 unsigned long tick_mask
= tick_ops
->softint_mask
;
740 int cpu
= smp_processor_id();
741 struct clock_event_device
*evt
= &per_cpu(sparc64_events
, cpu
);
743 clear_softint(tick_mask
);
747 kstat_this_cpu
.irqs
[0]++;
749 if (unlikely(!evt
->event_handler
)) {
751 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu
);
753 evt
->event_handler(evt
);
757 set_irq_regs(old_regs
);
760 void __devinit
setup_sparc64_timer(void)
762 struct clock_event_device
*sevt
;
763 unsigned long pstate
;
765 /* Guarantee that the following sequences execute
768 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
769 "wrpr %0, %1, %%pstate"
773 tick_ops
->init_tick();
775 /* Restore PSTATE_IE. */
776 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
780 sevt
= &__get_cpu_var(sparc64_events
);
782 memcpy(sevt
, &sparc64_clockevent
, sizeof(*sevt
));
783 sevt
->cpumask
= cpumask_of_cpu(smp_processor_id());
785 clockevents_register_device(sevt
);
788 #define SPARC64_NSEC_PER_CYC_SHIFT 10UL
790 static struct clocksource clocksource_tick
= {
792 .mask
= CLOCKSOURCE_MASK(64),
794 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
797 static void __init
setup_clockevent_multiplier(unsigned long hz
)
799 unsigned long mult
, shift
= 32;
802 mult
= div_sc(hz
, NSEC_PER_SEC
, shift
);
803 if (mult
&& (mult
>> 32UL) == 0UL)
809 sparc64_clockevent
.shift
= shift
;
810 sparc64_clockevent
.mult
= mult
;
813 static unsigned long tb_ticks_per_usec __read_mostly
;
815 void __delay(unsigned long loops
)
817 unsigned long bclock
, now
;
819 bclock
= tick_ops
->get_tick();
821 now
= tick_ops
->get_tick();
822 } while ((now
-bclock
) < loops
);
824 EXPORT_SYMBOL(__delay
);
826 void udelay(unsigned long usecs
)
828 __delay(tb_ticks_per_usec
* usecs
);
830 EXPORT_SYMBOL(udelay
);
832 void __init
time_init(void)
834 unsigned long clock
= sparc64_init_timers();
836 tb_ticks_per_usec
= clock
/ USEC_PER_SEC
;
838 timer_ticks_per_nsec_quotient
=
839 clocksource_hz2mult(clock
, SPARC64_NSEC_PER_CYC_SHIFT
);
841 clocksource_tick
.name
= tick_ops
->name
;
842 clocksource_tick
.mult
=
843 clocksource_hz2mult(clock
,
844 clocksource_tick
.shift
);
845 clocksource_tick
.read
= tick_ops
->get_tick
;
847 printk("clocksource: mult[%x] shift[%d]\n",
848 clocksource_tick
.mult
, clocksource_tick
.shift
);
850 clocksource_register(&clocksource_tick
);
852 sparc64_clockevent
.name
= tick_ops
->name
;
854 setup_clockevent_multiplier(clock
);
856 sparc64_clockevent
.max_delta_ns
=
857 clockevent_delta2ns(0x7fffffffffffffffUL
, &sparc64_clockevent
);
858 sparc64_clockevent
.min_delta_ns
=
859 clockevent_delta2ns(0xF, &sparc64_clockevent
);
861 printk("clockevent: mult[%lx] shift[%d]\n",
862 sparc64_clockevent
.mult
, sparc64_clockevent
.shift
);
864 setup_sparc64_timer();
867 unsigned long long sched_clock(void)
869 unsigned long ticks
= tick_ops
->get_tick();
871 return (ticks
* timer_ticks_per_nsec_quotient
)
872 >> SPARC64_NSEC_PER_CYC_SHIFT
;
875 int __devinit
read_current_timer(unsigned long *timer_val
)
877 *timer_val
= tick_ops
->get_tick();