projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[SPARC64]: Kill pgtable quicklists and use SLAB.
[deliverable/linux.git] / arch / sparc64 / kernel / time.c
1 /* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $
2 * time.c: UltraSparc timer and TOD clock support.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 *
7 * Based largely on code which is:
8 *
9 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
10 */
11
12 #include <linux/config.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/time.h>
22 #include <linux/timex.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/delay.h>
27 #include <linux/profile.h>
28 #include <linux/bcd.h>
29 #include <linux/jiffies.h>
30 #include <linux/cpufreq.h>
31 #include <linux/percpu.h>
32 #include <linux/profile.h>
33
34 #include <asm/oplib.h>
35 #include <asm/mostek.h>
36 #include <asm/timer.h>
37 #include <asm/irq.h>
38 #include <asm/io.h>
39 #include <asm/sbus.h>
40 #include <asm/fhc.h>
41 #include <asm/pbm.h>
42 #include <asm/ebus.h>
43 #include <asm/isa.h>
44 #include <asm/starfire.h>
45 #include <asm/smp.h>
46 #include <asm/sections.h>
47 #include <asm/cpudata.h>
48
49 DEFINE_SPINLOCK(mostek_lock);
50 DEFINE_SPINLOCK(rtc_lock);
51 void __iomem *mstk48t02_regs = NULL;
52 #ifdef CONFIG_PCI
53 unsigned long ds1287_regs = 0UL;
54 #endif
55
56 extern unsigned long wall_jiffies;
57
58 static void __iomem *mstk48t08_regs;
59 static void __iomem *mstk48t59_regs;
60
61 static int set_rtc_mmss(unsigned long);
62
63 #define TICK_PRIV_BIT (1UL << 63)
64
65 #ifdef CONFIG_SMP
66 unsigned long profile_pc(struct pt_regs *regs)
67 {
68 unsigned long pc = instruction_pointer(regs);
69
70 if (in_lock_functions(pc))
71 return regs->u_regs[UREG_RETPC];
72 return pc;
73 }
74 EXPORT_SYMBOL(profile_pc);
75 #endif
76
77 static void tick_disable_protection(void)
78 {
79 /* Set things up so user can access tick register for profiling
80 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
81 * read back of %tick after writing it.
82 */
83 __asm__ __volatile__(
84 " ba,pt %%xcc, 1f\n"
85 " nop\n"
86 " .align 64\n"
87 "1: rd %%tick, %%g2\n"
88 " add %%g2, 6, %%g2\n"
89 " andn %%g2, %0, %%g2\n"
90 " wrpr %%g2, 0, %%tick\n"
91 " rdpr %%tick, %%g0"
92 : /* no outputs */
93 : "r" (TICK_PRIV_BIT)
94 : "g2");
95 }
96
97 static void tick_init_tick(unsigned long offset)
98 {
99 tick_disable_protection();
100
101 __asm__ __volatile__(
102 " rd %%tick, %%g1\n"
103 " andn %%g1, %1, %%g1\n"
104 " ba,pt %%xcc, 1f\n"
105 " add %%g1, %0, %%g1\n"
106 " .align 64\n"
107 "1: wr %%g1, 0x0, %%tick_cmpr\n"
108 " rd %%tick_cmpr, %%g0"
109 : /* no outputs */
110 : "r" (offset), "r" (TICK_PRIV_BIT)
111 : "g1");
112 }
113
114 static unsigned long tick_get_tick(void)
115 {
116 unsigned long ret;
117
118 __asm__ __volatile__("rd %%tick, %0\n\t"
119 "mov %0, %0"
120 : "=r" (ret));
121
122 return ret & ~TICK_PRIV_BIT;
123 }
124
125 static unsigned long tick_get_compare(void)
126 {
127 unsigned long ret;
128
129 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
130 "mov %0, %0"
131 : "=r" (ret));
132
133 return ret;
134 }
135
136 static unsigned long tick_add_compare(unsigned long adj)
137 {
138 unsigned long new_compare;
139
140 /* Workaround for Spitfire Errata (#54 I think??), I discovered
141 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
142 * number 103640.
143 *
144 * On Blackbird writes to %tick_cmpr can fail, the
145 * workaround seems to be to execute the wr instruction
146 * at the start of an I-cache line, and perform a dummy
147 * read back from %tick_cmpr right after writing to it. -DaveM
148 */
149 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
150 "ba,pt %%xcc, 1f\n\t"
151 " add %0, %1, %0\n\t"
152 ".align 64\n"
153 "1:\n\t"
154 "wr %0, 0, %%tick_cmpr\n\t"
155 "rd %%tick_cmpr, %%g0"
156 : "=&r" (new_compare)
157 : "r" (adj));
158
159 return new_compare;
160 }
161
162 static unsigned long tick_add_tick(unsigned long adj, unsigned long offset)
163 {
164 unsigned long new_tick, tmp;
165
166 /* Also need to handle Blackbird bug here too. */
167 __asm__ __volatile__("rd %%tick, %0\n\t"
168 "add %0, %2, %0\n\t"
169 "wrpr %0, 0, %%tick\n\t"
170 "andn %0, %4, %1\n\t"
171 "ba,pt %%xcc, 1f\n\t"
172 " add %1, %3, %1\n\t"
173 ".align 64\n"
174 "1:\n\t"
175 "wr %1, 0, %%tick_cmpr\n\t"
176 "rd %%tick_cmpr, %%g0"
177 : "=&r" (new_tick), "=&r" (tmp)
178 : "r" (adj), "r" (offset), "r" (TICK_PRIV_BIT));
179
180 return new_tick;
181 }
182
183 static struct sparc64_tick_ops tick_operations __read_mostly = {
184 .init_tick = tick_init_tick,
185 .get_tick = tick_get_tick,
186 .get_compare = tick_get_compare,
187 .add_tick = tick_add_tick,
188 .add_compare = tick_add_compare,
189 .softint_mask = 1UL << 0,
190 };
191
192 struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations;
193
194 static void stick_init_tick(unsigned long offset)
195 {
196 tick_disable_protection();
197
198 /* Let the user get at STICK too. */
199 __asm__ __volatile__(
200 " rd %%asr24, %%g2\n"
201 " andn %%g2, %0, %%g2\n"
202 " wr %%g2, 0, %%asr24"
203 : /* no outputs */
204 : "r" (TICK_PRIV_BIT)
205 : "g1", "g2");
206
207 __asm__ __volatile__(
208 " rd %%asr24, %%g1\n"
209 " andn %%g1, %1, %%g1\n"
210 " add %%g1, %0, %%g1\n"
211 " wr %%g1, 0x0, %%asr25"
212 : /* no outputs */
213 : "r" (offset), "r" (TICK_PRIV_BIT)
214 : "g1");
215 }
216
217 static unsigned long stick_get_tick(void)
218 {
219 unsigned long ret;
220
221 __asm__ __volatile__("rd %%asr24, %0"
222 : "=r" (ret));
223
224 return ret & ~TICK_PRIV_BIT;
225 }
226
227 static unsigned long stick_get_compare(void)
228 {
229 unsigned long ret;
230
231 __asm__ __volatile__("rd %%asr25, %0"
232 : "=r" (ret));
233
234 return ret;
235 }
236
237 static unsigned long stick_add_tick(unsigned long adj, unsigned long offset)
238 {
239 unsigned long new_tick, tmp;
240
241 __asm__ __volatile__("rd %%asr24, %0\n\t"
242 "add %0, %2, %0\n\t"
243 "wr %0, 0, %%asr24\n\t"
244 "andn %0, %4, %1\n\t"
245 "add %1, %3, %1\n\t"
246 "wr %1, 0, %%asr25"
247 : "=&r" (new_tick), "=&r" (tmp)
248 : "r" (adj), "r" (offset), "r" (TICK_PRIV_BIT));
249
250 return new_tick;
251 }
252
253 static unsigned long stick_add_compare(unsigned long adj)
254 {
255 unsigned long new_compare;
256
257 __asm__ __volatile__("rd %%asr25, %0\n\t"
258 "add %0, %1, %0\n\t"
259 "wr %0, 0, %%asr25"
260 : "=&r" (new_compare)
261 : "r" (adj));
262
263 return new_compare;
264 }
265
266 static struct sparc64_tick_ops stick_operations __read_mostly = {
267 .init_tick = stick_init_tick,
268 .get_tick = stick_get_tick,
269 .get_compare = stick_get_compare,
270 .add_tick = stick_add_tick,
271 .add_compare = stick_add_compare,
272 .softint_mask = 1UL << 16,
273 };
274
275 /* On Hummingbird the STICK/STICK_CMPR register is implemented
276 * in I/O space. There are two 64-bit registers each, the
277 * first holds the low 32-bits of the value and the second holds
278 * the high 32-bits.
279 *
280 * Since STICK is constantly updating, we have to access it carefully.
281 *
282 * The sequence we use to read is:
283 * 1) read high
284 * 2) read low
285 * 3) read high again, if it rolled re-read both low and high again.
286 *
287 * Writing STICK safely is also tricky:
288 * 1) write low to zero
289 * 2) write high
290 * 3) write low
291 */
292 #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
293 #define HBIRD_STICK_ADDR 0x1fe0000f070UL
294
295 static unsigned long __hbird_read_stick(void)
296 {
297 unsigned long ret, tmp1, tmp2, tmp3;
298 unsigned long addr = HBIRD_STICK_ADDR+8;
299
300 __asm__ __volatile__("ldxa [%1] %5, %2\n"
301 "1:\n\t"
302 "sub %1, 0x8, %1\n\t"
303 "ldxa [%1] %5, %3\n\t"
304 "add %1, 0x8, %1\n\t"
305 "ldxa [%1] %5, %4\n\t"
306 "cmp %4, %2\n\t"
307 "bne,a,pn %%xcc, 1b\n\t"
308 " mov %4, %2\n\t"
309 "sllx %4, 32, %4\n\t"
310 "or %3, %4, %0\n\t"
311 : "=&r" (ret), "=&r" (addr),
312 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
313 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr));
314
315 return ret;
316 }
317
318 static unsigned long __hbird_read_compare(void)
319 {
320 unsigned long low, high;
321 unsigned long addr = HBIRD_STICKCMP_ADDR;
322
323 __asm__ __volatile__("ldxa [%2] %3, %0\n\t"
324 "add %2, 0x8, %2\n\t"
325 "ldxa [%2] %3, %1"
326 : "=&r" (low), "=&r" (high), "=&r" (addr)
327 : "i" (ASI_PHYS_BYPASS_EC_E), "2" (addr));
328
329 return (high << 32UL) | low;
330 }
331
332 static void __hbird_write_stick(unsigned long val)
333 {
334 unsigned long low = (val & 0xffffffffUL);
335 unsigned long high = (val >> 32UL);
336 unsigned long addr = HBIRD_STICK_ADDR;
337
338 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t"
339 "add %0, 0x8, %0\n\t"
340 "stxa %3, [%0] %4\n\t"
341 "sub %0, 0x8, %0\n\t"
342 "stxa %2, [%0] %4"
343 : "=&r" (addr)
344 : "0" (addr), "r" (low), "r" (high),
345 "i" (ASI_PHYS_BYPASS_EC_E));
346 }
347
348 static void __hbird_write_compare(unsigned long val)
349 {
350 unsigned long low = (val & 0xffffffffUL);
351 unsigned long high = (val >> 32UL);
352 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL;
353
354 __asm__ __volatile__("stxa %3, [%0] %4\n\t"
355 "sub %0, 0x8, %0\n\t"
356 "stxa %2, [%0] %4"
357 : "=&r" (addr)
358 : "0" (addr), "r" (low), "r" (high),
359 "i" (ASI_PHYS_BYPASS_EC_E));
360 }
361
362 static void hbtick_init_tick(unsigned long offset)
363 {
364 unsigned long val;
365
366 tick_disable_protection();
367
368 /* XXX This seems to be necessary to 'jumpstart' Hummingbird
369 * XXX into actually sending STICK interrupts. I think because
370 * XXX of how we store %tick_cmpr in head.S this somehow resets the
371 * XXX {TICK + STICK} interrupt mux. -DaveM
372 */
373 __hbird_write_stick(__hbird_read_stick());
374
375 val = __hbird_read_stick() & ~TICK_PRIV_BIT;
376 __hbird_write_compare(val + offset);
377 }
378
379 static unsigned long hbtick_get_tick(void)
380 {
381 return __hbird_read_stick() & ~TICK_PRIV_BIT;
382 }
383
384 static unsigned long hbtick_get_compare(void)
385 {
386 return __hbird_read_compare();
387 }
388
389 static unsigned long hbtick_add_tick(unsigned long adj, unsigned long offset)
390 {
391 unsigned long val;
392
393 val = __hbird_read_stick() + adj;
394 __hbird_write_stick(val);
395
396 val &= ~TICK_PRIV_BIT;
397 __hbird_write_compare(val + offset);
398
399 return val;
400 }
401
402 static unsigned long hbtick_add_compare(unsigned long adj)
403 {
404 unsigned long val = __hbird_read_compare() + adj;
405
406 val &= ~TICK_PRIV_BIT;
407 __hbird_write_compare(val);
408
409 return val;
410 }
411
412 static struct sparc64_tick_ops hbtick_operations __read_mostly = {
413 .init_tick = hbtick_init_tick,
414 .get_tick = hbtick_get_tick,
415 .get_compare = hbtick_get_compare,
416 .add_tick = hbtick_add_tick,
417 .add_compare = hbtick_add_compare,
418 .softint_mask = 1UL << 0,
419 };
420
421 /* timer_interrupt() needs to keep up the real-time clock,
422 * as well as call the "do_timer()" routine every clocktick
423 *
424 * NOTE: On SUN5 systems the ticker interrupt comes in using 2
425 * interrupts, one at level14 and one with softint bit 0.
426 */
427 unsigned long timer_tick_offset __read_mostly;
428
429 static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
430
431 #define TICK_SIZE (tick_nsec / 1000)
432
433 static inline void timer_check_rtc(void)
434 {
435 /* last time the cmos clock got updated */
436 static long last_rtc_update;
437
438 /* Determine when to update the Mostek clock. */
439 if (ntp_synced() &&
440 xtime.tv_sec > last_rtc_update + 660 &&
441 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
442 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
443 if (set_rtc_mmss(xtime.tv_sec) == 0)
444 last_rtc_update = xtime.tv_sec;
445 else
446 last_rtc_update = xtime.tv_sec - 600;
447 /* do it again in 60 s */
448 }
449 }
450
451 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
452 {
453 unsigned long ticks, compare, pstate;
454
455 write_seqlock(&xtime_lock);
456
457 do {
458 #ifndef CONFIG_SMP
459 profile_tick(CPU_PROFILING, regs);
460 update_process_times(user_mode(regs));
461 #endif
462 do_timer(regs);
463
464 /* Guarantee that the following sequences execute
465 * uninterrupted.
466 */
467 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
468 "wrpr %0, %1, %%pstate"
469 : "=r" (pstate)
470 : "i" (PSTATE_IE));
471
472 compare = tick_ops->add_compare(timer_tick_offset);
473 ticks = tick_ops->get_tick();
474
475 /* Restore PSTATE_IE. */
476 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
477 : /* no outputs */
478 : "r" (pstate));
479 } while (time_after_eq(ticks, compare));
480
481 timer_check_rtc();
482
483 write_sequnlock(&xtime_lock);
484
485 return IRQ_HANDLED;
486 }
487
488 #ifdef CONFIG_SMP
489 void timer_tick_interrupt(struct pt_regs *regs)
490 {
491 write_seqlock(&xtime_lock);
492
493 do_timer(regs);
494
495 timer_check_rtc();
496
497 write_sequnlock(&xtime_lock);
498 }
499 #endif
500
501 /* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
502 static void __init kick_start_clock(void)
503 {
504 void __iomem *regs = mstk48t02_regs;
505 u8 sec, tmp;
506 int i, count;
507
508 prom_printf("CLOCK: Clock was stopped. Kick start ");
509
510 spin_lock_irq(&mostek_lock);
511
512 /* Turn on the kick start bit to start the oscillator. */
513 tmp = mostek_read(regs + MOSTEK_CREG);
514 tmp |= MSTK_CREG_WRITE;
515 mostek_write(regs + MOSTEK_CREG, tmp);
516 tmp = mostek_read(regs + MOSTEK_SEC);
517 tmp &= ~MSTK_STOP;
518 mostek_write(regs + MOSTEK_SEC, tmp);
519 tmp = mostek_read(regs + MOSTEK_HOUR);
520 tmp |= MSTK_KICK_START;
521 mostek_write(regs + MOSTEK_HOUR, tmp);
522 tmp = mostek_read(regs + MOSTEK_CREG);
523 tmp &= ~MSTK_CREG_WRITE;
524 mostek_write(regs + MOSTEK_CREG, tmp);
525
526 spin_unlock_irq(&mostek_lock);
527
528 /* Delay to allow the clock oscillator to start. */
529 sec = MSTK_REG_SEC(regs);
530 for (i = 0; i < 3; i++) {
531 while (sec == MSTK_REG_SEC(regs))
532 for (count = 0; count < 100000; count++)
533 /* nothing */ ;
534 prom_printf(".");
535 sec = MSTK_REG_SEC(regs);
536 }
537 prom_printf("\n");
538
539 spin_lock_irq(&mostek_lock);
540
541 /* Turn off kick start and set a "valid" time and date. */
542 tmp = mostek_read(regs + MOSTEK_CREG);
543 tmp |= MSTK_CREG_WRITE;
544 mostek_write(regs + MOSTEK_CREG, tmp);
545 tmp = mostek_read(regs + MOSTEK_HOUR);
546 tmp &= ~MSTK_KICK_START;
547 mostek_write(regs + MOSTEK_HOUR, tmp);
548 MSTK_SET_REG_SEC(regs,0);
549 MSTK_SET_REG_MIN(regs,0);
550 MSTK_SET_REG_HOUR(regs,0);
551 MSTK_SET_REG_DOW(regs,5);
552 MSTK_SET_REG_DOM(regs,1);
553 MSTK_SET_REG_MONTH(regs,8);
554 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
555 tmp = mostek_read(regs + MOSTEK_CREG);
556 tmp &= ~MSTK_CREG_WRITE;
557 mostek_write(regs + MOSTEK_CREG, tmp);
558
559 spin_unlock_irq(&mostek_lock);
560
561 /* Ensure the kick start bit is off. If it isn't, turn it off. */
562 while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
563 prom_printf("CLOCK: Kick start still on!\n");
564
565 spin_lock_irq(&mostek_lock);
566
567 tmp = mostek_read(regs + MOSTEK_CREG);
568 tmp |= MSTK_CREG_WRITE;
569 mostek_write(regs + MOSTEK_CREG, tmp);
570
571 tmp = mostek_read(regs + MOSTEK_HOUR);
572 tmp &= ~MSTK_KICK_START;
573 mostek_write(regs + MOSTEK_HOUR, tmp);
574
575 tmp = mostek_read(regs + MOSTEK_CREG);
576 tmp &= ~MSTK_CREG_WRITE;
577 mostek_write(regs + MOSTEK_CREG, tmp);
578
579 spin_unlock_irq(&mostek_lock);
580 }
581
582 prom_printf("CLOCK: Kick start procedure successful.\n");
583 }
584
585 /* Return nonzero if the clock chip battery is low. */
586 static int __init has_low_battery(void)
587 {
588 void __iomem *regs = mstk48t02_regs;
589 u8 data1, data2;
590
591 spin_lock_irq(&mostek_lock);
592
593 data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */
594 mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */
595 data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */
596 mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */
597
598 spin_unlock_irq(&mostek_lock);
599
600 return (data1 == data2); /* Was the write blocked? */
601 }
602
603 /* Probe for the real time clock chip. */
604 static void __init set_system_time(void)
605 {
606 unsigned int year, mon, day, hour, min, sec;
607 void __iomem *mregs = mstk48t02_regs;
608 #ifdef CONFIG_PCI
609 unsigned long dregs = ds1287_regs;
610 #else
611 unsigned long dregs = 0UL;
612 #endif
613 u8 tmp;
614
615 if (!mregs && !dregs) {
616 prom_printf("Something wrong, clock regs not mapped yet.\n");
617 prom_halt();
618 }
619
620 if (mregs) {
621 spin_lock_irq(&mostek_lock);
622
623 /* Traditional Mostek chip. */
624 tmp = mostek_read(mregs + MOSTEK_CREG);
625 tmp |= MSTK_CREG_READ;
626 mostek_write(mregs + MOSTEK_CREG, tmp);
627
628 sec = MSTK_REG_SEC(mregs);
629 min = MSTK_REG_MIN(mregs);
630 hour = MSTK_REG_HOUR(mregs);
631 day = MSTK_REG_DOM(mregs);
632 mon = MSTK_REG_MONTH(mregs);
633 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
634 } else {
635 int i;
636
637 /* Dallas 12887 RTC chip. */
638
639 /* Stolen from arch/i386/kernel/time.c, see there for
640 * credits and descriptive comments.
641 */
642 for (i = 0; i < 1000000; i++) {
643 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
644 break;
645 udelay(10);
646 }
647 for (i = 0; i < 1000000; i++) {
648 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
649 break;
650 udelay(10);
651 }
652 do {
653 sec = CMOS_READ(RTC_SECONDS);
654 min = CMOS_READ(RTC_MINUTES);
655 hour = CMOS_READ(RTC_HOURS);
656 day = CMOS_READ(RTC_DAY_OF_MONTH);
657 mon = CMOS_READ(RTC_MONTH);
658 year = CMOS_READ(RTC_YEAR);
659 } while (sec != CMOS_READ(RTC_SECONDS));
660 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
661 BCD_TO_BIN(sec);
662 BCD_TO_BIN(min);
663 BCD_TO_BIN(hour);
664 BCD_TO_BIN(day);
665 BCD_TO_BIN(mon);
666 BCD_TO_BIN(year);
667 }
668 if ((year += 1900) < 1970)
669 year += 100;
670 }
671
672 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
673 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
674 set_normalized_timespec(&wall_to_monotonic,
675 -xtime.tv_sec, -xtime.tv_nsec);
676
677 if (mregs) {
678 tmp = mostek_read(mregs + MOSTEK_CREG);
679 tmp &= ~MSTK_CREG_READ;
680 mostek_write(mregs + MOSTEK_CREG, tmp);
681
682 spin_unlock_irq(&mostek_lock);
683 }
684 }
685
686 void __init clock_probe(void)
687 {
688 struct linux_prom_registers clk_reg[2];
689 char model[128];
690 int node, busnd = -1, err;
691 unsigned long flags;
692 struct linux_central *cbus;
693 #ifdef CONFIG_PCI
694 struct linux_ebus *ebus = NULL;
695 struct sparc_isa_bridge *isa_br = NULL;
696 #endif
697 static int invoked;
698
699 if (invoked)
700 return;
701 invoked = 1;
702
703
704 if (this_is_starfire) {
705 /* davem suggests we keep this within the 4M locked kernel image */
706 static char obp_gettod[256];
707 static u32 unix_tod;
708
709 sprintf(obp_gettod, "h# %08x unix-gettod",
710 (unsigned int) (long) &unix_tod);
711 prom_feval(obp_gettod);
712 xtime.tv_sec = unix_tod;
713 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
714 set_normalized_timespec(&wall_to_monotonic,
715 -xtime.tv_sec, -xtime.tv_nsec);
716 return;
717 }
718
719 local_irq_save(flags);
720
721 cbus = central_bus;
722 if (cbus != NULL)
723 busnd = central_bus->child->prom_node;
724
725 /* Check FHC Central then EBUSs then ISA bridges then SBUSs.
726 * That way we handle the presence of multiple properly.
727 *
728 * As a special case, machines with Central must provide the
729 * timer chip there.
730 */
731 #ifdef CONFIG_PCI
732 if (ebus_chain != NULL) {
733 ebus = ebus_chain;
734 if (busnd == -1)
735 busnd = ebus->prom_node;
736 }
737 if (isa_chain != NULL) {
738 isa_br = isa_chain;
739 if (busnd == -1)
740 busnd = isa_br->prom_node;
741 }
742 #endif
743 if (sbus_root != NULL && busnd == -1)
744 busnd = sbus_root->prom_node;
745
746 if (busnd == -1) {
747 prom_printf("clock_probe: problem, cannot find bus to search.\n");
748 prom_halt();
749 }
750
751 node = prom_getchild(busnd);
752
753 while (1) {
754 if (!node)
755 model[0] = 0;
756 else
757 prom_getstring(node, "model", model, sizeof(model));
758 if (strcmp(model, "mk48t02") &&
759 strcmp(model, "mk48t08") &&
760 strcmp(model, "mk48t59") &&
761 strcmp(model, "m5819") &&
762 strcmp(model, "m5819p") &&
763 strcmp(model, "m5823") &&
764 strcmp(model, "ds1287")) {
765 if (cbus != NULL) {
766 prom_printf("clock_probe: Central bus lacks timer chip.\n");
767 prom_halt();
768 }
769
770 if (node != 0)
771 node = prom_getsibling(node);
772 #ifdef CONFIG_PCI
773 while ((node == 0) && ebus != NULL) {
774 ebus = ebus->next;
775 if (ebus != NULL) {
776 busnd = ebus->prom_node;
777 node = prom_getchild(busnd);
778 }
779 }
780 while ((node == 0) && isa_br != NULL) {
781 isa_br = isa_br->next;
782 if (isa_br != NULL) {
783 busnd = isa_br->prom_node;
784 node = prom_getchild(busnd);
785 }
786 }
787 #endif
788 if (node == 0) {
789 prom_printf("clock_probe: Cannot find timer chip\n");
790 prom_halt();
791 }
792 continue;
793 }
794
795 err = prom_getproperty(node, "reg", (char *)clk_reg,
796 sizeof(clk_reg));
797 if(err == -1) {
798 prom_printf("clock_probe: Cannot get Mostek reg property\n");
799 prom_halt();
800 }
801
802 if (cbus != NULL) {
803 apply_fhc_ranges(central_bus->child, clk_reg, 1);
804 apply_central_ranges(central_bus, clk_reg, 1);
805 }
806 #ifdef CONFIG_PCI
807 else if (ebus != NULL) {
808 struct linux_ebus_device *edev;
809
810 for_each_ebusdev(edev, ebus)
811 if (edev->prom_node == node)
812 break;
813 if (edev == NULL) {
814 if (isa_chain != NULL)
815 goto try_isa_clock;
816 prom_printf("%s: Mostek not probed by EBUS\n",
817 __FUNCTION__);
818 prom_halt();
819 }
820
821 if (!strcmp(model, "ds1287") ||
822 !strcmp(model, "m5819") ||
823 !strcmp(model, "m5819p") ||
824 !strcmp(model, "m5823")) {
825 ds1287_regs = edev->resource[0].start;
826 } else {
827 mstk48t59_regs = (void __iomem *)
828 edev->resource[0].start;
829 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
830 }
831 break;
832 }
833 else if (isa_br != NULL) {
834 struct sparc_isa_device *isadev;
835
836 try_isa_clock:
837 for_each_isadev(isadev, isa_br)
838 if (isadev->prom_node == node)
839 break;
840 if (isadev == NULL) {
841 prom_printf("%s: Mostek not probed by ISA\n");
842 prom_halt();
843 }
844 if (!strcmp(model, "ds1287") ||
845 !strcmp(model, "m5819") ||
846 !strcmp(model, "m5819p") ||
847 !strcmp(model, "m5823")) {
848 ds1287_regs = isadev->resource.start;
849 } else {
850 mstk48t59_regs = (void __iomem *)
851 isadev->resource.start;
852 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
853 }
854 break;
855 }
856 #endif
857 else {
858 if (sbus_root->num_sbus_ranges) {
859 int nranges = sbus_root->num_sbus_ranges;
860 int rngc;
861
862 for (rngc = 0; rngc < nranges; rngc++)
863 if (clk_reg[0].which_io ==
864 sbus_root->sbus_ranges[rngc].ot_child_space)
865 break;
866 if (rngc == nranges) {
867 prom_printf("clock_probe: Cannot find ranges for "
868 "clock regs.\n");
869 prom_halt();
870 }
871 clk_reg[0].which_io =
872 sbus_root->sbus_ranges[rngc].ot_parent_space;
873 clk_reg[0].phys_addr +=
874 sbus_root->sbus_ranges[rngc].ot_parent_base;
875 }
876 }
877
878 if(model[5] == '0' && model[6] == '2') {
879 mstk48t02_regs = (void __iomem *)
880 (((u64)clk_reg[0].phys_addr) |
881 (((u64)clk_reg[0].which_io)<<32UL));
882 } else if(model[5] == '0' && model[6] == '8') {
883 mstk48t08_regs = (void __iomem *)
884 (((u64)clk_reg[0].phys_addr) |
885 (((u64)clk_reg[0].which_io)<<32UL));
886 mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
887 } else {
888 mstk48t59_regs = (void __iomem *)
889 (((u64)clk_reg[0].phys_addr) |
890 (((u64)clk_reg[0].which_io)<<32UL));
891 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
892 }
893 break;
894 }
895
896 if (mstk48t02_regs != NULL) {
897 /* Report a low battery voltage condition. */
898 if (has_low_battery())
899 prom_printf("NVRAM: Low battery voltage!\n");
900
901 /* Kick start the clock if it is completely stopped. */
902 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
903 kick_start_clock();
904 }
905
906 set_system_time();
907
908 local_irq_restore(flags);
909 }
910
911 /* This is gets the master TICK_INT timer going. */
912 static unsigned long sparc64_init_timers(void)
913 {
914 unsigned long clock;
915 int node;
916 #ifdef CONFIG_SMP
917 extern void smp_tick_init(void);
918 #endif
919
920 if (tlb_type == spitfire) {
921 unsigned long ver, manuf, impl;
922
923 __asm__ __volatile__ ("rdpr %%ver, %0"
924 : "=&r" (ver));
925 manuf = ((ver >> 48) & 0xffff);
926 impl = ((ver >> 32) & 0xffff);
927 if (manuf == 0x17 && impl == 0x13) {
928 /* Hummingbird, aka Ultra-IIe */
929 tick_ops = &hbtick_operations;
930 node = prom_root_node;
931 clock = prom_getint(node, "stick-frequency");
932 } else {
933 tick_ops = &tick_operations;
934 cpu_find_by_instance(0, &node, NULL);
935 clock = prom_getint(node, "clock-frequency");
936 }
937 } else {
938 tick_ops = &stick_operations;
939 node = prom_root_node;
940 clock = prom_getint(node, "stick-frequency");
941 }
942 timer_tick_offset = clock / HZ;
943
944 #ifdef CONFIG_SMP
945 smp_tick_init();
946 #endif
947
948 return clock;
949 }
950
951 static void sparc64_start_timers(irqreturn_t (*cfunc)(int, void *, struct pt_regs *))
952 {
953 unsigned long pstate;
954 int err;
955
956 /* Register IRQ handler. */
957 err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, 0,
958 "timer", NULL);
959
960 if (err) {
961 prom_printf("Serious problem, cannot register TICK_INT\n");
962 prom_halt();
963 }
964
965 /* Guarantee that the following sequences execute
966 * uninterrupted.
967 */
968 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
969 "wrpr %0, %1, %%pstate"
970 : "=r" (pstate)
971 : "i" (PSTATE_IE));
972
973 tick_ops->init_tick(timer_tick_offset);
974
975 /* Restore PSTATE_IE. */
976 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
977 : /* no outputs */
978 : "r" (pstate));
979
980 local_irq_enable();
981 }
982
983 struct freq_table {
984 unsigned long udelay_val_ref;
985 unsigned long clock_tick_ref;
986 unsigned int ref_freq;
987 };
988 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0, 0 };
989
990 unsigned long sparc64_get_clock_tick(unsigned int cpu)
991 {
992 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
993
994 if (ft->clock_tick_ref)
995 return ft->clock_tick_ref;
996 return cpu_data(cpu).clock_tick;
997 }
998
999 #ifdef CONFIG_CPU_FREQ
1000
1001 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
1002 void *data)
1003 {
1004 struct cpufreq_freqs *freq = data;
1005 unsigned int cpu = freq->cpu;
1006 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
1007
1008 if (!ft->ref_freq) {
1009 ft->ref_freq = freq->old;
1010 ft->udelay_val_ref = cpu_data(cpu).udelay_val;
1011 ft->clock_tick_ref = cpu_data(cpu).clock_tick;
1012 }
1013 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1014 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
1015 (val == CPUFREQ_RESUMECHANGE)) {
1016 cpu_data(cpu).udelay_val =
1017 cpufreq_scale(ft->udelay_val_ref,
1018 ft->ref_freq,
1019 freq->new);
1020 cpu_data(cpu).clock_tick =
1021 cpufreq_scale(ft->clock_tick_ref,
1022 ft->ref_freq,
1023 freq->new);
1024 }
1025
1026 return 0;
1027 }
1028
1029 static struct notifier_block sparc64_cpufreq_notifier_block = {
1030 .notifier_call = sparc64_cpufreq_notifier
1031 };
1032
1033 #endif /* CONFIG_CPU_FREQ */
1034
1035 static struct time_interpolator sparc64_cpu_interpolator = {
1036 .source = TIME_SOURCE_CPU,
1037 .shift = 16,
1038 .mask = 0xffffffffffffffffLL
1039 };
1040
1041 /* The quotient formula is taken from the IA64 port. */
1042 #define SPARC64_NSEC_PER_CYC_SHIFT 30UL
1043 void __init time_init(void)
1044 {
1045 unsigned long clock = sparc64_init_timers();
1046
1047 sparc64_cpu_interpolator.frequency = clock;
1048 register_time_interpolator(&sparc64_cpu_interpolator);
1049
1050 /* Now that the interpolator is registered, it is
1051 * safe to start the timer ticking.
1052 */
1053 sparc64_start_timers(timer_interrupt);
1054
1055 timer_ticks_per_nsec_quotient =
1056 (((NSEC_PER_SEC << SPARC64_NSEC_PER_CYC_SHIFT) +
1057 (clock / 2)) / clock);
1058
1059 #ifdef CONFIG_CPU_FREQ
1060 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block,
1061 CPUFREQ_TRANSITION_NOTIFIER);
1062 #endif
1063 }
1064
1065 unsigned long long sched_clock(void)
1066 {
1067 unsigned long ticks = tick_ops->get_tick();
1068
1069 return (ticks * timer_ticks_per_nsec_quotient)
1070 >> SPARC64_NSEC_PER_CYC_SHIFT;
1071 }
1072
1073 static int set_rtc_mmss(unsigned long nowtime)
1074 {
1075 int real_seconds, real_minutes, chip_minutes;
1076 void __iomem *mregs = mstk48t02_regs;
1077 #ifdef CONFIG_PCI
1078 unsigned long dregs = ds1287_regs;
1079 #else
1080 unsigned long dregs = 0UL;
1081 #endif
1082 unsigned long flags;
1083 u8 tmp;
1084
1085 /*
1086 * Not having a register set can lead to trouble.
1087 * Also starfire doesn't have a tod clock.
1088 */
1089 if (!mregs && !dregs)
1090 return -1;
1091
1092 if (mregs) {
1093 spin_lock_irqsave(&mostek_lock, flags);
1094
1095 /* Read the current RTC minutes. */
1096 tmp = mostek_read(mregs + MOSTEK_CREG);
1097 tmp |= MSTK_CREG_READ;
1098 mostek_write(mregs + MOSTEK_CREG, tmp);
1099
1100 chip_minutes = MSTK_REG_MIN(mregs);
1101
1102 tmp = mostek_read(mregs + MOSTEK_CREG);
1103 tmp &= ~MSTK_CREG_READ;
1104 mostek_write(mregs + MOSTEK_CREG, tmp);
1105
1106 /*
1107 * since we're only adjusting minutes and seconds,
1108 * don't interfere with hour overflow. This avoids
1109 * messing with unknown time zones but requires your
1110 * RTC not to be off by more than 15 minutes
1111 */
1112 real_seconds = nowtime % 60;
1113 real_minutes = nowtime / 60;
1114 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1115 real_minutes += 30; /* correct for half hour time zone */
1116 real_minutes %= 60;
1117
1118 if (abs(real_minutes - chip_minutes) < 30) {
1119 tmp = mostek_read(mregs + MOSTEK_CREG);
1120 tmp |= MSTK_CREG_WRITE;
1121 mostek_write(mregs + MOSTEK_CREG, tmp);
1122
1123 MSTK_SET_REG_SEC(mregs,real_seconds);
1124 MSTK_SET_REG_MIN(mregs,real_minutes);
1125
1126 tmp = mostek_read(mregs + MOSTEK_CREG);
1127 tmp &= ~MSTK_CREG_WRITE;
1128 mostek_write(mregs + MOSTEK_CREG, tmp);
1129
1130 spin_unlock_irqrestore(&mostek_lock, flags);
1131
1132 return 0;
1133 } else {
1134 spin_unlock_irqrestore(&mostek_lock, flags);
1135
1136 return -1;
1137 }
1138 } else {
1139 int retval = 0;
1140 unsigned char save_control, save_freq_select;
1141
1142 /* Stolen from arch/i386/kernel/time.c, see there for
1143 * credits and descriptive comments.
1144 */
1145 spin_lock_irqsave(&rtc_lock, flags);
1146 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
1147 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1148
1149 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
1150 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1151
1152 chip_minutes = CMOS_READ(RTC_MINUTES);
1153 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
1154 BCD_TO_BIN(chip_minutes);
1155 real_seconds = nowtime % 60;
1156 real_minutes = nowtime / 60;
1157 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1158 real_minutes += 30;
1159 real_minutes %= 60;
1160
1161 if (abs(real_minutes - chip_minutes) < 30) {
1162 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1163 BIN_TO_BCD(real_seconds);
1164 BIN_TO_BCD(real_minutes);
1165 }
1166 CMOS_WRITE(real_seconds,RTC_SECONDS);
1167 CMOS_WRITE(real_minutes,RTC_MINUTES);
1168 } else {
1169 printk(KERN_WARNING
1170 "set_rtc_mmss: can't update from %d to %d\n",
1171 chip_minutes, real_minutes);
1172 retval = -1;
1173 }
1174
1175 CMOS_WRITE(save_control, RTC_CONTROL);
1176 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1177 spin_unlock_irqrestore(&rtc_lock, flags);
1178
1179 return retval;
1180 }
1181 }
Linux kernel - Deliverables
This page took 0.078489 seconds and 5 git commands to generate.