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ARM: OMAP1: Fix compile for board-nokia770
[deliverable/linux.git] / arch / sparc64 / kernel / traps.c
1 /* arch/sparc64/kernel/traps.c
2 *
3 * Copyright (C) 1995,1997 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
5 */
6
7 /*
8 * I like traps on v9, :))))
9 */
10
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/kallsyms.h>
15 #include <linux/signal.h>
16 #include <linux/smp.h>
17 #include <linux/mm.h>
18 #include <linux/init.h>
19 #include <linux/kdebug.h>
20
21 #include <asm/smp.h>
22 #include <asm/delay.h>
23 #include <asm/system.h>
24 #include <asm/ptrace.h>
25 #include <asm/oplib.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/unistd.h>
29 #include <asm/uaccess.h>
30 #include <asm/fpumacro.h>
31 #include <asm/lsu.h>
32 #include <asm/dcu.h>
33 #include <asm/estate.h>
34 #include <asm/chafsr.h>
35 #include <asm/sfafsr.h>
36 #include <asm/psrcompat.h>
37 #include <asm/processor.h>
38 #include <asm/timer.h>
39 #include <asm/head.h>
40 #ifdef CONFIG_KMOD
41 #include <linux/kmod.h>
42 #endif
43 #include <asm/prom.h>
44
45
46 /* When an irrecoverable trap occurs at tl > 0, the trap entry
47 * code logs the trap state registers at every level in the trap
48 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
49 * is as follows:
50 */
51 struct tl1_traplog {
52 struct {
53 unsigned long tstate;
54 unsigned long tpc;
55 unsigned long tnpc;
56 unsigned long tt;
57 } trapstack[4];
58 unsigned long tl;
59 };
60
61 static void dump_tl1_traplog(struct tl1_traplog *p)
62 {
63 int i, limit;
64
65 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
66 "dumping track stack.\n", p->tl);
67
68 limit = (tlb_type == hypervisor) ? 2 : 4;
69 for (i = 0; i < limit; i++) {
70 printk(KERN_EMERG
71 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
72 "TNPC[%016lx] TT[%lx]\n",
73 i + 1,
74 p->trapstack[i].tstate, p->trapstack[i].tpc,
75 p->trapstack[i].tnpc, p->trapstack[i].tt);
76 print_symbol("TRAPLOG: TPC<%s>\n", p->trapstack[i].tpc);
77 }
78 }
79
80 void do_call_debug(struct pt_regs *regs)
81 {
82 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
83 }
84
85 void bad_trap(struct pt_regs *regs, long lvl)
86 {
87 char buffer[32];
88 siginfo_t info;
89
90 if (notify_die(DIE_TRAP, "bad trap", regs,
91 0, lvl, SIGTRAP) == NOTIFY_STOP)
92 return;
93
94 if (lvl < 0x100) {
95 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
96 die_if_kernel(buffer, regs);
97 }
98
99 lvl -= 0x100;
100 if (regs->tstate & TSTATE_PRIV) {
101 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
102 die_if_kernel(buffer, regs);
103 }
104 if (test_thread_flag(TIF_32BIT)) {
105 regs->tpc &= 0xffffffff;
106 regs->tnpc &= 0xffffffff;
107 }
108 info.si_signo = SIGILL;
109 info.si_errno = 0;
110 info.si_code = ILL_ILLTRP;
111 info.si_addr = (void __user *)regs->tpc;
112 info.si_trapno = lvl;
113 force_sig_info(SIGILL, &info, current);
114 }
115
116 void bad_trap_tl1(struct pt_regs *regs, long lvl)
117 {
118 char buffer[32];
119
120 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
121 0, lvl, SIGTRAP) == NOTIFY_STOP)
122 return;
123
124 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
125
126 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
127 die_if_kernel (buffer, regs);
128 }
129
130 #ifdef CONFIG_DEBUG_BUGVERBOSE
131 void do_BUG(const char *file, int line)
132 {
133 bust_spinlocks(1);
134 printk("kernel BUG at %s:%d!\n", file, line);
135 }
136 #endif
137
138 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
139 {
140 siginfo_t info;
141
142 if (notify_die(DIE_TRAP, "instruction access exception", regs,
143 0, 0x8, SIGTRAP) == NOTIFY_STOP)
144 return;
145
146 if (regs->tstate & TSTATE_PRIV) {
147 printk("spitfire_insn_access_exception: SFSR[%016lx] "
148 "SFAR[%016lx], going.\n", sfsr, sfar);
149 die_if_kernel("Iax", regs);
150 }
151 if (test_thread_flag(TIF_32BIT)) {
152 regs->tpc &= 0xffffffff;
153 regs->tnpc &= 0xffffffff;
154 }
155 info.si_signo = SIGSEGV;
156 info.si_errno = 0;
157 info.si_code = SEGV_MAPERR;
158 info.si_addr = (void __user *)regs->tpc;
159 info.si_trapno = 0;
160 force_sig_info(SIGSEGV, &info, current);
161 }
162
163 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
164 {
165 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
166 0, 0x8, SIGTRAP) == NOTIFY_STOP)
167 return;
168
169 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
170 spitfire_insn_access_exception(regs, sfsr, sfar);
171 }
172
173 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
174 {
175 unsigned short type = (type_ctx >> 16);
176 unsigned short ctx = (type_ctx & 0xffff);
177 siginfo_t info;
178
179 if (notify_die(DIE_TRAP, "instruction access exception", regs,
180 0, 0x8, SIGTRAP) == NOTIFY_STOP)
181 return;
182
183 if (regs->tstate & TSTATE_PRIV) {
184 printk("sun4v_insn_access_exception: ADDR[%016lx] "
185 "CTX[%04x] TYPE[%04x], going.\n",
186 addr, ctx, type);
187 die_if_kernel("Iax", regs);
188 }
189
190 if (test_thread_flag(TIF_32BIT)) {
191 regs->tpc &= 0xffffffff;
192 regs->tnpc &= 0xffffffff;
193 }
194 info.si_signo = SIGSEGV;
195 info.si_errno = 0;
196 info.si_code = SEGV_MAPERR;
197 info.si_addr = (void __user *) addr;
198 info.si_trapno = 0;
199 force_sig_info(SIGSEGV, &info, current);
200 }
201
202 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
203 {
204 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
205 0, 0x8, SIGTRAP) == NOTIFY_STOP)
206 return;
207
208 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
209 sun4v_insn_access_exception(regs, addr, type_ctx);
210 }
211
212 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
213 {
214 siginfo_t info;
215
216 if (notify_die(DIE_TRAP, "data access exception", regs,
217 0, 0x30, SIGTRAP) == NOTIFY_STOP)
218 return;
219
220 if (regs->tstate & TSTATE_PRIV) {
221 /* Test if this comes from uaccess places. */
222 const struct exception_table_entry *entry;
223
224 entry = search_exception_tables(regs->tpc);
225 if (entry) {
226 /* Ouch, somebody is trying VM hole tricks on us... */
227 #ifdef DEBUG_EXCEPTIONS
228 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
229 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
230 regs->tpc, entry->fixup);
231 #endif
232 regs->tpc = entry->fixup;
233 regs->tnpc = regs->tpc + 4;
234 return;
235 }
236 /* Shit... */
237 printk("spitfire_data_access_exception: SFSR[%016lx] "
238 "SFAR[%016lx], going.\n", sfsr, sfar);
239 die_if_kernel("Dax", regs);
240 }
241
242 info.si_signo = SIGSEGV;
243 info.si_errno = 0;
244 info.si_code = SEGV_MAPERR;
245 info.si_addr = (void __user *)sfar;
246 info.si_trapno = 0;
247 force_sig_info(SIGSEGV, &info, current);
248 }
249
250 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
251 {
252 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
253 0, 0x30, SIGTRAP) == NOTIFY_STOP)
254 return;
255
256 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
257 spitfire_data_access_exception(regs, sfsr, sfar);
258 }
259
260 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
261 {
262 unsigned short type = (type_ctx >> 16);
263 unsigned short ctx = (type_ctx & 0xffff);
264 siginfo_t info;
265
266 if (notify_die(DIE_TRAP, "data access exception", regs,
267 0, 0x8, SIGTRAP) == NOTIFY_STOP)
268 return;
269
270 if (regs->tstate & TSTATE_PRIV) {
271 printk("sun4v_data_access_exception: ADDR[%016lx] "
272 "CTX[%04x] TYPE[%04x], going.\n",
273 addr, ctx, type);
274 die_if_kernel("Dax", regs);
275 }
276
277 if (test_thread_flag(TIF_32BIT)) {
278 regs->tpc &= 0xffffffff;
279 regs->tnpc &= 0xffffffff;
280 }
281 info.si_signo = SIGSEGV;
282 info.si_errno = 0;
283 info.si_code = SEGV_MAPERR;
284 info.si_addr = (void __user *) addr;
285 info.si_trapno = 0;
286 force_sig_info(SIGSEGV, &info, current);
287 }
288
289 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
290 {
291 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
292 0, 0x8, SIGTRAP) == NOTIFY_STOP)
293 return;
294
295 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
296 sun4v_data_access_exception(regs, addr, type_ctx);
297 }
298
299 #ifdef CONFIG_PCI
300 /* This is really pathetic... */
301 extern volatile int pci_poke_in_progress;
302 extern volatile int pci_poke_cpu;
303 extern volatile int pci_poke_faulted;
304 #endif
305
306 /* When access exceptions happen, we must do this. */
307 static void spitfire_clean_and_reenable_l1_caches(void)
308 {
309 unsigned long va;
310
311 if (tlb_type != spitfire)
312 BUG();
313
314 /* Clean 'em. */
315 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
316 spitfire_put_icache_tag(va, 0x0);
317 spitfire_put_dcache_tag(va, 0x0);
318 }
319
320 /* Re-enable in LSU. */
321 __asm__ __volatile__("flush %%g6\n\t"
322 "membar #Sync\n\t"
323 "stxa %0, [%%g0] %1\n\t"
324 "membar #Sync"
325 : /* no outputs */
326 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
327 LSU_CONTROL_IM | LSU_CONTROL_DM),
328 "i" (ASI_LSU_CONTROL)
329 : "memory");
330 }
331
332 static void spitfire_enable_estate_errors(void)
333 {
334 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
335 "membar #Sync"
336 : /* no outputs */
337 : "r" (ESTATE_ERR_ALL),
338 "i" (ASI_ESTATE_ERROR_EN));
339 }
340
341 static char ecc_syndrome_table[] = {
342 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
343 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
344 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
345 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
346 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
347 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
348 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
349 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
350 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
351 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
352 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
353 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
354 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
355 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
356 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
357 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
358 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
359 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
360 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
361 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
362 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
363 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
364 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
365 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
366 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
367 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
368 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
369 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
370 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
371 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
372 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
373 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
374 };
375
376 static char *syndrome_unknown = "<Unknown>";
377
378 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
379 {
380 unsigned short scode;
381 char memmod_str[64], *p;
382
383 if (udbl & bit) {
384 scode = ecc_syndrome_table[udbl & 0xff];
385 if (prom_getunumber(scode, afar,
386 memmod_str, sizeof(memmod_str)) == -1)
387 p = syndrome_unknown;
388 else
389 p = memmod_str;
390 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
391 "Memory Module \"%s\"\n",
392 smp_processor_id(), scode, p);
393 }
394
395 if (udbh & bit) {
396 scode = ecc_syndrome_table[udbh & 0xff];
397 if (prom_getunumber(scode, afar,
398 memmod_str, sizeof(memmod_str)) == -1)
399 p = syndrome_unknown;
400 else
401 p = memmod_str;
402 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
403 "Memory Module \"%s\"\n",
404 smp_processor_id(), scode, p);
405 }
406
407 }
408
409 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
410 {
411
412 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
413 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
414 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
415
416 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
417
418 /* We always log it, even if someone is listening for this
419 * trap.
420 */
421 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
422 0, TRAP_TYPE_CEE, SIGTRAP);
423
424 /* The Correctable ECC Error trap does not disable I/D caches. So
425 * we only have to restore the ESTATE Error Enable register.
426 */
427 spitfire_enable_estate_errors();
428 }
429
430 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
431 {
432 siginfo_t info;
433
434 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
435 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
436 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
437
438 /* XXX add more human friendly logging of the error status
439 * XXX as is implemented for cheetah
440 */
441
442 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
443
444 /* We always log it, even if someone is listening for this
445 * trap.
446 */
447 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
448 0, tt, SIGTRAP);
449
450 if (regs->tstate & TSTATE_PRIV) {
451 if (tl1)
452 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
453 die_if_kernel("UE", regs);
454 }
455
456 /* XXX need more intelligent processing here, such as is implemented
457 * XXX for cheetah errors, in fact if the E-cache still holds the
458 * XXX line with bad parity this will loop
459 */
460
461 spitfire_clean_and_reenable_l1_caches();
462 spitfire_enable_estate_errors();
463
464 if (test_thread_flag(TIF_32BIT)) {
465 regs->tpc &= 0xffffffff;
466 regs->tnpc &= 0xffffffff;
467 }
468 info.si_signo = SIGBUS;
469 info.si_errno = 0;
470 info.si_code = BUS_OBJERR;
471 info.si_addr = (void *)0;
472 info.si_trapno = 0;
473 force_sig_info(SIGBUS, &info, current);
474 }
475
476 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
477 {
478 unsigned long afsr, tt, udbh, udbl;
479 int tl1;
480
481 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
482 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
483 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
484 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
485 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
486
487 #ifdef CONFIG_PCI
488 if (tt == TRAP_TYPE_DAE &&
489 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
490 spitfire_clean_and_reenable_l1_caches();
491 spitfire_enable_estate_errors();
492
493 pci_poke_faulted = 1;
494 regs->tnpc = regs->tpc + 4;
495 return;
496 }
497 #endif
498
499 if (afsr & SFAFSR_UE)
500 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
501
502 if (tt == TRAP_TYPE_CEE) {
503 /* Handle the case where we took a CEE trap, but ACK'd
504 * only the UE state in the UDB error registers.
505 */
506 if (afsr & SFAFSR_UE) {
507 if (udbh & UDBE_CE) {
508 __asm__ __volatile__(
509 "stxa %0, [%1] %2\n\t"
510 "membar #Sync"
511 : /* no outputs */
512 : "r" (udbh & UDBE_CE),
513 "r" (0x0), "i" (ASI_UDB_ERROR_W));
514 }
515 if (udbl & UDBE_CE) {
516 __asm__ __volatile__(
517 "stxa %0, [%1] %2\n\t"
518 "membar #Sync"
519 : /* no outputs */
520 : "r" (udbl & UDBE_CE),
521 "r" (0x18), "i" (ASI_UDB_ERROR_W));
522 }
523 }
524
525 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
526 }
527 }
528
529 int cheetah_pcache_forced_on;
530
531 void cheetah_enable_pcache(void)
532 {
533 unsigned long dcr;
534
535 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
536 smp_processor_id());
537
538 __asm__ __volatile__("ldxa [%%g0] %1, %0"
539 : "=r" (dcr)
540 : "i" (ASI_DCU_CONTROL_REG));
541 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
542 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
543 "membar #Sync"
544 : /* no outputs */
545 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
546 }
547
548 /* Cheetah error trap handling. */
549 static unsigned long ecache_flush_physbase;
550 static unsigned long ecache_flush_linesize;
551 static unsigned long ecache_flush_size;
552
553 /* WARNING: The error trap handlers in assembly know the precise
554 * layout of the following structure.
555 *
556 * C-level handlers below use this information to log the error
557 * and then determine how to recover (if possible).
558 */
559 struct cheetah_err_info {
560 /*0x00*/u64 afsr;
561 /*0x08*/u64 afar;
562
563 /* D-cache state */
564 /*0x10*/u64 dcache_data[4]; /* The actual data */
565 /*0x30*/u64 dcache_index; /* D-cache index */
566 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
567 /*0x40*/u64 dcache_utag; /* D-cache microtag */
568 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
569
570 /* I-cache state */
571 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
572 /*0x90*/u64 icache_index; /* I-cache index */
573 /*0x98*/u64 icache_tag; /* I-cache phys tag */
574 /*0xa0*/u64 icache_utag; /* I-cache microtag */
575 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
576 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
577 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
578
579 /* E-cache state */
580 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
581 /*0xe0*/u64 ecache_index; /* E-cache index */
582 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
583
584 /*0xf0*/u64 __pad[32 - 30];
585 };
586 #define CHAFSR_INVALID ((u64)-1L)
587
588 /* This table is ordered in priority of errors and matches the
589 * AFAR overwrite policy as well.
590 */
591
592 struct afsr_error_table {
593 unsigned long mask;
594 const char *name;
595 };
596
597 static const char CHAFSR_PERR_msg[] =
598 "System interface protocol error";
599 static const char CHAFSR_IERR_msg[] =
600 "Internal processor error";
601 static const char CHAFSR_ISAP_msg[] =
602 "System request parity error on incoming addresss";
603 static const char CHAFSR_UCU_msg[] =
604 "Uncorrectable E-cache ECC error for ifetch/data";
605 static const char CHAFSR_UCC_msg[] =
606 "SW Correctable E-cache ECC error for ifetch/data";
607 static const char CHAFSR_UE_msg[] =
608 "Uncorrectable system bus data ECC error for read";
609 static const char CHAFSR_EDU_msg[] =
610 "Uncorrectable E-cache ECC error for stmerge/blkld";
611 static const char CHAFSR_EMU_msg[] =
612 "Uncorrectable system bus MTAG error";
613 static const char CHAFSR_WDU_msg[] =
614 "Uncorrectable E-cache ECC error for writeback";
615 static const char CHAFSR_CPU_msg[] =
616 "Uncorrectable ECC error for copyout";
617 static const char CHAFSR_CE_msg[] =
618 "HW corrected system bus data ECC error for read";
619 static const char CHAFSR_EDC_msg[] =
620 "HW corrected E-cache ECC error for stmerge/blkld";
621 static const char CHAFSR_EMC_msg[] =
622 "HW corrected system bus MTAG ECC error";
623 static const char CHAFSR_WDC_msg[] =
624 "HW corrected E-cache ECC error for writeback";
625 static const char CHAFSR_CPC_msg[] =
626 "HW corrected ECC error for copyout";
627 static const char CHAFSR_TO_msg[] =
628 "Unmapped error from system bus";
629 static const char CHAFSR_BERR_msg[] =
630 "Bus error response from system bus";
631 static const char CHAFSR_IVC_msg[] =
632 "HW corrected system bus data ECC error for ivec read";
633 static const char CHAFSR_IVU_msg[] =
634 "Uncorrectable system bus data ECC error for ivec read";
635 static struct afsr_error_table __cheetah_error_table[] = {
636 { CHAFSR_PERR, CHAFSR_PERR_msg },
637 { CHAFSR_IERR, CHAFSR_IERR_msg },
638 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
639 { CHAFSR_UCU, CHAFSR_UCU_msg },
640 { CHAFSR_UCC, CHAFSR_UCC_msg },
641 { CHAFSR_UE, CHAFSR_UE_msg },
642 { CHAFSR_EDU, CHAFSR_EDU_msg },
643 { CHAFSR_EMU, CHAFSR_EMU_msg },
644 { CHAFSR_WDU, CHAFSR_WDU_msg },
645 { CHAFSR_CPU, CHAFSR_CPU_msg },
646 { CHAFSR_CE, CHAFSR_CE_msg },
647 { CHAFSR_EDC, CHAFSR_EDC_msg },
648 { CHAFSR_EMC, CHAFSR_EMC_msg },
649 { CHAFSR_WDC, CHAFSR_WDC_msg },
650 { CHAFSR_CPC, CHAFSR_CPC_msg },
651 { CHAFSR_TO, CHAFSR_TO_msg },
652 { CHAFSR_BERR, CHAFSR_BERR_msg },
653 /* These two do not update the AFAR. */
654 { CHAFSR_IVC, CHAFSR_IVC_msg },
655 { CHAFSR_IVU, CHAFSR_IVU_msg },
656 { 0, NULL },
657 };
658 static const char CHPAFSR_DTO_msg[] =
659 "System bus unmapped error for prefetch/storequeue-read";
660 static const char CHPAFSR_DBERR_msg[] =
661 "System bus error for prefetch/storequeue-read";
662 static const char CHPAFSR_THCE_msg[] =
663 "Hardware corrected E-cache Tag ECC error";
664 static const char CHPAFSR_TSCE_msg[] =
665 "SW handled correctable E-cache Tag ECC error";
666 static const char CHPAFSR_TUE_msg[] =
667 "Uncorrectable E-cache Tag ECC error";
668 static const char CHPAFSR_DUE_msg[] =
669 "System bus uncorrectable data ECC error due to prefetch/store-fill";
670 static struct afsr_error_table __cheetah_plus_error_table[] = {
671 { CHAFSR_PERR, CHAFSR_PERR_msg },
672 { CHAFSR_IERR, CHAFSR_IERR_msg },
673 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
674 { CHAFSR_UCU, CHAFSR_UCU_msg },
675 { CHAFSR_UCC, CHAFSR_UCC_msg },
676 { CHAFSR_UE, CHAFSR_UE_msg },
677 { CHAFSR_EDU, CHAFSR_EDU_msg },
678 { CHAFSR_EMU, CHAFSR_EMU_msg },
679 { CHAFSR_WDU, CHAFSR_WDU_msg },
680 { CHAFSR_CPU, CHAFSR_CPU_msg },
681 { CHAFSR_CE, CHAFSR_CE_msg },
682 { CHAFSR_EDC, CHAFSR_EDC_msg },
683 { CHAFSR_EMC, CHAFSR_EMC_msg },
684 { CHAFSR_WDC, CHAFSR_WDC_msg },
685 { CHAFSR_CPC, CHAFSR_CPC_msg },
686 { CHAFSR_TO, CHAFSR_TO_msg },
687 { CHAFSR_BERR, CHAFSR_BERR_msg },
688 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
689 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
690 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
691 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
692 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
693 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
694 /* These two do not update the AFAR. */
695 { CHAFSR_IVC, CHAFSR_IVC_msg },
696 { CHAFSR_IVU, CHAFSR_IVU_msg },
697 { 0, NULL },
698 };
699 static const char JPAFSR_JETO_msg[] =
700 "System interface protocol error, hw timeout caused";
701 static const char JPAFSR_SCE_msg[] =
702 "Parity error on system snoop results";
703 static const char JPAFSR_JEIC_msg[] =
704 "System interface protocol error, illegal command detected";
705 static const char JPAFSR_JEIT_msg[] =
706 "System interface protocol error, illegal ADTYPE detected";
707 static const char JPAFSR_OM_msg[] =
708 "Out of range memory error has occurred";
709 static const char JPAFSR_ETP_msg[] =
710 "Parity error on L2 cache tag SRAM";
711 static const char JPAFSR_UMS_msg[] =
712 "Error due to unsupported store";
713 static const char JPAFSR_RUE_msg[] =
714 "Uncorrectable ECC error from remote cache/memory";
715 static const char JPAFSR_RCE_msg[] =
716 "Correctable ECC error from remote cache/memory";
717 static const char JPAFSR_BP_msg[] =
718 "JBUS parity error on returned read data";
719 static const char JPAFSR_WBP_msg[] =
720 "JBUS parity error on data for writeback or block store";
721 static const char JPAFSR_FRC_msg[] =
722 "Foreign read to DRAM incurring correctable ECC error";
723 static const char JPAFSR_FRU_msg[] =
724 "Foreign read to DRAM incurring uncorrectable ECC error";
725 static struct afsr_error_table __jalapeno_error_table[] = {
726 { JPAFSR_JETO, JPAFSR_JETO_msg },
727 { JPAFSR_SCE, JPAFSR_SCE_msg },
728 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
729 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
730 { CHAFSR_PERR, CHAFSR_PERR_msg },
731 { CHAFSR_IERR, CHAFSR_IERR_msg },
732 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
733 { CHAFSR_UCU, CHAFSR_UCU_msg },
734 { CHAFSR_UCC, CHAFSR_UCC_msg },
735 { CHAFSR_UE, CHAFSR_UE_msg },
736 { CHAFSR_EDU, CHAFSR_EDU_msg },
737 { JPAFSR_OM, JPAFSR_OM_msg },
738 { CHAFSR_WDU, CHAFSR_WDU_msg },
739 { CHAFSR_CPU, CHAFSR_CPU_msg },
740 { CHAFSR_CE, CHAFSR_CE_msg },
741 { CHAFSR_EDC, CHAFSR_EDC_msg },
742 { JPAFSR_ETP, JPAFSR_ETP_msg },
743 { CHAFSR_WDC, CHAFSR_WDC_msg },
744 { CHAFSR_CPC, CHAFSR_CPC_msg },
745 { CHAFSR_TO, CHAFSR_TO_msg },
746 { CHAFSR_BERR, CHAFSR_BERR_msg },
747 { JPAFSR_UMS, JPAFSR_UMS_msg },
748 { JPAFSR_RUE, JPAFSR_RUE_msg },
749 { JPAFSR_RCE, JPAFSR_RCE_msg },
750 { JPAFSR_BP, JPAFSR_BP_msg },
751 { JPAFSR_WBP, JPAFSR_WBP_msg },
752 { JPAFSR_FRC, JPAFSR_FRC_msg },
753 { JPAFSR_FRU, JPAFSR_FRU_msg },
754 /* These two do not update the AFAR. */
755 { CHAFSR_IVU, CHAFSR_IVU_msg },
756 { 0, NULL },
757 };
758 static struct afsr_error_table *cheetah_error_table;
759 static unsigned long cheetah_afsr_errors;
760
761 /* This is allocated at boot time based upon the largest hardware
762 * cpu ID in the system. We allocate two entries per cpu, one for
763 * TL==0 logging and one for TL >= 1 logging.
764 */
765 struct cheetah_err_info *cheetah_error_log;
766
767 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
768 {
769 struct cheetah_err_info *p;
770 int cpu = smp_processor_id();
771
772 if (!cheetah_error_log)
773 return NULL;
774
775 p = cheetah_error_log + (cpu * 2);
776 if ((afsr & CHAFSR_TL1) != 0UL)
777 p++;
778
779 return p;
780 }
781
782 extern unsigned int tl0_icpe[], tl1_icpe[];
783 extern unsigned int tl0_dcpe[], tl1_dcpe[];
784 extern unsigned int tl0_fecc[], tl1_fecc[];
785 extern unsigned int tl0_cee[], tl1_cee[];
786 extern unsigned int tl0_iae[], tl1_iae[];
787 extern unsigned int tl0_dae[], tl1_dae[];
788 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
789 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
790 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
791 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
792 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
793
794 void __init cheetah_ecache_flush_init(void)
795 {
796 unsigned long largest_size, smallest_linesize, order, ver;
797 int i, sz;
798
799 /* Scan all cpu device tree nodes, note two values:
800 * 1) largest E-cache size
801 * 2) smallest E-cache line size
802 */
803 largest_size = 0UL;
804 smallest_linesize = ~0UL;
805
806 for (i = 0; i < NR_CPUS; i++) {
807 unsigned long val;
808
809 val = cpu_data(i).ecache_size;
810 if (!val)
811 continue;
812
813 if (val > largest_size)
814 largest_size = val;
815
816 val = cpu_data(i).ecache_line_size;
817 if (val < smallest_linesize)
818 smallest_linesize = val;
819
820 }
821
822 if (largest_size == 0UL || smallest_linesize == ~0UL) {
823 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
824 "parameters.\n");
825 prom_halt();
826 }
827
828 ecache_flush_size = (2 * largest_size);
829 ecache_flush_linesize = smallest_linesize;
830
831 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
832
833 if (ecache_flush_physbase == ~0UL) {
834 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
835 "contiguous physical memory.\n",
836 ecache_flush_size);
837 prom_halt();
838 }
839
840 /* Now allocate error trap reporting scoreboard. */
841 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
842 for (order = 0; order < MAX_ORDER; order++) {
843 if ((PAGE_SIZE << order) >= sz)
844 break;
845 }
846 cheetah_error_log = (struct cheetah_err_info *)
847 __get_free_pages(GFP_KERNEL, order);
848 if (!cheetah_error_log) {
849 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
850 "error logging scoreboard (%d bytes).\n", sz);
851 prom_halt();
852 }
853 memset(cheetah_error_log, 0, PAGE_SIZE << order);
854
855 /* Mark all AFSRs as invalid so that the trap handler will
856 * log new new information there.
857 */
858 for (i = 0; i < 2 * NR_CPUS; i++)
859 cheetah_error_log[i].afsr = CHAFSR_INVALID;
860
861 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
862 if ((ver >> 32) == __JALAPENO_ID ||
863 (ver >> 32) == __SERRANO_ID) {
864 cheetah_error_table = &__jalapeno_error_table[0];
865 cheetah_afsr_errors = JPAFSR_ERRORS;
866 } else if ((ver >> 32) == 0x003e0015) {
867 cheetah_error_table = &__cheetah_plus_error_table[0];
868 cheetah_afsr_errors = CHPAFSR_ERRORS;
869 } else {
870 cheetah_error_table = &__cheetah_error_table[0];
871 cheetah_afsr_errors = CHAFSR_ERRORS;
872 }
873
874 /* Now patch trap tables. */
875 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
876 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
877 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
878 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
879 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
880 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
881 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
882 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
883 if (tlb_type == cheetah_plus) {
884 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
885 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
886 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
887 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
888 }
889 flushi(PAGE_OFFSET);
890 }
891
892 static void cheetah_flush_ecache(void)
893 {
894 unsigned long flush_base = ecache_flush_physbase;
895 unsigned long flush_linesize = ecache_flush_linesize;
896 unsigned long flush_size = ecache_flush_size;
897
898 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
899 " bne,pt %%xcc, 1b\n\t"
900 " ldxa [%2 + %0] %3, %%g0\n\t"
901 : "=&r" (flush_size)
902 : "0" (flush_size), "r" (flush_base),
903 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
904 }
905
906 static void cheetah_flush_ecache_line(unsigned long physaddr)
907 {
908 unsigned long alias;
909
910 physaddr &= ~(8UL - 1UL);
911 physaddr = (ecache_flush_physbase +
912 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
913 alias = physaddr + (ecache_flush_size >> 1UL);
914 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
915 "ldxa [%1] %2, %%g0\n\t"
916 "membar #Sync"
917 : /* no outputs */
918 : "r" (physaddr), "r" (alias),
919 "i" (ASI_PHYS_USE_EC));
920 }
921
922 /* Unfortunately, the diagnostic access to the I-cache tags we need to
923 * use to clear the thing interferes with I-cache coherency transactions.
924 *
925 * So we must only flush the I-cache when it is disabled.
926 */
927 static void __cheetah_flush_icache(void)
928 {
929 unsigned int icache_size, icache_line_size;
930 unsigned long addr;
931
932 icache_size = local_cpu_data().icache_size;
933 icache_line_size = local_cpu_data().icache_line_size;
934
935 /* Clear the valid bits in all the tags. */
936 for (addr = 0; addr < icache_size; addr += icache_line_size) {
937 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
938 "membar #Sync"
939 : /* no outputs */
940 : "r" (addr | (2 << 3)),
941 "i" (ASI_IC_TAG));
942 }
943 }
944
945 static void cheetah_flush_icache(void)
946 {
947 unsigned long dcu_save;
948
949 /* Save current DCU, disable I-cache. */
950 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
951 "or %0, %2, %%g1\n\t"
952 "stxa %%g1, [%%g0] %1\n\t"
953 "membar #Sync"
954 : "=r" (dcu_save)
955 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
956 : "g1");
957
958 __cheetah_flush_icache();
959
960 /* Restore DCU register */
961 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
962 "membar #Sync"
963 : /* no outputs */
964 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
965 }
966
967 static void cheetah_flush_dcache(void)
968 {
969 unsigned int dcache_size, dcache_line_size;
970 unsigned long addr;
971
972 dcache_size = local_cpu_data().dcache_size;
973 dcache_line_size = local_cpu_data().dcache_line_size;
974
975 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
976 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
977 "membar #Sync"
978 : /* no outputs */
979 : "r" (addr), "i" (ASI_DCACHE_TAG));
980 }
981 }
982
983 /* In order to make the even parity correct we must do two things.
984 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
985 * Next, we clear out all 32-bytes of data for that line. Data of
986 * all-zero + tag parity value of zero == correct parity.
987 */
988 static void cheetah_plus_zap_dcache_parity(void)
989 {
990 unsigned int dcache_size, dcache_line_size;
991 unsigned long addr;
992
993 dcache_size = local_cpu_data().dcache_size;
994 dcache_line_size = local_cpu_data().dcache_line_size;
995
996 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
997 unsigned long tag = (addr >> 14);
998 unsigned long line;
999
1000 __asm__ __volatile__("membar #Sync\n\t"
1001 "stxa %0, [%1] %2\n\t"
1002 "membar #Sync"
1003 : /* no outputs */
1004 : "r" (tag), "r" (addr),
1005 "i" (ASI_DCACHE_UTAG));
1006 for (line = addr; line < addr + dcache_line_size; line += 8)
1007 __asm__ __volatile__("membar #Sync\n\t"
1008 "stxa %%g0, [%0] %1\n\t"
1009 "membar #Sync"
1010 : /* no outputs */
1011 : "r" (line),
1012 "i" (ASI_DCACHE_DATA));
1013 }
1014 }
1015
1016 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1017 * something palatable to the memory controller driver get_unumber
1018 * routine.
1019 */
1020 #define MT0 137
1021 #define MT1 138
1022 #define MT2 139
1023 #define NONE 254
1024 #define MTC0 140
1025 #define MTC1 141
1026 #define MTC2 142
1027 #define MTC3 143
1028 #define C0 128
1029 #define C1 129
1030 #define C2 130
1031 #define C3 131
1032 #define C4 132
1033 #define C5 133
1034 #define C6 134
1035 #define C7 135
1036 #define C8 136
1037 #define M2 144
1038 #define M3 145
1039 #define M4 146
1040 #define M 147
1041 static unsigned char cheetah_ecc_syntab[] = {
1042 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1043 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1044 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1045 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1046 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1047 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1048 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1049 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1050 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1051 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1052 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1053 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1054 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1055 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1056 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1057 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1058 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1059 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1060 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1061 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1062 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1063 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1064 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1065 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1066 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1067 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1068 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1069 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1070 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1071 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1072 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1073 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1074 };
1075 static unsigned char cheetah_mtag_syntab[] = {
1076 NONE, MTC0,
1077 MTC1, NONE,
1078 MTC2, NONE,
1079 NONE, MT0,
1080 MTC3, NONE,
1081 NONE, MT1,
1082 NONE, MT2,
1083 NONE, NONE
1084 };
1085
1086 /* Return the highest priority error conditon mentioned. */
1087 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1088 {
1089 unsigned long tmp = 0;
1090 int i;
1091
1092 for (i = 0; cheetah_error_table[i].mask; i++) {
1093 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1094 return tmp;
1095 }
1096 return tmp;
1097 }
1098
1099 static const char *cheetah_get_string(unsigned long bit)
1100 {
1101 int i;
1102
1103 for (i = 0; cheetah_error_table[i].mask; i++) {
1104 if ((bit & cheetah_error_table[i].mask) != 0UL)
1105 return cheetah_error_table[i].name;
1106 }
1107 return "???";
1108 }
1109
1110 extern int chmc_getunumber(int, unsigned long, char *, int);
1111
1112 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1113 unsigned long afsr, unsigned long afar, int recoverable)
1114 {
1115 unsigned long hipri;
1116 char unum[256];
1117
1118 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1119 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1120 afsr, afar,
1121 (afsr & CHAFSR_TL1) ? 1 : 0);
1122 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1123 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1124 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1125 printk("%s" "ERROR(%d): ",
1126 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1127 print_symbol("TPC<%s>\n", regs->tpc);
1128 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1129 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1130 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1131 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1132 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1133 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1134 hipri = cheetah_get_hipri(afsr);
1135 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 hipri, cheetah_get_string(hipri));
1138
1139 /* Try to get unumber if relevant. */
1140 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1141 CHAFSR_CPC | CHAFSR_CPU | \
1142 CHAFSR_UE | CHAFSR_CE | \
1143 CHAFSR_EDC | CHAFSR_EDU | \
1144 CHAFSR_UCC | CHAFSR_UCU | \
1145 CHAFSR_WDU | CHAFSR_WDC)
1146 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1147 if (afsr & ESYND_ERRORS) {
1148 int syndrome;
1149 int ret;
1150
1151 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1152 syndrome = cheetah_ecc_syntab[syndrome];
1153 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1154 if (ret != -1)
1155 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1156 (recoverable ? KERN_WARNING : KERN_CRIT),
1157 smp_processor_id(), unum);
1158 } else if (afsr & MSYND_ERRORS) {
1159 int syndrome;
1160 int ret;
1161
1162 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1163 syndrome = cheetah_mtag_syntab[syndrome];
1164 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1165 if (ret != -1)
1166 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1167 (recoverable ? KERN_WARNING : KERN_CRIT),
1168 smp_processor_id(), unum);
1169 }
1170
1171 /* Now dump the cache snapshots. */
1172 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1173 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1174 (int) info->dcache_index,
1175 info->dcache_tag,
1176 info->dcache_utag,
1177 info->dcache_stag);
1178 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1179 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1180 info->dcache_data[0],
1181 info->dcache_data[1],
1182 info->dcache_data[2],
1183 info->dcache_data[3]);
1184 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1185 "u[%016lx] l[%016lx]\n",
1186 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1187 (int) info->icache_index,
1188 info->icache_tag,
1189 info->icache_utag,
1190 info->icache_stag,
1191 info->icache_upper,
1192 info->icache_lower);
1193 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1194 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1195 info->icache_data[0],
1196 info->icache_data[1],
1197 info->icache_data[2],
1198 info->icache_data[3]);
1199 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1200 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1201 info->icache_data[4],
1202 info->icache_data[5],
1203 info->icache_data[6],
1204 info->icache_data[7]);
1205 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1206 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1207 (int) info->ecache_index, info->ecache_tag);
1208 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1209 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1210 info->ecache_data[0],
1211 info->ecache_data[1],
1212 info->ecache_data[2],
1213 info->ecache_data[3]);
1214
1215 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1216 while (afsr != 0UL) {
1217 unsigned long bit = cheetah_get_hipri(afsr);
1218
1219 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1220 (recoverable ? KERN_WARNING : KERN_CRIT),
1221 bit, cheetah_get_string(bit));
1222
1223 afsr &= ~bit;
1224 }
1225
1226 if (!recoverable)
1227 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1228 }
1229
1230 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1231 {
1232 unsigned long afsr, afar;
1233 int ret = 0;
1234
1235 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1236 : "=r" (afsr)
1237 : "i" (ASI_AFSR));
1238 if ((afsr & cheetah_afsr_errors) != 0) {
1239 if (logp != NULL) {
1240 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1241 : "=r" (afar)
1242 : "i" (ASI_AFAR));
1243 logp->afsr = afsr;
1244 logp->afar = afar;
1245 }
1246 ret = 1;
1247 }
1248 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1249 "membar #Sync\n\t"
1250 : : "r" (afsr), "i" (ASI_AFSR));
1251
1252 return ret;
1253 }
1254
1255 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1256 {
1257 struct cheetah_err_info local_snapshot, *p;
1258 int recoverable;
1259
1260 /* Flush E-cache */
1261 cheetah_flush_ecache();
1262
1263 p = cheetah_get_error_log(afsr);
1264 if (!p) {
1265 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1266 afsr, afar);
1267 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1268 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1269 prom_halt();
1270 }
1271
1272 /* Grab snapshot of logged error. */
1273 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1274
1275 /* If the current trap snapshot does not match what the
1276 * trap handler passed along into our args, big trouble.
1277 * In such a case, mark the local copy as invalid.
1278 *
1279 * Else, it matches and we mark the afsr in the non-local
1280 * copy as invalid so we may log new error traps there.
1281 */
1282 if (p->afsr != afsr || p->afar != afar)
1283 local_snapshot.afsr = CHAFSR_INVALID;
1284 else
1285 p->afsr = CHAFSR_INVALID;
1286
1287 cheetah_flush_icache();
1288 cheetah_flush_dcache();
1289
1290 /* Re-enable I-cache/D-cache */
1291 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1292 "or %%g1, %1, %%g1\n\t"
1293 "stxa %%g1, [%%g0] %0\n\t"
1294 "membar #Sync"
1295 : /* no outputs */
1296 : "i" (ASI_DCU_CONTROL_REG),
1297 "i" (DCU_DC | DCU_IC)
1298 : "g1");
1299
1300 /* Re-enable error reporting */
1301 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1302 "or %%g1, %1, %%g1\n\t"
1303 "stxa %%g1, [%%g0] %0\n\t"
1304 "membar #Sync"
1305 : /* no outputs */
1306 : "i" (ASI_ESTATE_ERROR_EN),
1307 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1308 : "g1");
1309
1310 /* Decide if we can continue after handling this trap and
1311 * logging the error.
1312 */
1313 recoverable = 1;
1314 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1315 recoverable = 0;
1316
1317 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1318 * error was logged while we had error reporting traps disabled.
1319 */
1320 if (cheetah_recheck_errors(&local_snapshot)) {
1321 unsigned long new_afsr = local_snapshot.afsr;
1322
1323 /* If we got a new asynchronous error, die... */
1324 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1325 CHAFSR_WDU | CHAFSR_CPU |
1326 CHAFSR_IVU | CHAFSR_UE |
1327 CHAFSR_BERR | CHAFSR_TO))
1328 recoverable = 0;
1329 }
1330
1331 /* Log errors. */
1332 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1333
1334 if (!recoverable)
1335 panic("Irrecoverable Fast-ECC error trap.\n");
1336
1337 /* Flush E-cache to kick the error trap handlers out. */
1338 cheetah_flush_ecache();
1339 }
1340
1341 /* Try to fix a correctable error by pushing the line out from
1342 * the E-cache. Recheck error reporting registers to see if the
1343 * problem is intermittent.
1344 */
1345 static int cheetah_fix_ce(unsigned long physaddr)
1346 {
1347 unsigned long orig_estate;
1348 unsigned long alias1, alias2;
1349 int ret;
1350
1351 /* Make sure correctable error traps are disabled. */
1352 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1353 "andn %0, %1, %%g1\n\t"
1354 "stxa %%g1, [%%g0] %2\n\t"
1355 "membar #Sync"
1356 : "=&r" (orig_estate)
1357 : "i" (ESTATE_ERROR_CEEN),
1358 "i" (ASI_ESTATE_ERROR_EN)
1359 : "g1");
1360
1361 /* We calculate alias addresses that will force the
1362 * cache line in question out of the E-cache. Then
1363 * we bring it back in with an atomic instruction so
1364 * that we get it in some modified/exclusive state,
1365 * then we displace it again to try and get proper ECC
1366 * pushed back into the system.
1367 */
1368 physaddr &= ~(8UL - 1UL);
1369 alias1 = (ecache_flush_physbase +
1370 (physaddr & ((ecache_flush_size >> 1) - 1)));
1371 alias2 = alias1 + (ecache_flush_size >> 1);
1372 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1373 "ldxa [%1] %3, %%g0\n\t"
1374 "casxa [%2] %3, %%g0, %%g0\n\t"
1375 "membar #StoreLoad | #StoreStore\n\t"
1376 "ldxa [%0] %3, %%g0\n\t"
1377 "ldxa [%1] %3, %%g0\n\t"
1378 "membar #Sync"
1379 : /* no outputs */
1380 : "r" (alias1), "r" (alias2),
1381 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1382
1383 /* Did that trigger another error? */
1384 if (cheetah_recheck_errors(NULL)) {
1385 /* Try one more time. */
1386 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1387 "membar #Sync"
1388 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1389 if (cheetah_recheck_errors(NULL))
1390 ret = 2;
1391 else
1392 ret = 1;
1393 } else {
1394 /* No new error, intermittent problem. */
1395 ret = 0;
1396 }
1397
1398 /* Restore error enables. */
1399 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1400 "membar #Sync"
1401 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1402
1403 return ret;
1404 }
1405
1406 /* Return non-zero if PADDR is a valid physical memory address. */
1407 static int cheetah_check_main_memory(unsigned long paddr)
1408 {
1409 unsigned long vaddr = PAGE_OFFSET + paddr;
1410
1411 if (vaddr > (unsigned long) high_memory)
1412 return 0;
1413
1414 return kern_addr_valid(vaddr);
1415 }
1416
1417 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1418 {
1419 struct cheetah_err_info local_snapshot, *p;
1420 int recoverable, is_memory;
1421
1422 p = cheetah_get_error_log(afsr);
1423 if (!p) {
1424 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1425 afsr, afar);
1426 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1427 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1428 prom_halt();
1429 }
1430
1431 /* Grab snapshot of logged error. */
1432 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1433
1434 /* If the current trap snapshot does not match what the
1435 * trap handler passed along into our args, big trouble.
1436 * In such a case, mark the local copy as invalid.
1437 *
1438 * Else, it matches and we mark the afsr in the non-local
1439 * copy as invalid so we may log new error traps there.
1440 */
1441 if (p->afsr != afsr || p->afar != afar)
1442 local_snapshot.afsr = CHAFSR_INVALID;
1443 else
1444 p->afsr = CHAFSR_INVALID;
1445
1446 is_memory = cheetah_check_main_memory(afar);
1447
1448 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1449 /* XXX Might want to log the results of this operation
1450 * XXX somewhere... -DaveM
1451 */
1452 cheetah_fix_ce(afar);
1453 }
1454
1455 {
1456 int flush_all, flush_line;
1457
1458 flush_all = flush_line = 0;
1459 if ((afsr & CHAFSR_EDC) != 0UL) {
1460 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1461 flush_line = 1;
1462 else
1463 flush_all = 1;
1464 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1465 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1466 flush_line = 1;
1467 else
1468 flush_all = 1;
1469 }
1470
1471 /* Trap handler only disabled I-cache, flush it. */
1472 cheetah_flush_icache();
1473
1474 /* Re-enable I-cache */
1475 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1476 "or %%g1, %1, %%g1\n\t"
1477 "stxa %%g1, [%%g0] %0\n\t"
1478 "membar #Sync"
1479 : /* no outputs */
1480 : "i" (ASI_DCU_CONTROL_REG),
1481 "i" (DCU_IC)
1482 : "g1");
1483
1484 if (flush_all)
1485 cheetah_flush_ecache();
1486 else if (flush_line)
1487 cheetah_flush_ecache_line(afar);
1488 }
1489
1490 /* Re-enable error reporting */
1491 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1492 "or %%g1, %1, %%g1\n\t"
1493 "stxa %%g1, [%%g0] %0\n\t"
1494 "membar #Sync"
1495 : /* no outputs */
1496 : "i" (ASI_ESTATE_ERROR_EN),
1497 "i" (ESTATE_ERROR_CEEN)
1498 : "g1");
1499
1500 /* Decide if we can continue after handling this trap and
1501 * logging the error.
1502 */
1503 recoverable = 1;
1504 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1505 recoverable = 0;
1506
1507 /* Re-check AFSR/AFAR */
1508 (void) cheetah_recheck_errors(&local_snapshot);
1509
1510 /* Log errors. */
1511 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1512
1513 if (!recoverable)
1514 panic("Irrecoverable Correctable-ECC error trap.\n");
1515 }
1516
1517 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1518 {
1519 struct cheetah_err_info local_snapshot, *p;
1520 int recoverable, is_memory;
1521
1522 #ifdef CONFIG_PCI
1523 /* Check for the special PCI poke sequence. */
1524 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1525 cheetah_flush_icache();
1526 cheetah_flush_dcache();
1527
1528 /* Re-enable I-cache/D-cache */
1529 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1530 "or %%g1, %1, %%g1\n\t"
1531 "stxa %%g1, [%%g0] %0\n\t"
1532 "membar #Sync"
1533 : /* no outputs */
1534 : "i" (ASI_DCU_CONTROL_REG),
1535 "i" (DCU_DC | DCU_IC)
1536 : "g1");
1537
1538 /* Re-enable error reporting */
1539 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1540 "or %%g1, %1, %%g1\n\t"
1541 "stxa %%g1, [%%g0] %0\n\t"
1542 "membar #Sync"
1543 : /* no outputs */
1544 : "i" (ASI_ESTATE_ERROR_EN),
1545 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1546 : "g1");
1547
1548 (void) cheetah_recheck_errors(NULL);
1549
1550 pci_poke_faulted = 1;
1551 regs->tpc += 4;
1552 regs->tnpc = regs->tpc + 4;
1553 return;
1554 }
1555 #endif
1556
1557 p = cheetah_get_error_log(afsr);
1558 if (!p) {
1559 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1560 afsr, afar);
1561 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1562 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1563 prom_halt();
1564 }
1565
1566 /* Grab snapshot of logged error. */
1567 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1568
1569 /* If the current trap snapshot does not match what the
1570 * trap handler passed along into our args, big trouble.
1571 * In such a case, mark the local copy as invalid.
1572 *
1573 * Else, it matches and we mark the afsr in the non-local
1574 * copy as invalid so we may log new error traps there.
1575 */
1576 if (p->afsr != afsr || p->afar != afar)
1577 local_snapshot.afsr = CHAFSR_INVALID;
1578 else
1579 p->afsr = CHAFSR_INVALID;
1580
1581 is_memory = cheetah_check_main_memory(afar);
1582
1583 {
1584 int flush_all, flush_line;
1585
1586 flush_all = flush_line = 0;
1587 if ((afsr & CHAFSR_EDU) != 0UL) {
1588 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1589 flush_line = 1;
1590 else
1591 flush_all = 1;
1592 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1593 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1594 flush_line = 1;
1595 else
1596 flush_all = 1;
1597 }
1598
1599 cheetah_flush_icache();
1600 cheetah_flush_dcache();
1601
1602 /* Re-enable I/D caches */
1603 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1604 "or %%g1, %1, %%g1\n\t"
1605 "stxa %%g1, [%%g0] %0\n\t"
1606 "membar #Sync"
1607 : /* no outputs */
1608 : "i" (ASI_DCU_CONTROL_REG),
1609 "i" (DCU_IC | DCU_DC)
1610 : "g1");
1611
1612 if (flush_all)
1613 cheetah_flush_ecache();
1614 else if (flush_line)
1615 cheetah_flush_ecache_line(afar);
1616 }
1617
1618 /* Re-enable error reporting */
1619 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1620 "or %%g1, %1, %%g1\n\t"
1621 "stxa %%g1, [%%g0] %0\n\t"
1622 "membar #Sync"
1623 : /* no outputs */
1624 : "i" (ASI_ESTATE_ERROR_EN),
1625 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1626 : "g1");
1627
1628 /* Decide if we can continue after handling this trap and
1629 * logging the error.
1630 */
1631 recoverable = 1;
1632 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1633 recoverable = 0;
1634
1635 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1636 * error was logged while we had error reporting traps disabled.
1637 */
1638 if (cheetah_recheck_errors(&local_snapshot)) {
1639 unsigned long new_afsr = local_snapshot.afsr;
1640
1641 /* If we got a new asynchronous error, die... */
1642 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1643 CHAFSR_WDU | CHAFSR_CPU |
1644 CHAFSR_IVU | CHAFSR_UE |
1645 CHAFSR_BERR | CHAFSR_TO))
1646 recoverable = 0;
1647 }
1648
1649 /* Log errors. */
1650 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1651
1652 /* "Recoverable" here means we try to yank the page from ever
1653 * being newly used again. This depends upon a few things:
1654 * 1) Must be main memory, and AFAR must be valid.
1655 * 2) If we trapped from user, OK.
1656 * 3) Else, if we trapped from kernel we must find exception
1657 * table entry (ie. we have to have been accessing user
1658 * space).
1659 *
1660 * If AFAR is not in main memory, or we trapped from kernel
1661 * and cannot find an exception table entry, it is unacceptable
1662 * to try and continue.
1663 */
1664 if (recoverable && is_memory) {
1665 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1666 /* OK, usermode access. */
1667 recoverable = 1;
1668 } else {
1669 const struct exception_table_entry *entry;
1670
1671 entry = search_exception_tables(regs->tpc);
1672 if (entry) {
1673 /* OK, kernel access to userspace. */
1674 recoverable = 1;
1675
1676 } else {
1677 /* BAD, privileged state is corrupted. */
1678 recoverable = 0;
1679 }
1680
1681 if (recoverable) {
1682 if (pfn_valid(afar >> PAGE_SHIFT))
1683 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1684 else
1685 recoverable = 0;
1686
1687 /* Only perform fixup if we still have a
1688 * recoverable condition.
1689 */
1690 if (recoverable) {
1691 regs->tpc = entry->fixup;
1692 regs->tnpc = regs->tpc + 4;
1693 }
1694 }
1695 }
1696 } else {
1697 recoverable = 0;
1698 }
1699
1700 if (!recoverable)
1701 panic("Irrecoverable deferred error trap.\n");
1702 }
1703
1704 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1705 *
1706 * Bit0: 0=dcache,1=icache
1707 * Bit1: 0=recoverable,1=unrecoverable
1708 *
1709 * The hardware has disabled both the I-cache and D-cache in
1710 * the %dcr register.
1711 */
1712 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1713 {
1714 if (type & 0x1)
1715 __cheetah_flush_icache();
1716 else
1717 cheetah_plus_zap_dcache_parity();
1718 cheetah_flush_dcache();
1719
1720 /* Re-enable I-cache/D-cache */
1721 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1722 "or %%g1, %1, %%g1\n\t"
1723 "stxa %%g1, [%%g0] %0\n\t"
1724 "membar #Sync"
1725 : /* no outputs */
1726 : "i" (ASI_DCU_CONTROL_REG),
1727 "i" (DCU_DC | DCU_IC)
1728 : "g1");
1729
1730 if (type & 0x2) {
1731 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1732 smp_processor_id(),
1733 (type & 0x1) ? 'I' : 'D',
1734 regs->tpc);
1735 print_symbol(KERN_EMERG "TPC<%s>\n", regs->tpc);
1736 panic("Irrecoverable Cheetah+ parity error.");
1737 }
1738
1739 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1740 smp_processor_id(),
1741 (type & 0x1) ? 'I' : 'D',
1742 regs->tpc);
1743 print_symbol(KERN_WARNING "TPC<%s>\n", regs->tpc);
1744 }
1745
1746 struct sun4v_error_entry {
1747 u64 err_handle;
1748 u64 err_stick;
1749
1750 u32 err_type;
1751 #define SUN4V_ERR_TYPE_UNDEFINED 0
1752 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1753 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1754 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1755 #define SUN4V_ERR_TYPE_WARNING_RES 4
1756
1757 u32 err_attrs;
1758 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1759 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1760 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1761 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1762 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1763 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1764 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1765 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1766
1767 u64 err_raddr;
1768 u32 err_size;
1769 u16 err_cpu;
1770 u16 err_pad;
1771 };
1772
1773 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1774 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1775
1776 static const char *sun4v_err_type_to_str(u32 type)
1777 {
1778 switch (type) {
1779 case SUN4V_ERR_TYPE_UNDEFINED:
1780 return "undefined";
1781 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1782 return "uncorrected resumable";
1783 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1784 return "precise nonresumable";
1785 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1786 return "deferred nonresumable";
1787 case SUN4V_ERR_TYPE_WARNING_RES:
1788 return "warning resumable";
1789 default:
1790 return "unknown";
1791 };
1792 }
1793
1794 extern void __show_regs(struct pt_regs * regs);
1795
1796 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1797 {
1798 int cnt;
1799
1800 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1801 printk("%s: err_handle[%lx] err_stick[%lx] err_type[%08x:%s]\n",
1802 pfx,
1803 ent->err_handle, ent->err_stick,
1804 ent->err_type,
1805 sun4v_err_type_to_str(ent->err_type));
1806 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1807 pfx,
1808 ent->err_attrs,
1809 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1810 "processor" : ""),
1811 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1812 "memory" : ""),
1813 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1814 "pio" : ""),
1815 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1816 "integer-regs" : ""),
1817 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1818 "fpu-regs" : ""),
1819 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1820 "user" : ""),
1821 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1822 "privileged" : ""),
1823 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1824 "queue-full" : ""));
1825 printk("%s: err_raddr[%016lx] err_size[%u] err_cpu[%u]\n",
1826 pfx,
1827 ent->err_raddr, ent->err_size, ent->err_cpu);
1828
1829 __show_regs(regs);
1830
1831 if ((cnt = atomic_read(ocnt)) != 0) {
1832 atomic_set(ocnt, 0);
1833 wmb();
1834 printk("%s: Queue overflowed %d times.\n",
1835 pfx, cnt);
1836 }
1837 }
1838
1839 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1840 * Log the event and clear the first word of the entry.
1841 */
1842 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1843 {
1844 struct sun4v_error_entry *ent, local_copy;
1845 struct trap_per_cpu *tb;
1846 unsigned long paddr;
1847 int cpu;
1848
1849 cpu = get_cpu();
1850
1851 tb = &trap_block[cpu];
1852 paddr = tb->resum_kernel_buf_pa + offset;
1853 ent = __va(paddr);
1854
1855 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1856
1857 /* We have a local copy now, so release the entry. */
1858 ent->err_handle = 0;
1859 wmb();
1860
1861 put_cpu();
1862
1863 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1864 /* If err_type is 0x4, it's a powerdown request. Do
1865 * not do the usual resumable error log because that
1866 * makes it look like some abnormal error.
1867 */
1868 printk(KERN_INFO "Power down request...\n");
1869 kill_cad_pid(SIGINT, 1);
1870 return;
1871 }
1872
1873 sun4v_log_error(regs, &local_copy, cpu,
1874 KERN_ERR "RESUMABLE ERROR",
1875 &sun4v_resum_oflow_cnt);
1876 }
1877
1878 /* If we try to printk() we'll probably make matters worse, by trying
1879 * to retake locks this cpu already holds or causing more errors. So
1880 * just bump a counter, and we'll report these counter bumps above.
1881 */
1882 void sun4v_resum_overflow(struct pt_regs *regs)
1883 {
1884 atomic_inc(&sun4v_resum_oflow_cnt);
1885 }
1886
1887 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1888 * Log the event, clear the first word of the entry, and die.
1889 */
1890 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1891 {
1892 struct sun4v_error_entry *ent, local_copy;
1893 struct trap_per_cpu *tb;
1894 unsigned long paddr;
1895 int cpu;
1896
1897 cpu = get_cpu();
1898
1899 tb = &trap_block[cpu];
1900 paddr = tb->nonresum_kernel_buf_pa + offset;
1901 ent = __va(paddr);
1902
1903 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1904
1905 /* We have a local copy now, so release the entry. */
1906 ent->err_handle = 0;
1907 wmb();
1908
1909 put_cpu();
1910
1911 #ifdef CONFIG_PCI
1912 /* Check for the special PCI poke sequence. */
1913 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1914 pci_poke_faulted = 1;
1915 regs->tpc += 4;
1916 regs->tnpc = regs->tpc + 4;
1917 return;
1918 }
1919 #endif
1920
1921 sun4v_log_error(regs, &local_copy, cpu,
1922 KERN_EMERG "NON-RESUMABLE ERROR",
1923 &sun4v_nonresum_oflow_cnt);
1924
1925 panic("Non-resumable error.");
1926 }
1927
1928 /* If we try to printk() we'll probably make matters worse, by trying
1929 * to retake locks this cpu already holds or causing more errors. So
1930 * just bump a counter, and we'll report these counter bumps above.
1931 */
1932 void sun4v_nonresum_overflow(struct pt_regs *regs)
1933 {
1934 /* XXX Actually even this can make not that much sense. Perhaps
1935 * XXX we should just pull the plug and panic directly from here?
1936 */
1937 atomic_inc(&sun4v_nonresum_oflow_cnt);
1938 }
1939
1940 unsigned long sun4v_err_itlb_vaddr;
1941 unsigned long sun4v_err_itlb_ctx;
1942 unsigned long sun4v_err_itlb_pte;
1943 unsigned long sun4v_err_itlb_error;
1944
1945 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1946 {
1947 if (tl > 1)
1948 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1949
1950 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1951 regs->tpc, tl);
1952 print_symbol(KERN_EMERG "SUN4V-ITLB: TPC<%s>\n", regs->tpc);
1953 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1954 "pte[%lx] error[%lx]\n",
1955 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1956 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1957
1958 prom_halt();
1959 }
1960
1961 unsigned long sun4v_err_dtlb_vaddr;
1962 unsigned long sun4v_err_dtlb_ctx;
1963 unsigned long sun4v_err_dtlb_pte;
1964 unsigned long sun4v_err_dtlb_error;
1965
1966 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1967 {
1968 if (tl > 1)
1969 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1970
1971 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1972 regs->tpc, tl);
1973 print_symbol(KERN_EMERG "SUN4V-DTLB: TPC<%s>\n", regs->tpc);
1974 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1975 "pte[%lx] error[%lx]\n",
1976 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1977 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1978
1979 prom_halt();
1980 }
1981
1982 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1983 {
1984 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1985 err, op);
1986 }
1987
1988 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
1989 {
1990 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
1991 err, op);
1992 }
1993
1994 void do_fpe_common(struct pt_regs *regs)
1995 {
1996 if (regs->tstate & TSTATE_PRIV) {
1997 regs->tpc = regs->tnpc;
1998 regs->tnpc += 4;
1999 } else {
2000 unsigned long fsr = current_thread_info()->xfsr[0];
2001 siginfo_t info;
2002
2003 if (test_thread_flag(TIF_32BIT)) {
2004 regs->tpc &= 0xffffffff;
2005 regs->tnpc &= 0xffffffff;
2006 }
2007 info.si_signo = SIGFPE;
2008 info.si_errno = 0;
2009 info.si_addr = (void __user *)regs->tpc;
2010 info.si_trapno = 0;
2011 info.si_code = __SI_FAULT;
2012 if ((fsr & 0x1c000) == (1 << 14)) {
2013 if (fsr & 0x10)
2014 info.si_code = FPE_FLTINV;
2015 else if (fsr & 0x08)
2016 info.si_code = FPE_FLTOVF;
2017 else if (fsr & 0x04)
2018 info.si_code = FPE_FLTUND;
2019 else if (fsr & 0x02)
2020 info.si_code = FPE_FLTDIV;
2021 else if (fsr & 0x01)
2022 info.si_code = FPE_FLTRES;
2023 }
2024 force_sig_info(SIGFPE, &info, current);
2025 }
2026 }
2027
2028 void do_fpieee(struct pt_regs *regs)
2029 {
2030 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2031 0, 0x24, SIGFPE) == NOTIFY_STOP)
2032 return;
2033
2034 do_fpe_common(regs);
2035 }
2036
2037 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2038
2039 void do_fpother(struct pt_regs *regs)
2040 {
2041 struct fpustate *f = FPUSTATE;
2042 int ret = 0;
2043
2044 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2045 0, 0x25, SIGFPE) == NOTIFY_STOP)
2046 return;
2047
2048 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2049 case (2 << 14): /* unfinished_FPop */
2050 case (3 << 14): /* unimplemented_FPop */
2051 ret = do_mathemu(regs, f);
2052 break;
2053 }
2054 if (ret)
2055 return;
2056 do_fpe_common(regs);
2057 }
2058
2059 void do_tof(struct pt_regs *regs)
2060 {
2061 siginfo_t info;
2062
2063 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2064 0, 0x26, SIGEMT) == NOTIFY_STOP)
2065 return;
2066
2067 if (regs->tstate & TSTATE_PRIV)
2068 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2069 if (test_thread_flag(TIF_32BIT)) {
2070 regs->tpc &= 0xffffffff;
2071 regs->tnpc &= 0xffffffff;
2072 }
2073 info.si_signo = SIGEMT;
2074 info.si_errno = 0;
2075 info.si_code = EMT_TAGOVF;
2076 info.si_addr = (void __user *)regs->tpc;
2077 info.si_trapno = 0;
2078 force_sig_info(SIGEMT, &info, current);
2079 }
2080
2081 void do_div0(struct pt_regs *regs)
2082 {
2083 siginfo_t info;
2084
2085 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2086 0, 0x28, SIGFPE) == NOTIFY_STOP)
2087 return;
2088
2089 if (regs->tstate & TSTATE_PRIV)
2090 die_if_kernel("TL0: Kernel divide by zero.", regs);
2091 if (test_thread_flag(TIF_32BIT)) {
2092 regs->tpc &= 0xffffffff;
2093 regs->tnpc &= 0xffffffff;
2094 }
2095 info.si_signo = SIGFPE;
2096 info.si_errno = 0;
2097 info.si_code = FPE_INTDIV;
2098 info.si_addr = (void __user *)regs->tpc;
2099 info.si_trapno = 0;
2100 force_sig_info(SIGFPE, &info, current);
2101 }
2102
2103 void instruction_dump (unsigned int *pc)
2104 {
2105 int i;
2106
2107 if ((((unsigned long) pc) & 3))
2108 return;
2109
2110 printk("Instruction DUMP:");
2111 for (i = -3; i < 6; i++)
2112 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2113 printk("\n");
2114 }
2115
2116 static void user_instruction_dump (unsigned int __user *pc)
2117 {
2118 int i;
2119 unsigned int buf[9];
2120
2121 if ((((unsigned long) pc) & 3))
2122 return;
2123
2124 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2125 return;
2126
2127 printk("Instruction DUMP:");
2128 for (i = 0; i < 9; i++)
2129 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2130 printk("\n");
2131 }
2132
2133 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2134 {
2135 unsigned long pc, fp, thread_base, ksp;
2136 struct thread_info *tp;
2137 struct reg_window *rw;
2138 int count = 0;
2139
2140 ksp = (unsigned long) _ksp;
2141 if (!tsk)
2142 tsk = current;
2143 tp = task_thread_info(tsk);
2144 if (ksp == 0UL) {
2145 if (tsk == current)
2146 asm("mov %%fp, %0" : "=r" (ksp));
2147 else
2148 ksp = tp->ksp;
2149 }
2150 if (tp == current_thread_info())
2151 flushw_all();
2152
2153 fp = ksp + STACK_BIAS;
2154 thread_base = (unsigned long) tp;
2155
2156 printk("Call Trace:");
2157 #ifdef CONFIG_KALLSYMS
2158 printk("\n");
2159 #endif
2160 do {
2161 /* Bogus frame pointer? */
2162 if (fp < (thread_base + sizeof(struct thread_info)) ||
2163 fp >= (thread_base + THREAD_SIZE))
2164 break;
2165 rw = (struct reg_window *)fp;
2166 pc = rw->ins[7];
2167 printk(" [%016lx] ", pc);
2168 print_symbol("%s\n", pc);
2169 fp = rw->ins[6] + STACK_BIAS;
2170 } while (++count < 16);
2171 #ifndef CONFIG_KALLSYMS
2172 printk("\n");
2173 #endif
2174 }
2175
2176 void dump_stack(void)
2177 {
2178 show_stack(current, NULL);
2179 }
2180
2181 EXPORT_SYMBOL(dump_stack);
2182
2183 static inline int is_kernel_stack(struct task_struct *task,
2184 struct reg_window *rw)
2185 {
2186 unsigned long rw_addr = (unsigned long) rw;
2187 unsigned long thread_base, thread_end;
2188
2189 if (rw_addr < PAGE_OFFSET) {
2190 if (task != &init_task)
2191 return 0;
2192 }
2193
2194 thread_base = (unsigned long) task_stack_page(task);
2195 thread_end = thread_base + sizeof(union thread_union);
2196 if (rw_addr >= thread_base &&
2197 rw_addr < thread_end &&
2198 !(rw_addr & 0x7UL))
2199 return 1;
2200
2201 return 0;
2202 }
2203
2204 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2205 {
2206 unsigned long fp = rw->ins[6];
2207
2208 if (!fp)
2209 return NULL;
2210
2211 return (struct reg_window *) (fp + STACK_BIAS);
2212 }
2213
2214 void die_if_kernel(char *str, struct pt_regs *regs)
2215 {
2216 static int die_counter;
2217 extern void smp_report_regs(void);
2218 int count = 0;
2219
2220 /* Amuse the user. */
2221 printk(
2222 " \\|/ ____ \\|/\n"
2223 " \"@'/ .. \\`@\"\n"
2224 " /_| \\__/ |_\\\n"
2225 " \\__U_/\n");
2226
2227 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2228 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2229 __asm__ __volatile__("flushw");
2230 __show_regs(regs);
2231 add_taint(TAINT_DIE);
2232 if (regs->tstate & TSTATE_PRIV) {
2233 struct reg_window *rw = (struct reg_window *)
2234 (regs->u_regs[UREG_FP] + STACK_BIAS);
2235
2236 /* Stop the back trace when we hit userland or we
2237 * find some badly aligned kernel stack.
2238 */
2239 while (rw &&
2240 count++ < 30&&
2241 is_kernel_stack(current, rw)) {
2242 printk("Caller[%016lx]", rw->ins[7]);
2243 print_symbol(": %s", rw->ins[7]);
2244 printk("\n");
2245
2246 rw = kernel_stack_up(rw);
2247 }
2248 instruction_dump ((unsigned int *) regs->tpc);
2249 } else {
2250 if (test_thread_flag(TIF_32BIT)) {
2251 regs->tpc &= 0xffffffff;
2252 regs->tnpc &= 0xffffffff;
2253 }
2254 user_instruction_dump ((unsigned int __user *) regs->tpc);
2255 }
2256 #if 0
2257 #ifdef CONFIG_SMP
2258 smp_report_regs();
2259 #endif
2260 #endif
2261 if (regs->tstate & TSTATE_PRIV)
2262 do_exit(SIGKILL);
2263 do_exit(SIGSEGV);
2264 }
2265
2266 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2267 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2268
2269 extern int handle_popc(u32 insn, struct pt_regs *regs);
2270 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2271 extern int vis_emul(struct pt_regs *, unsigned int);
2272
2273 void do_illegal_instruction(struct pt_regs *regs)
2274 {
2275 unsigned long pc = regs->tpc;
2276 unsigned long tstate = regs->tstate;
2277 u32 insn;
2278 siginfo_t info;
2279
2280 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2281 0, 0x10, SIGILL) == NOTIFY_STOP)
2282 return;
2283
2284 if (tstate & TSTATE_PRIV)
2285 die_if_kernel("Kernel illegal instruction", regs);
2286 if (test_thread_flag(TIF_32BIT))
2287 pc = (u32)pc;
2288 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2289 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2290 if (handle_popc(insn, regs))
2291 return;
2292 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2293 if (handle_ldf_stq(insn, regs))
2294 return;
2295 } else if (tlb_type == hypervisor) {
2296 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2297 if (!vis_emul(regs, insn))
2298 return;
2299 } else {
2300 struct fpustate *f = FPUSTATE;
2301
2302 /* XXX maybe verify XFSR bits like
2303 * XXX do_fpother() does?
2304 */
2305 if (do_mathemu(regs, f))
2306 return;
2307 }
2308 }
2309 }
2310 info.si_signo = SIGILL;
2311 info.si_errno = 0;
2312 info.si_code = ILL_ILLOPC;
2313 info.si_addr = (void __user *)pc;
2314 info.si_trapno = 0;
2315 force_sig_info(SIGILL, &info, current);
2316 }
2317
2318 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2319
2320 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2321 {
2322 siginfo_t info;
2323
2324 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2325 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2326 return;
2327
2328 if (regs->tstate & TSTATE_PRIV) {
2329 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2330 return;
2331 }
2332 info.si_signo = SIGBUS;
2333 info.si_errno = 0;
2334 info.si_code = BUS_ADRALN;
2335 info.si_addr = (void __user *)sfar;
2336 info.si_trapno = 0;
2337 force_sig_info(SIGBUS, &info, current);
2338 }
2339
2340 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2341 {
2342 siginfo_t info;
2343
2344 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2345 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2346 return;
2347
2348 if (regs->tstate & TSTATE_PRIV) {
2349 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2350 return;
2351 }
2352 info.si_signo = SIGBUS;
2353 info.si_errno = 0;
2354 info.si_code = BUS_ADRALN;
2355 info.si_addr = (void __user *) addr;
2356 info.si_trapno = 0;
2357 force_sig_info(SIGBUS, &info, current);
2358 }
2359
2360 void do_privop(struct pt_regs *regs)
2361 {
2362 siginfo_t info;
2363
2364 if (notify_die(DIE_TRAP, "privileged operation", regs,
2365 0, 0x11, SIGILL) == NOTIFY_STOP)
2366 return;
2367
2368 if (test_thread_flag(TIF_32BIT)) {
2369 regs->tpc &= 0xffffffff;
2370 regs->tnpc &= 0xffffffff;
2371 }
2372 info.si_signo = SIGILL;
2373 info.si_errno = 0;
2374 info.si_code = ILL_PRVOPC;
2375 info.si_addr = (void __user *)regs->tpc;
2376 info.si_trapno = 0;
2377 force_sig_info(SIGILL, &info, current);
2378 }
2379
2380 void do_privact(struct pt_regs *regs)
2381 {
2382 do_privop(regs);
2383 }
2384
2385 /* Trap level 1 stuff or other traps we should never see... */
2386 void do_cee(struct pt_regs *regs)
2387 {
2388 die_if_kernel("TL0: Cache Error Exception", regs);
2389 }
2390
2391 void do_cee_tl1(struct pt_regs *regs)
2392 {
2393 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2394 die_if_kernel("TL1: Cache Error Exception", regs);
2395 }
2396
2397 void do_dae_tl1(struct pt_regs *regs)
2398 {
2399 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2400 die_if_kernel("TL1: Data Access Exception", regs);
2401 }
2402
2403 void do_iae_tl1(struct pt_regs *regs)
2404 {
2405 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2406 die_if_kernel("TL1: Instruction Access Exception", regs);
2407 }
2408
2409 void do_div0_tl1(struct pt_regs *regs)
2410 {
2411 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2412 die_if_kernel("TL1: DIV0 Exception", regs);
2413 }
2414
2415 void do_fpdis_tl1(struct pt_regs *regs)
2416 {
2417 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2418 die_if_kernel("TL1: FPU Disabled", regs);
2419 }
2420
2421 void do_fpieee_tl1(struct pt_regs *regs)
2422 {
2423 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2424 die_if_kernel("TL1: FPU IEEE Exception", regs);
2425 }
2426
2427 void do_fpother_tl1(struct pt_regs *regs)
2428 {
2429 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2430 die_if_kernel("TL1: FPU Other Exception", regs);
2431 }
2432
2433 void do_ill_tl1(struct pt_regs *regs)
2434 {
2435 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2436 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2437 }
2438
2439 void do_irq_tl1(struct pt_regs *regs)
2440 {
2441 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2442 die_if_kernel("TL1: IRQ Exception", regs);
2443 }
2444
2445 void do_lddfmna_tl1(struct pt_regs *regs)
2446 {
2447 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2448 die_if_kernel("TL1: LDDF Exception", regs);
2449 }
2450
2451 void do_stdfmna_tl1(struct pt_regs *regs)
2452 {
2453 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2454 die_if_kernel("TL1: STDF Exception", regs);
2455 }
2456
2457 void do_paw(struct pt_regs *regs)
2458 {
2459 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2460 }
2461
2462 void do_paw_tl1(struct pt_regs *regs)
2463 {
2464 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2465 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2466 }
2467
2468 void do_vaw(struct pt_regs *regs)
2469 {
2470 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2471 }
2472
2473 void do_vaw_tl1(struct pt_regs *regs)
2474 {
2475 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2476 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2477 }
2478
2479 void do_tof_tl1(struct pt_regs *regs)
2480 {
2481 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2482 die_if_kernel("TL1: Tag Overflow Exception", regs);
2483 }
2484
2485 void do_getpsr(struct pt_regs *regs)
2486 {
2487 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2488 regs->tpc = regs->tnpc;
2489 regs->tnpc += 4;
2490 if (test_thread_flag(TIF_32BIT)) {
2491 regs->tpc &= 0xffffffff;
2492 regs->tnpc &= 0xffffffff;
2493 }
2494 }
2495
2496 struct trap_per_cpu trap_block[NR_CPUS];
2497
2498 /* This can get invoked before sched_init() so play it super safe
2499 * and use hard_smp_processor_id().
2500 */
2501 void init_cur_cpu_trap(struct thread_info *t)
2502 {
2503 int cpu = hard_smp_processor_id();
2504 struct trap_per_cpu *p = &trap_block[cpu];
2505
2506 p->thread = t;
2507 p->pgd_paddr = 0;
2508 }
2509
2510 extern void thread_info_offsets_are_bolixed_dave(void);
2511 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2512 extern void tsb_config_offsets_are_bolixed_dave(void);
2513
2514 /* Only invoked on boot processor. */
2515 void __init trap_init(void)
2516 {
2517 /* Compile time sanity check. */
2518 if (TI_TASK != offsetof(struct thread_info, task) ||
2519 TI_FLAGS != offsetof(struct thread_info, flags) ||
2520 TI_CPU != offsetof(struct thread_info, cpu) ||
2521 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2522 TI_KSP != offsetof(struct thread_info, ksp) ||
2523 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2524 TI_KREGS != offsetof(struct thread_info, kregs) ||
2525 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2526 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2527 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2528 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2529 TI_GSR != offsetof(struct thread_info, gsr) ||
2530 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2531 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2532 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2533 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2534 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2535 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2536 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2537 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2538 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2539 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2540 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2541 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2542 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2543 (TI_FPREGS & (64 - 1)))
2544 thread_info_offsets_are_bolixed_dave();
2545
2546 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
2547 (TRAP_PER_CPU_PGD_PADDR !=
2548 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2549 (TRAP_PER_CPU_CPU_MONDO_PA !=
2550 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2551 (TRAP_PER_CPU_DEV_MONDO_PA !=
2552 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2553 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2554 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2555 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2556 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2557 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2558 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2559 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2560 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2561 (TRAP_PER_CPU_FAULT_INFO !=
2562 offsetof(struct trap_per_cpu, fault_info)) ||
2563 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2564 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2565 (TRAP_PER_CPU_CPU_LIST_PA !=
2566 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2567 (TRAP_PER_CPU_TSB_HUGE !=
2568 offsetof(struct trap_per_cpu, tsb_huge)) ||
2569 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2570 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2571 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2572 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2573 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2574 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2575 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2576 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2577 (TRAP_PER_CPU_RESUM_QMASK !=
2578 offsetof(struct trap_per_cpu, resum_qmask)) ||
2579 (TRAP_PER_CPU_NONRESUM_QMASK !=
2580 offsetof(struct trap_per_cpu, nonresum_qmask)))
2581 trap_per_cpu_offsets_are_bolixed_dave();
2582
2583 if ((TSB_CONFIG_TSB !=
2584 offsetof(struct tsb_config, tsb)) ||
2585 (TSB_CONFIG_RSS_LIMIT !=
2586 offsetof(struct tsb_config, tsb_rss_limit)) ||
2587 (TSB_CONFIG_NENTRIES !=
2588 offsetof(struct tsb_config, tsb_nentries)) ||
2589 (TSB_CONFIG_REG_VAL !=
2590 offsetof(struct tsb_config, tsb_reg_val)) ||
2591 (TSB_CONFIG_MAP_VADDR !=
2592 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2593 (TSB_CONFIG_MAP_PTE !=
2594 offsetof(struct tsb_config, tsb_map_pte)))
2595 tsb_config_offsets_are_bolixed_dave();
2596
2597 /* Attach to the address space of init_task. On SMP we
2598 * do this in smp.c:smp_callin for other cpus.
2599 */
2600 atomic_inc(&init_mm.mm_count);
2601 current->active_mm = &init_mm;
2602 }
Linux kernel - Deliverables
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