1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
11 /* Invoked from TLB miss handler, we are in the
12 * MMU global registers and they are setup like
15 * %g1: TSB entry pointer
16 * %g2: available temporary
17 * %g3: FAULT_CODE_{D,I}TLB
18 * %g4: available temporary
19 * %g5: available temporary
21 * %g7: physical address base of the linux page
22 * tables for the current address space
26 mov TLB_TAG_ACCESS, %g4
27 ldxa [%g4] ASI_DMMU, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
33 mov TLB_TAG_ACCESS, %g4
34 ldxa [%g4] ASI_IMMU, %g4
35 ba,pt %xcc, tsb_miss_page_table_walk
38 tsb_miss_page_table_walk:
39 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
42 TSB_LOCK_TAG(%g1, %g2, %g4)
44 /* Load and check PTE. */
45 ldxa [%g5] ASI_PHYS_USE_EC, %g5
46 brgez,a,pn %g5, tsb_do_fault
49 TSB_WRITE(%g1, %g5, %g6)
51 /* Finally, load TLB and return from trap. */
53 cmp %g3, FAULT_CODE_DTLB
54 bne,pn %xcc, tsb_itlb_load
58 stxa %g5, [%g0] ASI_DTLB_DATA_IN
62 stxa %g5, [%g0] ASI_ITLB_DATA_IN
65 /* No valid entry in the page tables, do full fault
71 cmp %g3, FAULT_CODE_DTLB
73 bne,pn %xcc, tsb_do_itlb_fault
74 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
79 mov TLB_TAG_ACCESS, %g4
80 ldxa [%g4] ASI_DMMU, %g5
81 be,pt %xcc, sparc64_realfault_common
82 mov FAULT_CODE_DTLB, %g4
83 ba,pt %xcc, winfix_trampoline
88 ba,pt %xcc, sparc64_realfault_common
89 mov FAULT_CODE_ITLB, %g4
91 .globl sparc64_realfault_common
92 sparc64_realfault_common:
93 stb %g4, [%g6 + TI_FAULT_CODE] ! Save fault code
94 stx %g5, [%g6 + TI_FAULT_ADDR] ! Save fault address
95 ba,pt %xcc, etrap ! Save trap state
97 call do_sparc64_fault ! Call fault handler
98 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
99 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
100 nop ! Delay slot (fill me)
102 .globl winfix_trampoline
104 rdpr %tpc, %g3 ! Prepare winfixup TNPC
105 or %g3, 0x7c, %g3 ! Compute branch offset
106 wrpr %g3, %tnpc ! Write it into TNPC
109 /* Reload MMU related context switch state at
112 * %o0: page table physical address
115 .globl tsb_context_switch
117 wrpr %g0, PSTATE_MG | PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV, %pstate
119 /* Set page table base alternate global. */
122 /* XXX can this happen? */
126 /* Lock TSB into D-TLB. */
127 sethi %hi(PAGE_SIZE), %o3
129 sethi %hi(TSBMAP_BASE), %o2
132 /* XXX handle PAGE_SIZE != 8K correctly... */
134 stxa %o2, [%g1] ASI_DMMU
137 stxa %o2, [%g1] ASI_IMMU
140 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZBITS)^0xfffff80000000000)
141 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W | _PAGE_L)
142 sethi %uhi(KERN_HIGHBITS), %g2
143 or %g2, %ulo(KERN_HIGHBITS), %g2
145 or %g2, KERN_LOWBITS, %g2
151 /* We use entry 61 for this locked entry. This is the spitfire
152 * TLB entry number, and luckily cheetah masks the value with
153 * 15 ending us up with entry 13 which is what we want in that
156 * XXX Interactions with prom_world()...
158 mov TLB_TAG_ACCESS, %g1
159 stxa %o2, [%g1] ASI_DMMU
162 stxa %o1, [%g1] ASI_DTLB_DATA_ACCESS
166 wrpr %g0, PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE, %pstate