arch/sparc64/kernel/tsb.S

   1 /* tsb.S: Sparc64 TSB table handling.
   2  *
   3  * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
   4  */
   5
   6 #include <asm/tsb.h>
   7 #include <asm/hypervisor.h>
   8
   9         .text
  10         .align  32
  11
  12         /* Invoked from TLB miss handler, we are in the
  13          * MMU global registers and they are setup like
  14          * this:
  15          *
  16          * %g1: TSB entry pointer
  17          * %g2: available temporary
  18          * %g3: FAULT_CODE_{D,I}TLB
  19          * %g4: available temporary
  20          * %g5: available temporary
  21          * %g6: TAG TARGET
  22          * %g7: available temporary, will be loaded by us with
  23          *      the physical address base of the linux page
  24          *      tables for the current address space
  25          */
  26 tsb_miss_dtlb:
  27         mov             TLB_TAG_ACCESS, %g4
  28         ba,pt           %xcc, tsb_miss_page_table_walk
  29          ldxa           [%g4] ASI_DMMU, %g4
  30
  31 tsb_miss_itlb:
  32         mov             TLB_TAG_ACCESS, %g4
  33         ba,pt           %xcc, tsb_miss_page_table_walk
  34          ldxa           [%g4] ASI_IMMU, %g4
  35
  36         /* At this point we have:
  37          * %g4 --       missing virtual address
  38          * %g1 --       TSB entry address
  39          * %g6 --       TAG TARGET ((vaddr >> 22) | (ctx << 48))
  40          */
  41 tsb_miss_page_table_walk:
  42         TRAP_LOAD_PGD_PHYS(%g7, %g5)
  43
  44         /* And now we have the PGD base physical address in %g7.  */
  45 tsb_miss_page_table_walk_sun4v_fastpath:
  46         USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
  47
  48 tsb_reload:
  49         TSB_LOCK_TAG(%g1, %g2, %g7)
  50
  51         /* Load and check PTE.  */
  52         ldxa            [%g5] ASI_PHYS_USE_EC, %g5
  53         brgez,a,pn      %g5, tsb_do_fault
  54          TSB_STORE(%g1, %g0)
  55
  56         /* If it is larger than the base page size, don't
  57          * bother putting it into the TSB.
  58          */
  59         sethi           %hi(_PAGE_ALL_SZ_BITS), %g7
  60         ldx             [%g7 + %lo(_PAGE_ALL_SZ_BITS)], %g7
  61         and             %g5, %g7, %g2
  62         sethi           %hi(_PAGE_SZBITS), %g7
  63         ldx             [%g7 + %lo(_PAGE_SZBITS)], %g7
  64         cmp             %g2, %g7
  65         bne,a,pn        %xcc, tsb_tlb_reload
  66          TSB_STORE(%g1, %g0)
  67
  68         TSB_WRITE(%g1, %g5, %g6)
  69
  70         /* Finally, load TLB and return from trap.  */
  71 tsb_tlb_reload:
  72         cmp             %g3, FAULT_CODE_DTLB
  73         bne,pn          %xcc, tsb_itlb_load
  74          nop
  75
  76 tsb_dtlb_load:
  77
  78 661:    stxa            %g5, [%g0] ASI_DTLB_DATA_IN
  79         retry
  80         .section        .sun4v_2insn_patch, "ax"
  81         .word           661b
  82         nop
  83         nop
  84         .previous
  85
  86         /* For sun4v the ASI_DTLB_DATA_IN store and the retry
  87          * instruction get nop'd out and we get here to branch
  88          * to the sun4v tlb load code.  The registers are setup
  89          * as follows:
  90          *
  91          * %g4: vaddr
  92          * %g5: PTE
  93          * %g6: TAG
  94          *
  95          * The sun4v TLB load wants the PTE in %g3 so we fix that
  96          * up here.
  97          */
  98         ba,pt           %xcc, sun4v_dtlb_load
  99          mov            %g5, %g3
 100
 101 tsb_itlb_load:
 102
 103 661:    stxa            %g5, [%g0] ASI_ITLB_DATA_IN
 104         retry
 105         .section        .sun4v_2insn_patch, "ax"
 106         .word           661b
 107         nop
 108         nop
 109         .previous
 110
 111         /* For sun4v the ASI_ITLB_DATA_IN store and the retry
 112          * instruction get nop'd out and we get here to branch
 113          * to the sun4v tlb load code.  The registers are setup
 114          * as follows:
 115          *
 116          * %g4: vaddr
 117          * %g5: PTE
 118          * %g6: TAG
 119          *
 120          * The sun4v TLB load wants the PTE in %g3 so we fix that
 121          * up here.
 122          */
 123         ba,pt           %xcc, sun4v_itlb_load
 124          mov            %g5, %g3
 125
 126         /* No valid entry in the page tables, do full fault
 127          * processing.
 128          */
 129
 130         .globl          tsb_do_fault
 131 tsb_do_fault:
 132         cmp             %g3, FAULT_CODE_DTLB
 133
 134 661:    rdpr            %pstate, %g5
 135         wrpr            %g5, PSTATE_AG | PSTATE_MG, %pstate
 136         .section        .sun4v_2insn_patch, "ax"
 137         .word           661b
 138         nop
 139         nop
 140         .previous
 141
 142         bne,pn          %xcc, tsb_do_itlb_fault
 143          nop
 144
 145 tsb_do_dtlb_fault:
 146         rdpr    %tl, %g3
 147         cmp     %g3, 1
 148
 149 661:    mov     TLB_TAG_ACCESS, %g4
 150         ldxa    [%g4] ASI_DMMU, %g5
 151         .section .sun4v_2insn_patch, "ax"
 152         .word   661b
 153         mov     %g4, %g5
 154         nop
 155         .previous
 156
 157         be,pt   %xcc, sparc64_realfault_common
 158          mov    FAULT_CODE_DTLB, %g4
 159         ba,pt   %xcc, winfix_trampoline
 160          nop
 161
 162 tsb_do_itlb_fault:
 163         rdpr    %tpc, %g5
 164         ba,pt   %xcc, sparc64_realfault_common
 165          mov    FAULT_CODE_ITLB, %g4
 166
 167         .globl  sparc64_realfault_common
 168 sparc64_realfault_common:
 169         /* fault code in %g4, fault address in %g5, etrap will
 170          * preserve these two values in %l4 and %l5 respectively
 171          */
 172         ba,pt   %xcc, etrap                     ! Save trap state
 173 1:       rd     %pc, %g7                        ! ...
 174         stb     %l4, [%g6 + TI_FAULT_CODE]      ! Save fault code
 175         stx     %l5, [%g6 + TI_FAULT_ADDR]      ! Save fault address
 176         call    do_sparc64_fault                ! Call fault handler
 177          add    %sp, PTREGS_OFF, %o0            ! Compute pt_regs arg
 178         ba,pt   %xcc, rtrap_clr_l6              ! Restore cpu state
 179          nop                                    ! Delay slot (fill me)
 180
 181 winfix_trampoline:
 182         rdpr    %tpc, %g3                       ! Prepare winfixup TNPC
 183         or      %g3, 0x7c, %g3                  ! Compute branch offset
 184         wrpr    %g3, %tnpc                      ! Write it into TNPC
 185         done                                    ! Trap return
 186
 187         /* Insert an entry into the TSB.
 188          *
 189          * %o0: TSB entry pointer (virt or phys address)
 190          * %o1: tag
 191          * %o2: pte
 192          */
 193         .align  32
 194         .globl  __tsb_insert
 195 __tsb_insert:
 196         rdpr    %pstate, %o5
 197         wrpr    %o5, PSTATE_IE, %pstate
 198         TSB_LOCK_TAG(%o0, %g2, %g3)
 199         TSB_WRITE(%o0, %o2, %o1)
 200         wrpr    %o5, %pstate
 201         retl
 202          nop
 203
 204         /* Flush the given TSB entry if it has the matching
 205          * tag.
 206          *
 207          * %o0: TSB entry pointer (virt or phys address)
 208          * %o1: tag
 209          */
 210         .align  32
 211         .globl  tsb_flush
 212 tsb_flush:
 213         sethi   %hi(TSB_TAG_LOCK_HIGH), %g2
 214 1:      TSB_LOAD_TAG(%o0, %g1)
 215         srlx    %g1, 32, %o3
 216         andcc   %o3, %g2, %g0
 217         bne,pn  %icc, 1b
 218          membar #LoadLoad
 219         cmp     %g1, %o1
 220         bne,pt  %xcc, 2f
 221          clr    %o3
 222         TSB_CAS_TAG(%o0, %g1, %o3)
 223         cmp     %g1, %o3
 224         bne,pn  %xcc, 1b
 225          nop
 226 2:      retl
 227          TSB_MEMBAR
 228
 229         /* Reload MMU related context switch state at
 230          * schedule() time.
 231          *
 232          * %o0: page table physical address
 233          * %o1: TSB register value
 234          * %o2: TSB virtual address
 235          * %o3: TSB mapping locked PTE
 236          * %o4: Hypervisor TSB descriptor physical address
 237          *
 238          * We have to run this whole thing with interrupts
 239          * disabled so that the current cpu doesn't change
 240          * due to preemption.
 241          */
 242         .align  32
 243         .globl  __tsb_context_switch
 244 __tsb_context_switch:
 245         rdpr    %pstate, %o5
 246         wrpr    %o5, PSTATE_IE, %pstate
 247
 248         ldub    [%g6 + TI_CPU], %g1
 249         sethi   %hi(trap_block), %g2
 250         sllx    %g1, TRAP_BLOCK_SZ_SHIFT, %g1
 251         or      %g2, %lo(trap_block), %g2
 252         add     %g2, %g1, %g2
 253         stx     %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
 254
 255         sethi   %hi(tlb_type), %g1
 256         lduw    [%g1 + %lo(tlb_type)], %g1
 257         cmp     %g1, 3
 258         bne,pt  %icc, 1f
 259          nop
 260
 261         /* Hypervisor TSB switch. */
 262         mov     SCRATCHPAD_UTSBREG1, %g1
 263         stxa    %o1, [%g1] ASI_SCRATCHPAD
 264         mov     -1, %g2
 265         mov     SCRATCHPAD_UTSBREG2, %g1
 266         stxa    %g2, [%g1] ASI_SCRATCHPAD
 267
 268         /* Save away %o5's %pstate, we have to use %o5 for
 269          * the hypervisor call.
 270          */
 271         mov     %o5, %g1
 272
 273         mov     HV_FAST_MMU_TSB_CTXNON0, %o5
 274         mov     1, %o0
 275         mov     %o4, %o1
 276         ta      HV_FAST_TRAP
 277
 278         /* Finish up and restore %o5.  */
 279         ba,pt   %xcc, 9f
 280          mov    %g1, %o5
 281
 282         /* SUN4U TSB switch.  */
 283 1:      mov     TSB_REG, %g1
 284         stxa    %o1, [%g1] ASI_DMMU
 285         membar  #Sync
 286         stxa    %o1, [%g1] ASI_IMMU
 287         membar  #Sync
 288
 289 2:      brz     %o2, 9f
 290          nop
 291
 292         sethi   %hi(sparc64_highest_unlocked_tlb_ent), %g2
 293         mov     TLB_TAG_ACCESS, %g1
 294         lduw    [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
 295         stxa    %o2, [%g1] ASI_DMMU
 296         membar  #Sync
 297         sllx    %g2, 3, %g2
 298         stxa    %o3, [%g2] ASI_DTLB_DATA_ACCESS
 299         membar  #Sync
 300 9:
 301         wrpr    %o5, %pstate
 302
 303         retl
 304          nop