projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[SPARC64]: Set associativity of kernel TSB descriptor correctly.
[deliverable/linux.git] / arch / sparc64 / mm / init.c
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mm.h>
16 #include <linux/hugetlb.h>
17 #include <linux/slab.h>
18 #include <linux/initrd.h>
19 #include <linux/swap.h>
20 #include <linux/pagemap.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26
27 #include <asm/head.h>
28 #include <asm/system.h>
29 #include <asm/page.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
38 #include <asm/dma.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
43 #include <asm/tsb.h>
44 #include <asm/hypervisor.h>
45
46 extern void device_scan(void);
47
48 #define MAX_BANKS 32
49
50 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
51 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
52 static int pavail_ents __initdata;
53 static int pavail_rescan_ents __initdata;
54
55 static int cmp_p64(const void *a, const void *b)
56 {
57 const struct linux_prom64_registers *x = a, *y = b;
58
59 if (x->phys_addr > y->phys_addr)
60 return 1;
61 if (x->phys_addr < y->phys_addr)
62 return -1;
63 return 0;
64 }
65
66 static void __init read_obp_memory(const char *property,
67 struct linux_prom64_registers *regs,
68 int *num_ents)
69 {
70 int node = prom_finddevice("/memory");
71 int prop_size = prom_getproplen(node, property);
72 int ents, ret, i;
73
74 ents = prop_size / sizeof(struct linux_prom64_registers);
75 if (ents > MAX_BANKS) {
76 prom_printf("The machine has more %s property entries than "
77 "this kernel can support (%d).\n",
78 property, MAX_BANKS);
79 prom_halt();
80 }
81
82 ret = prom_getproperty(node, property, (char *) regs, prop_size);
83 if (ret == -1) {
84 prom_printf("Couldn't get %s property from /memory.\n");
85 prom_halt();
86 }
87
88 *num_ents = ents;
89
90 /* Sanitize what we got from the firmware, by page aligning
91 * everything.
92 */
93 for (i = 0; i < ents; i++) {
94 unsigned long base, size;
95
96 base = regs[i].phys_addr;
97 size = regs[i].reg_size;
98
99 size &= PAGE_MASK;
100 if (base & ~PAGE_MASK) {
101 unsigned long new_base = PAGE_ALIGN(base);
102
103 size -= new_base - base;
104 if ((long) size < 0L)
105 size = 0UL;
106 base = new_base;
107 }
108 regs[i].phys_addr = base;
109 regs[i].reg_size = size;
110 }
111 sort(regs, ents, sizeof(struct linux_prom64_registers),
112 cmp_p64, NULL);
113 }
114
115 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
116
117 /* Ugly, but necessary... -DaveM */
118 unsigned long phys_base __read_mostly;
119 unsigned long kern_base __read_mostly;
120 unsigned long kern_size __read_mostly;
121 unsigned long pfn_base __read_mostly;
122 unsigned long kern_linear_pte_xor __read_mostly;
123
124 /* get_new_mmu_context() uses "cache + 1". */
125 DEFINE_SPINLOCK(ctx_alloc_lock);
126 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
127 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
128 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
129
130 /* References to special section boundaries */
131 extern char _start[], _end[];
132
133 /* Initial ramdisk setup */
134 extern unsigned long sparc_ramdisk_image64;
135 extern unsigned int sparc_ramdisk_image;
136 extern unsigned int sparc_ramdisk_size;
137
138 struct page *mem_map_zero __read_mostly;
139
140 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
141
142 unsigned long sparc64_kern_pri_context __read_mostly;
143 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
144 unsigned long sparc64_kern_sec_context __read_mostly;
145
146 int bigkernel = 0;
147
148 kmem_cache_t *pgtable_cache __read_mostly;
149
150 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
151 {
152 clear_page(addr);
153 }
154
155 void pgtable_cache_init(void)
156 {
157 pgtable_cache = kmem_cache_create("pgtable_cache",
158 PAGE_SIZE, PAGE_SIZE,
159 SLAB_HWCACHE_ALIGN |
160 SLAB_MUST_HWCACHE_ALIGN,
161 zero_ctor,
162 NULL);
163 if (!pgtable_cache) {
164 prom_printf("pgtable_cache_init(): Could not create!\n");
165 prom_halt();
166 }
167 }
168
169 #ifdef CONFIG_DEBUG_DCFLUSH
170 atomic_t dcpage_flushes = ATOMIC_INIT(0);
171 #ifdef CONFIG_SMP
172 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
173 #endif
174 #endif
175
176 __inline__ void flush_dcache_page_impl(struct page *page)
177 {
178 #ifdef CONFIG_DEBUG_DCFLUSH
179 atomic_inc(&dcpage_flushes);
180 #endif
181
182 #ifdef DCACHE_ALIASING_POSSIBLE
183 __flush_dcache_page(page_address(page),
184 ((tlb_type == spitfire) &&
185 page_mapping(page) != NULL));
186 #else
187 if (page_mapping(page) != NULL &&
188 tlb_type == spitfire)
189 __flush_icache_page(__pa(page_address(page)));
190 #endif
191 }
192
193 #define PG_dcache_dirty PG_arch_1
194 #define PG_dcache_cpu_shift 24
195 #define PG_dcache_cpu_mask (256 - 1)
196
197 #if NR_CPUS > 256
198 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
199 #endif
200
201 #define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
203
204 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
205 {
206 unsigned long mask = this_cpu;
207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
218 "membar #StoreLoad | #StoreStore\n\t"
219 "bne,pn %%xcc, 1b\n\t"
220 " nop"
221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224 }
225
226 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "membar #StoreLoad | #StoreStore\n\t"
241 "bne,pn %%xcc, 1b\n\t"
242 " nop\n"
243 "2:"
244 : /* no outputs */
245 : "r" (cpu), "r" (mask), "r" (&page->flags),
246 "i" (PG_dcache_cpu_mask),
247 "i" (PG_dcache_cpu_shift)
248 : "g1", "g7");
249 }
250
251 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
252 {
253 unsigned long tsb_addr = (unsigned long) ent;
254
255 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
256 tsb_addr = __pa(tsb_addr);
257
258 __tsb_insert(tsb_addr, tag, pte);
259 }
260
261 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
262 unsigned long _PAGE_SZBITS __read_mostly;
263
264 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
265 {
266 struct mm_struct *mm;
267 struct page *page;
268 unsigned long pfn;
269 unsigned long pg_flags;
270
271 pfn = pte_pfn(pte);
272 if (pfn_valid(pfn) &&
273 (page = pfn_to_page(pfn), page_mapping(page)) &&
274 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
275 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
276 PG_dcache_cpu_mask);
277 int this_cpu = get_cpu();
278
279 /* This is just to optimize away some function calls
280 * in the SMP case.
281 */
282 if (cpu == this_cpu)
283 flush_dcache_page_impl(page);
284 else
285 smp_flush_dcache_page_impl(page, cpu);
286
287 clear_dcache_dirty_cpu(page, cpu);
288
289 put_cpu();
290 }
291
292 mm = vma->vm_mm;
293 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
294 struct tsb *tsb;
295 unsigned long tag;
296
297 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
298 (mm->context.tsb_nentries - 1UL)];
299 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
300 tsb_insert(tsb, tag, pte_val(pte));
301 }
302 }
303
304 void flush_dcache_page(struct page *page)
305 {
306 struct address_space *mapping;
307 int this_cpu;
308
309 /* Do not bother with the expensive D-cache flush if it
310 * is merely the zero page. The 'bigcore' testcase in GDB
311 * causes this case to run millions of times.
312 */
313 if (page == ZERO_PAGE(0))
314 return;
315
316 this_cpu = get_cpu();
317
318 mapping = page_mapping(page);
319 if (mapping && !mapping_mapped(mapping)) {
320 int dirty = test_bit(PG_dcache_dirty, &page->flags);
321 if (dirty) {
322 int dirty_cpu = dcache_dirty_cpu(page);
323
324 if (dirty_cpu == this_cpu)
325 goto out;
326 smp_flush_dcache_page_impl(page, dirty_cpu);
327 }
328 set_dcache_dirty(page, this_cpu);
329 } else {
330 /* We could delay the flush for the !page_mapping
331 * case too. But that case is for exec env/arg
332 * pages and those are %99 certainly going to get
333 * faulted into the tlb (and thus flushed) anyways.
334 */
335 flush_dcache_page_impl(page);
336 }
337
338 out:
339 put_cpu();
340 }
341
342 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
343 {
344 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
345 if (tlb_type == spitfire) {
346 unsigned long kaddr;
347
348 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
349 __flush_icache_page(__get_phys(kaddr));
350 }
351 }
352
353 unsigned long page_to_pfn(struct page *page)
354 {
355 return (unsigned long) ((page - mem_map) + pfn_base);
356 }
357
358 struct page *pfn_to_page(unsigned long pfn)
359 {
360 return (mem_map + (pfn - pfn_base));
361 }
362
363 void show_mem(void)
364 {
365 printk("Mem-info:\n");
366 show_free_areas();
367 printk("Free swap: %6ldkB\n",
368 nr_swap_pages << (PAGE_SHIFT-10));
369 printk("%ld pages of RAM\n", num_physpages);
370 printk("%d free pages\n", nr_free_pages());
371 }
372
373 void mmu_info(struct seq_file *m)
374 {
375 if (tlb_type == cheetah)
376 seq_printf(m, "MMU Type\t: Cheetah\n");
377 else if (tlb_type == cheetah_plus)
378 seq_printf(m, "MMU Type\t: Cheetah+\n");
379 else if (tlb_type == spitfire)
380 seq_printf(m, "MMU Type\t: Spitfire\n");
381 else if (tlb_type == hypervisor)
382 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
383 else
384 seq_printf(m, "MMU Type\t: ???\n");
385
386 #ifdef CONFIG_DEBUG_DCFLUSH
387 seq_printf(m, "DCPageFlushes\t: %d\n",
388 atomic_read(&dcpage_flushes));
389 #ifdef CONFIG_SMP
390 seq_printf(m, "DCPageFlushesXC\t: %d\n",
391 atomic_read(&dcpage_flushes_xcall));
392 #endif /* CONFIG_SMP */
393 #endif /* CONFIG_DEBUG_DCFLUSH */
394 }
395
396 struct linux_prom_translation {
397 unsigned long virt;
398 unsigned long size;
399 unsigned long data;
400 };
401
402 /* Exported for kernel TLB miss handling in ktlb.S */
403 struct linux_prom_translation prom_trans[512] __read_mostly;
404 unsigned int prom_trans_ents __read_mostly;
405
406 /* Exported for SMP bootup purposes. */
407 unsigned long kern_locked_tte_data;
408
409 /* The obp translations are saved based on 8k pagesize, since obp can
410 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
411 * HI_OBP_ADDRESS range are handled in ktlb.S.
412 */
413 static inline int in_obp_range(unsigned long vaddr)
414 {
415 return (vaddr >= LOW_OBP_ADDRESS &&
416 vaddr < HI_OBP_ADDRESS);
417 }
418
419 static int cmp_ptrans(const void *a, const void *b)
420 {
421 const struct linux_prom_translation *x = a, *y = b;
422
423 if (x->virt > y->virt)
424 return 1;
425 if (x->virt < y->virt)
426 return -1;
427 return 0;
428 }
429
430 /* Read OBP translations property into 'prom_trans[]'. */
431 static void __init read_obp_translations(void)
432 {
433 int n, node, ents, first, last, i;
434
435 node = prom_finddevice("/virtual-memory");
436 n = prom_getproplen(node, "translations");
437 if (unlikely(n == 0 || n == -1)) {
438 prom_printf("prom_mappings: Couldn't get size.\n");
439 prom_halt();
440 }
441 if (unlikely(n > sizeof(prom_trans))) {
442 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
443 prom_halt();
444 }
445
446 if ((n = prom_getproperty(node, "translations",
447 (char *)&prom_trans[0],
448 sizeof(prom_trans))) == -1) {
449 prom_printf("prom_mappings: Couldn't get property.\n");
450 prom_halt();
451 }
452
453 n = n / sizeof(struct linux_prom_translation);
454
455 ents = n;
456
457 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
458 cmp_ptrans, NULL);
459
460 /* Now kick out all the non-OBP entries. */
461 for (i = 0; i < ents; i++) {
462 if (in_obp_range(prom_trans[i].virt))
463 break;
464 }
465 first = i;
466 for (; i < ents; i++) {
467 if (!in_obp_range(prom_trans[i].virt))
468 break;
469 }
470 last = i;
471
472 for (i = 0; i < (last - first); i++) {
473 struct linux_prom_translation *src = &prom_trans[i + first];
474 struct linux_prom_translation *dest = &prom_trans[i];
475
476 *dest = *src;
477 }
478 for (; i < ents; i++) {
479 struct linux_prom_translation *dest = &prom_trans[i];
480 dest->virt = dest->size = dest->data = 0x0UL;
481 }
482
483 prom_trans_ents = last - first;
484
485 if (tlb_type == spitfire) {
486 /* Clear diag TTE bits. */
487 for (i = 0; i < prom_trans_ents; i++)
488 prom_trans[i].data &= ~0x0003fe0000000000UL;
489 }
490 }
491
492 static void __init hypervisor_tlb_lock(unsigned long vaddr,
493 unsigned long pte,
494 unsigned long mmu)
495 {
496 register unsigned long func asm("%o5");
497 register unsigned long arg0 asm("%o0");
498 register unsigned long arg1 asm("%o1");
499 register unsigned long arg2 asm("%o2");
500 register unsigned long arg3 asm("%o3");
501
502 func = HV_FAST_MMU_MAP_PERM_ADDR;
503 arg0 = vaddr;
504 arg1 = 0;
505 arg2 = pte;
506 arg3 = mmu;
507 __asm__ __volatile__("ta 0x80"
508 : "=&r" (func), "=&r" (arg0),
509 "=&r" (arg1), "=&r" (arg2),
510 "=&r" (arg3)
511 : "0" (func), "1" (arg0), "2" (arg1),
512 "3" (arg2), "4" (arg3));
513 }
514
515 static unsigned long kern_large_tte(unsigned long paddr);
516
517 static void __init remap_kernel(void)
518 {
519 unsigned long phys_page, tte_vaddr, tte_data;
520 int tlb_ent = sparc64_highest_locked_tlbent();
521
522 tte_vaddr = (unsigned long) KERNBASE;
523 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
524 tte_data = kern_large_tte(phys_page);
525
526 kern_locked_tte_data = tte_data;
527
528 /* Now lock us into the TLBs via Hypervisor or OBP. */
529 if (tlb_type == hypervisor) {
530 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
531 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
532 if (bigkernel) {
533 tte_vaddr += 0x400000;
534 tte_data += 0x400000;
535 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
536 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
537 }
538 } else {
539 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
540 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
541 if (bigkernel) {
542 tlb_ent -= 1;
543 prom_dtlb_load(tlb_ent,
544 tte_data + 0x400000,
545 tte_vaddr + 0x400000);
546 prom_itlb_load(tlb_ent,
547 tte_data + 0x400000,
548 tte_vaddr + 0x400000);
549 }
550 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
551 }
552 if (tlb_type == cheetah_plus) {
553 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
554 CTX_CHEETAH_PLUS_NUC);
555 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
556 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
557 }
558 }
559
560
561 static void __init inherit_prom_mappings(void)
562 {
563 read_obp_translations();
564
565 /* Now fixup OBP's idea about where we really are mapped. */
566 prom_printf("Remapping the kernel... ");
567 remap_kernel();
568 prom_printf("done.\n");
569 }
570
571 void prom_world(int enter)
572 {
573 if (!enter)
574 set_fs((mm_segment_t) { get_thread_current_ds() });
575
576 __asm__ __volatile__("flushw");
577 }
578
579 #ifdef DCACHE_ALIASING_POSSIBLE
580 void __flush_dcache_range(unsigned long start, unsigned long end)
581 {
582 unsigned long va;
583
584 if (tlb_type == spitfire) {
585 int n = 0;
586
587 for (va = start; va < end; va += 32) {
588 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
589 if (++n >= 512)
590 break;
591 }
592 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
593 start = __pa(start);
594 end = __pa(end);
595 for (va = start; va < end; va += 32)
596 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
597 "membar #Sync"
598 : /* no outputs */
599 : "r" (va),
600 "i" (ASI_DCACHE_INVALIDATE));
601 }
602 }
603 #endif /* DCACHE_ALIASING_POSSIBLE */
604
605 /* Caller does TLB context flushing on local CPU if necessary.
606 * The caller also ensures that CTX_VALID(mm->context) is false.
607 *
608 * We must be careful about boundary cases so that we never
609 * let the user have CTX 0 (nucleus) or we ever use a CTX
610 * version of zero (and thus NO_CONTEXT would not be caught
611 * by version mis-match tests in mmu_context.h).
612 */
613 void get_new_mmu_context(struct mm_struct *mm)
614 {
615 unsigned long ctx, new_ctx;
616 unsigned long orig_pgsz_bits;
617
618
619 spin_lock(&ctx_alloc_lock);
620 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
621 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
622 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
623 if (new_ctx >= (1 << CTX_NR_BITS)) {
624 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
625 if (new_ctx >= ctx) {
626 int i;
627 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
628 CTX_FIRST_VERSION;
629 if (new_ctx == 1)
630 new_ctx = CTX_FIRST_VERSION;
631
632 /* Don't call memset, for 16 entries that's just
633 * plain silly...
634 */
635 mmu_context_bmap[0] = 3;
636 mmu_context_bmap[1] = 0;
637 mmu_context_bmap[2] = 0;
638 mmu_context_bmap[3] = 0;
639 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
640 mmu_context_bmap[i + 0] = 0;
641 mmu_context_bmap[i + 1] = 0;
642 mmu_context_bmap[i + 2] = 0;
643 mmu_context_bmap[i + 3] = 0;
644 }
645 goto out;
646 }
647 }
648 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
649 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
650 out:
651 tlb_context_cache = new_ctx;
652 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
653 spin_unlock(&ctx_alloc_lock);
654 }
655
656 void sparc_ultra_dump_itlb(void)
657 {
658 int slot;
659
660 if (tlb_type == spitfire) {
661 printk ("Contents of itlb: ");
662 for (slot = 0; slot < 14; slot++) printk (" ");
663 printk ("%2x:%016lx,%016lx\n",
664 0,
665 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
666 for (slot = 1; slot < 64; slot+=3) {
667 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
668 slot,
669 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
670 slot+1,
671 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
672 slot+2,
673 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
674 }
675 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
676 printk ("Contents of itlb0:\n");
677 for (slot = 0; slot < 16; slot+=2) {
678 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
679 slot,
680 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
681 slot+1,
682 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
683 }
684 printk ("Contents of itlb2:\n");
685 for (slot = 0; slot < 128; slot+=2) {
686 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
687 slot,
688 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
689 slot+1,
690 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
691 }
692 }
693 }
694
695 void sparc_ultra_dump_dtlb(void)
696 {
697 int slot;
698
699 if (tlb_type == spitfire) {
700 printk ("Contents of dtlb: ");
701 for (slot = 0; slot < 14; slot++) printk (" ");
702 printk ("%2x:%016lx,%016lx\n", 0,
703 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
704 for (slot = 1; slot < 64; slot+=3) {
705 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
706 slot,
707 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
708 slot+1,
709 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
710 slot+2,
711 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
712 }
713 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
714 printk ("Contents of dtlb0:\n");
715 for (slot = 0; slot < 16; slot+=2) {
716 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
717 slot,
718 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
719 slot+1,
720 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
721 }
722 printk ("Contents of dtlb2:\n");
723 for (slot = 0; slot < 512; slot+=2) {
724 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
725 slot,
726 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
727 slot+1,
728 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
729 }
730 if (tlb_type == cheetah_plus) {
731 printk ("Contents of dtlb3:\n");
732 for (slot = 0; slot < 512; slot+=2) {
733 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
734 slot,
735 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
736 slot+1,
737 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
738 }
739 }
740 }
741 }
742
743 extern unsigned long cmdline_memory_size;
744
745 unsigned long __init bootmem_init(unsigned long *pages_avail)
746 {
747 unsigned long bootmap_size, start_pfn, end_pfn;
748 unsigned long end_of_phys_memory = 0UL;
749 unsigned long bootmap_pfn, bytes_avail, size;
750 int i;
751
752 #ifdef CONFIG_DEBUG_BOOTMEM
753 prom_printf("bootmem_init: Scan pavail, ");
754 #endif
755
756 bytes_avail = 0UL;
757 for (i = 0; i < pavail_ents; i++) {
758 end_of_phys_memory = pavail[i].phys_addr +
759 pavail[i].reg_size;
760 bytes_avail += pavail[i].reg_size;
761 if (cmdline_memory_size) {
762 if (bytes_avail > cmdline_memory_size) {
763 unsigned long slack = bytes_avail - cmdline_memory_size;
764
765 bytes_avail -= slack;
766 end_of_phys_memory -= slack;
767
768 pavail[i].reg_size -= slack;
769 if ((long)pavail[i].reg_size <= 0L) {
770 pavail[i].phys_addr = 0xdeadbeefUL;
771 pavail[i].reg_size = 0UL;
772 pavail_ents = i;
773 } else {
774 pavail[i+1].reg_size = 0Ul;
775 pavail[i+1].phys_addr = 0xdeadbeefUL;
776 pavail_ents = i + 1;
777 }
778 break;
779 }
780 }
781 }
782
783 *pages_avail = bytes_avail >> PAGE_SHIFT;
784
785 /* Start with page aligned address of last symbol in kernel
786 * image. The kernel is hard mapped below PAGE_OFFSET in a
787 * 4MB locked TLB translation.
788 */
789 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
790
791 bootmap_pfn = start_pfn;
792
793 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
794
795 #ifdef CONFIG_BLK_DEV_INITRD
796 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
797 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
798 unsigned long ramdisk_image = sparc_ramdisk_image ?
799 sparc_ramdisk_image : sparc_ramdisk_image64;
800 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
801 ramdisk_image -= KERNBASE;
802 initrd_start = ramdisk_image + phys_base;
803 initrd_end = initrd_start + sparc_ramdisk_size;
804 if (initrd_end > end_of_phys_memory) {
805 printk(KERN_CRIT "initrd extends beyond end of memory "
806 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
807 initrd_end, end_of_phys_memory);
808 initrd_start = 0;
809 }
810 if (initrd_start) {
811 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
812 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
813 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
814 }
815 }
816 #endif
817 /* Initialize the boot-time allocator. */
818 max_pfn = max_low_pfn = end_pfn;
819 min_low_pfn = pfn_base;
820
821 #ifdef CONFIG_DEBUG_BOOTMEM
822 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
823 min_low_pfn, bootmap_pfn, max_low_pfn);
824 #endif
825 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
826
827 /* Now register the available physical memory with the
828 * allocator.
829 */
830 for (i = 0; i < pavail_ents; i++) {
831 #ifdef CONFIG_DEBUG_BOOTMEM
832 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
833 i, pavail[i].phys_addr, pavail[i].reg_size);
834 #endif
835 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
836 }
837
838 #ifdef CONFIG_BLK_DEV_INITRD
839 if (initrd_start) {
840 size = initrd_end - initrd_start;
841
842 /* Resert the initrd image area. */
843 #ifdef CONFIG_DEBUG_BOOTMEM
844 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
845 initrd_start, initrd_end);
846 #endif
847 reserve_bootmem(initrd_start, size);
848 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
849
850 initrd_start += PAGE_OFFSET;
851 initrd_end += PAGE_OFFSET;
852 }
853 #endif
854 /* Reserve the kernel text/data/bss. */
855 #ifdef CONFIG_DEBUG_BOOTMEM
856 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
857 #endif
858 reserve_bootmem(kern_base, kern_size);
859 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
860
861 /* Reserve the bootmem map. We do not account for it
862 * in pages_avail because we will release that memory
863 * in free_all_bootmem.
864 */
865 size = bootmap_size;
866 #ifdef CONFIG_DEBUG_BOOTMEM
867 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
868 (bootmap_pfn << PAGE_SHIFT), size);
869 #endif
870 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
871 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
872
873 return end_pfn;
874 }
875
876 #ifdef CONFIG_DEBUG_PAGEALLOC
877 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
878 {
879 unsigned long vstart = PAGE_OFFSET + pstart;
880 unsigned long vend = PAGE_OFFSET + pend;
881 unsigned long alloc_bytes = 0UL;
882
883 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
884 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
885 vstart, vend);
886 prom_halt();
887 }
888
889 while (vstart < vend) {
890 unsigned long this_end, paddr = __pa(vstart);
891 pgd_t *pgd = pgd_offset_k(vstart);
892 pud_t *pud;
893 pmd_t *pmd;
894 pte_t *pte;
895
896 pud = pud_offset(pgd, vstart);
897 if (pud_none(*pud)) {
898 pmd_t *new;
899
900 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
901 alloc_bytes += PAGE_SIZE;
902 pud_populate(&init_mm, pud, new);
903 }
904
905 pmd = pmd_offset(pud, vstart);
906 if (!pmd_present(*pmd)) {
907 pte_t *new;
908
909 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
910 alloc_bytes += PAGE_SIZE;
911 pmd_populate_kernel(&init_mm, pmd, new);
912 }
913
914 pte = pte_offset_kernel(pmd, vstart);
915 this_end = (vstart + PMD_SIZE) & PMD_MASK;
916 if (this_end > vend)
917 this_end = vend;
918
919 while (vstart < this_end) {
920 pte_val(*pte) = (paddr | pgprot_val(prot));
921
922 vstart += PAGE_SIZE;
923 paddr += PAGE_SIZE;
924 pte++;
925 }
926 }
927
928 return alloc_bytes;
929 }
930
931 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
932 static int pall_ents __initdata;
933
934 extern unsigned int kvmap_linear_patch[1];
935
936 static void __init kernel_physical_mapping_init(void)
937 {
938 unsigned long i, mem_alloced = 0UL;
939
940 read_obp_memory("reg", &pall[0], &pall_ents);
941
942 for (i = 0; i < pall_ents; i++) {
943 unsigned long phys_start, phys_end;
944
945 phys_start = pall[i].phys_addr;
946 phys_end = phys_start + pall[i].reg_size;
947 mem_alloced += kernel_map_range(phys_start, phys_end,
948 PAGE_KERNEL);
949 }
950
951 printk("Allocated %ld bytes for kernel page tables.\n",
952 mem_alloced);
953
954 kvmap_linear_patch[0] = 0x01000000; /* nop */
955 flushi(&kvmap_linear_patch[0]);
956
957 __flush_tlb_all();
958 }
959
960 void kernel_map_pages(struct page *page, int numpages, int enable)
961 {
962 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
963 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
964
965 kernel_map_range(phys_start, phys_end,
966 (enable ? PAGE_KERNEL : __pgprot(0)));
967
968 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
969 PAGE_OFFSET + phys_end);
970
971 /* we should perform an IPI and flush all tlbs,
972 * but that can deadlock->flush only current cpu.
973 */
974 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
975 PAGE_OFFSET + phys_end);
976 }
977 #endif
978
979 unsigned long __init find_ecache_flush_span(unsigned long size)
980 {
981 int i;
982
983 for (i = 0; i < pavail_ents; i++) {
984 if (pavail[i].reg_size >= size)
985 return pavail[i].phys_addr;
986 }
987
988 return ~0UL;
989 }
990
991 static void __init tsb_phys_patch(void)
992 {
993 struct tsb_ldquad_phys_patch_entry *pquad;
994 struct tsb_phys_patch_entry *p;
995
996 pquad = &__tsb_ldquad_phys_patch;
997 while (pquad < &__tsb_ldquad_phys_patch_end) {
998 unsigned long addr = pquad->addr;
999
1000 if (tlb_type == hypervisor)
1001 *(unsigned int *) addr = pquad->sun4v_insn;
1002 else
1003 *(unsigned int *) addr = pquad->sun4u_insn;
1004 wmb();
1005 __asm__ __volatile__("flush %0"
1006 : /* no outputs */
1007 : "r" (addr));
1008
1009 pquad++;
1010 }
1011
1012 p = &__tsb_phys_patch;
1013 while (p < &__tsb_phys_patch_end) {
1014 unsigned long addr = p->addr;
1015
1016 *(unsigned int *) addr = p->insn;
1017 wmb();
1018 __asm__ __volatile__("flush %0"
1019 : /* no outputs */
1020 : "r" (addr));
1021
1022 p++;
1023 }
1024 }
1025
1026 /* Don't mark as init, we give this to the Hypervisor. */
1027 static struct hv_tsb_descr ktsb_descr[2];
1028 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1029
1030 static void __init sun4v_ktsb_init(void)
1031 {
1032 unsigned long ktsb_pa;
1033
1034 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1035
1036 switch (PAGE_SIZE) {
1037 case 8 * 1024:
1038 default:
1039 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1040 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1041 break;
1042
1043 case 64 * 1024:
1044 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1045 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1046 break;
1047
1048 case 512 * 1024:
1049 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1050 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1051 break;
1052
1053 case 4 * 1024 * 1024:
1054 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1055 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1056 break;
1057 };
1058
1059 ktsb_descr[0].assoc = 1;
1060 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1061 ktsb_descr[0].ctx_idx = 0;
1062 ktsb_descr[0].tsb_base = ktsb_pa;
1063 ktsb_descr[0].resv = 0;
1064
1065 /* XXX When we have a kernel large page size TSB, describe
1066 * XXX it in ktsb_descr[1] here.
1067 */
1068 }
1069
1070 void __cpuinit sun4v_ktsb_register(void)
1071 {
1072 register unsigned long func asm("%o5");
1073 register unsigned long arg0 asm("%o0");
1074 register unsigned long arg1 asm("%o1");
1075 unsigned long pa;
1076
1077 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1078
1079 func = HV_FAST_MMU_TSB_CTX0;
1080 /* XXX set arg0 to 2 when we use ktsb_descr[1], see above XXX */
1081 arg0 = 1;
1082 arg1 = pa;
1083 __asm__ __volatile__("ta %6"
1084 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1085 : "0" (func), "1" (arg0), "2" (arg1),
1086 "i" (HV_FAST_TRAP));
1087 }
1088
1089 /* paging_init() sets up the page tables */
1090
1091 extern void cheetah_ecache_flush_init(void);
1092 extern void sun4v_patch_tlb_handlers(void);
1093
1094 static unsigned long last_valid_pfn;
1095 pgd_t swapper_pg_dir[2048];
1096
1097 static void sun4u_pgprot_init(void);
1098 static void sun4v_pgprot_init(void);
1099
1100 void __init paging_init(void)
1101 {
1102 unsigned long end_pfn, pages_avail, shift;
1103 unsigned long real_end, i;
1104
1105 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1106 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1107
1108 if (tlb_type == hypervisor)
1109 sun4v_pgprot_init();
1110 else
1111 sun4u_pgprot_init();
1112
1113 if (tlb_type == cheetah_plus ||
1114 tlb_type == hypervisor)
1115 tsb_phys_patch();
1116
1117 if (tlb_type == hypervisor) {
1118 sun4v_patch_tlb_handlers();
1119 sun4v_ktsb_init();
1120 }
1121
1122 /* Find available physical memory... */
1123 read_obp_memory("available", &pavail[0], &pavail_ents);
1124
1125 phys_base = 0xffffffffffffffffUL;
1126 for (i = 0; i < pavail_ents; i++)
1127 phys_base = min(phys_base, pavail[i].phys_addr);
1128
1129 pfn_base = phys_base >> PAGE_SHIFT;
1130
1131 set_bit(0, mmu_context_bmap);
1132
1133 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1134
1135 real_end = (unsigned long)_end;
1136 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1137 bigkernel = 1;
1138 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1139 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1140 prom_halt();
1141 }
1142
1143 /* Set kernel pgd to upper alias so physical page computations
1144 * work.
1145 */
1146 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1147
1148 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1149
1150 /* Now can init the kernel/bad page tables. */
1151 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1152 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1153
1154 inherit_prom_mappings();
1155
1156 /* Ok, we can use our TLB miss and window trap handlers safely. */
1157 setup_tba();
1158
1159 __flush_tlb_all();
1160
1161 if (tlb_type == hypervisor)
1162 sun4v_ktsb_register();
1163
1164 /* Setup bootmem... */
1165 pages_avail = 0;
1166 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1167
1168 #ifdef CONFIG_DEBUG_PAGEALLOC
1169 kernel_physical_mapping_init();
1170 #endif
1171
1172 {
1173 unsigned long zones_size[MAX_NR_ZONES];
1174 unsigned long zholes_size[MAX_NR_ZONES];
1175 unsigned long npages;
1176 int znum;
1177
1178 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1179 zones_size[znum] = zholes_size[znum] = 0;
1180
1181 npages = end_pfn - pfn_base;
1182 zones_size[ZONE_DMA] = npages;
1183 zholes_size[ZONE_DMA] = npages - pages_avail;
1184
1185 free_area_init_node(0, &contig_page_data, zones_size,
1186 phys_base >> PAGE_SHIFT, zholes_size);
1187 }
1188
1189 device_scan();
1190 }
1191
1192 static void __init taint_real_pages(void)
1193 {
1194 int i;
1195
1196 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1197
1198 /* Find changes discovered in the physmem available rescan and
1199 * reserve the lost portions in the bootmem maps.
1200 */
1201 for (i = 0; i < pavail_ents; i++) {
1202 unsigned long old_start, old_end;
1203
1204 old_start = pavail[i].phys_addr;
1205 old_end = old_start +
1206 pavail[i].reg_size;
1207 while (old_start < old_end) {
1208 int n;
1209
1210 for (n = 0; pavail_rescan_ents; n++) {
1211 unsigned long new_start, new_end;
1212
1213 new_start = pavail_rescan[n].phys_addr;
1214 new_end = new_start +
1215 pavail_rescan[n].reg_size;
1216
1217 if (new_start <= old_start &&
1218 new_end >= (old_start + PAGE_SIZE)) {
1219 set_bit(old_start >> 22,
1220 sparc64_valid_addr_bitmap);
1221 goto do_next_page;
1222 }
1223 }
1224 reserve_bootmem(old_start, PAGE_SIZE);
1225
1226 do_next_page:
1227 old_start += PAGE_SIZE;
1228 }
1229 }
1230 }
1231
1232 void __init mem_init(void)
1233 {
1234 unsigned long codepages, datapages, initpages;
1235 unsigned long addr, last;
1236 int i;
1237
1238 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1239 i += 1;
1240 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1241 if (sparc64_valid_addr_bitmap == NULL) {
1242 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1243 prom_halt();
1244 }
1245 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1246
1247 addr = PAGE_OFFSET + kern_base;
1248 last = PAGE_ALIGN(kern_size) + addr;
1249 while (addr < last) {
1250 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1251 addr += PAGE_SIZE;
1252 }
1253
1254 taint_real_pages();
1255
1256 max_mapnr = last_valid_pfn - pfn_base;
1257 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1258
1259 #ifdef CONFIG_DEBUG_BOOTMEM
1260 prom_printf("mem_init: Calling free_all_bootmem().\n");
1261 #endif
1262 totalram_pages = num_physpages = free_all_bootmem() - 1;
1263
1264 /*
1265 * Set up the zero page, mark it reserved, so that page count
1266 * is not manipulated when freeing the page from user ptes.
1267 */
1268 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1269 if (mem_map_zero == NULL) {
1270 prom_printf("paging_init: Cannot alloc zero page.\n");
1271 prom_halt();
1272 }
1273 SetPageReserved(mem_map_zero);
1274
1275 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1276 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1277 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1278 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1279 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1280 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1281
1282 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1283 nr_free_pages() << (PAGE_SHIFT-10),
1284 codepages << (PAGE_SHIFT-10),
1285 datapages << (PAGE_SHIFT-10),
1286 initpages << (PAGE_SHIFT-10),
1287 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1288
1289 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1290 cheetah_ecache_flush_init();
1291 }
1292
1293 void free_initmem(void)
1294 {
1295 unsigned long addr, initend;
1296
1297 /*
1298 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1299 */
1300 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1301 initend = (unsigned long)(__init_end) & PAGE_MASK;
1302 for (; addr < initend; addr += PAGE_SIZE) {
1303 unsigned long page;
1304 struct page *p;
1305
1306 page = (addr +
1307 ((unsigned long) __va(kern_base)) -
1308 ((unsigned long) KERNBASE));
1309 memset((void *)addr, 0xcc, PAGE_SIZE);
1310 p = virt_to_page(page);
1311
1312 ClearPageReserved(p);
1313 set_page_count(p, 1);
1314 __free_page(p);
1315 num_physpages++;
1316 totalram_pages++;
1317 }
1318 }
1319
1320 #ifdef CONFIG_BLK_DEV_INITRD
1321 void free_initrd_mem(unsigned long start, unsigned long end)
1322 {
1323 if (start < end)
1324 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1325 for (; start < end; start += PAGE_SIZE) {
1326 struct page *p = virt_to_page(start);
1327
1328 ClearPageReserved(p);
1329 set_page_count(p, 1);
1330 __free_page(p);
1331 num_physpages++;
1332 totalram_pages++;
1333 }
1334 }
1335 #endif
1336
1337 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1338 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1339 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1340 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1341 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1342 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1343
1344 pgprot_t PAGE_KERNEL __read_mostly;
1345 EXPORT_SYMBOL(PAGE_KERNEL);
1346
1347 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1348 pgprot_t PAGE_COPY __read_mostly;
1349 pgprot_t PAGE_EXEC __read_mostly;
1350 unsigned long pg_iobits __read_mostly;
1351
1352 unsigned long _PAGE_IE __read_mostly;
1353 unsigned long _PAGE_E __read_mostly;
1354 unsigned long _PAGE_CACHE __read_mostly;
1355
1356 static void prot_init_common(unsigned long page_none,
1357 unsigned long page_shared,
1358 unsigned long page_copy,
1359 unsigned long page_readonly,
1360 unsigned long page_exec_bit)
1361 {
1362 PAGE_COPY = __pgprot(page_copy);
1363
1364 protection_map[0x0] = __pgprot(page_none);
1365 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1366 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1367 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1368 protection_map[0x4] = __pgprot(page_readonly);
1369 protection_map[0x5] = __pgprot(page_readonly);
1370 protection_map[0x6] = __pgprot(page_copy);
1371 protection_map[0x7] = __pgprot(page_copy);
1372 protection_map[0x8] = __pgprot(page_none);
1373 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1374 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1375 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1376 protection_map[0xc] = __pgprot(page_readonly);
1377 protection_map[0xd] = __pgprot(page_readonly);
1378 protection_map[0xe] = __pgprot(page_shared);
1379 protection_map[0xf] = __pgprot(page_shared);
1380 }
1381
1382 static void __init sun4u_pgprot_init(void)
1383 {
1384 unsigned long page_none, page_shared, page_copy, page_readonly;
1385 unsigned long page_exec_bit;
1386
1387 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1388 _PAGE_CACHE_4U | _PAGE_P_4U |
1389 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1390 _PAGE_EXEC_4U);
1391 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1392 _PAGE_CACHE_4U | _PAGE_P_4U |
1393 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1394 _PAGE_EXEC_4U | _PAGE_L_4U);
1395 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1396
1397 _PAGE_IE = _PAGE_IE_4U;
1398 _PAGE_E = _PAGE_E_4U;
1399 _PAGE_CACHE = _PAGE_CACHE_4U;
1400
1401 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1402 __ACCESS_BITS_4U | _PAGE_E_4U);
1403
1404 kern_linear_pte_xor = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1405 0xfffff80000000000;
1406 kern_linear_pte_xor |= (_PAGE_CP_4U | _PAGE_CV_4U |
1407 _PAGE_P_4U | _PAGE_W_4U);
1408
1409 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1410 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1411 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1412 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1413
1414
1415 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1416 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1417 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1418 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1419 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1420 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1421 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1422
1423 page_exec_bit = _PAGE_EXEC_4U;
1424
1425 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1426 page_exec_bit);
1427 }
1428
1429 static void __init sun4v_pgprot_init(void)
1430 {
1431 unsigned long page_none, page_shared, page_copy, page_readonly;
1432 unsigned long page_exec_bit;
1433
1434 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1435 _PAGE_CACHE_4V | _PAGE_P_4V |
1436 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1437 _PAGE_EXEC_4V);
1438 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1439 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1440
1441 _PAGE_IE = _PAGE_IE_4V;
1442 _PAGE_E = _PAGE_E_4V;
1443 _PAGE_CACHE = _PAGE_CACHE_4V;
1444
1445 kern_linear_pte_xor = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1446 0xfffff80000000000;
1447 kern_linear_pte_xor |= (_PAGE_CP_4V | _PAGE_CV_4V |
1448 _PAGE_P_4V | _PAGE_W_4V);
1449
1450 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1451 __ACCESS_BITS_4V | _PAGE_E_4V);
1452
1453 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1454 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1455 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1456 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1457 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1458
1459 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1460 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1461 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1462 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1463 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1464 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1465 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1466
1467 page_exec_bit = _PAGE_EXEC_4V;
1468
1469 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1470 page_exec_bit);
1471 }
1472
1473 unsigned long pte_sz_bits(unsigned long sz)
1474 {
1475 if (tlb_type == hypervisor) {
1476 switch (sz) {
1477 case 8 * 1024:
1478 default:
1479 return _PAGE_SZ8K_4V;
1480 case 64 * 1024:
1481 return _PAGE_SZ64K_4V;
1482 case 512 * 1024:
1483 return _PAGE_SZ512K_4V;
1484 case 4 * 1024 * 1024:
1485 return _PAGE_SZ4MB_4V;
1486 };
1487 } else {
1488 switch (sz) {
1489 case 8 * 1024:
1490 default:
1491 return _PAGE_SZ8K_4U;
1492 case 64 * 1024:
1493 return _PAGE_SZ64K_4U;
1494 case 512 * 1024:
1495 return _PAGE_SZ512K_4U;
1496 case 4 * 1024 * 1024:
1497 return _PAGE_SZ4MB_4U;
1498 };
1499 }
1500 }
1501
1502 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1503 {
1504 pte_t pte;
1505
1506 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1507 pte_val(pte) |= (((unsigned long)space) << 32);
1508 pte_val(pte) |= pte_sz_bits(page_size);
1509
1510 return pte;
1511 }
1512
1513 static unsigned long kern_large_tte(unsigned long paddr)
1514 {
1515 unsigned long val;
1516
1517 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1518 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1519 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1520 if (tlb_type == hypervisor)
1521 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1522 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1523 _PAGE_EXEC_4V | _PAGE_W_4V);
1524
1525 return val | paddr;
1526 }
1527
1528 /*
1529 * Translate PROM's mapping we capture at boot time into physical address.
1530 * The second parameter is only set from prom_callback() invocations.
1531 */
1532 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1533 {
1534 unsigned long mask;
1535 int i;
1536
1537 mask = _PAGE_PADDR_4U;
1538 if (tlb_type == hypervisor)
1539 mask = _PAGE_PADDR_4V;
1540
1541 for (i = 0; i < prom_trans_ents; i++) {
1542 struct linux_prom_translation *p = &prom_trans[i];
1543
1544 if (promva >= p->virt &&
1545 promva < (p->virt + p->size)) {
1546 unsigned long base = p->data & mask;
1547
1548 if (error)
1549 *error = 0;
1550 return base + (promva & (8192 - 1));
1551 }
1552 }
1553 if (error)
1554 *error = 1;
1555 return 0UL;
1556 }
1557
1558 /* XXX We should kill off this ugly thing at so me point. XXX */
1559 unsigned long sun4u_get_pte(unsigned long addr)
1560 {
1561 pgd_t *pgdp;
1562 pud_t *pudp;
1563 pmd_t *pmdp;
1564 pte_t *ptep;
1565 unsigned long mask = _PAGE_PADDR_4U;
1566
1567 if (tlb_type == hypervisor)
1568 mask = _PAGE_PADDR_4V;
1569
1570 if (addr >= PAGE_OFFSET)
1571 return addr & mask;
1572
1573 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1574 return prom_virt_to_phys(addr, NULL);
1575
1576 pgdp = pgd_offset_k(addr);
1577 pudp = pud_offset(pgdp, addr);
1578 pmdp = pmd_offset(pudp, addr);
1579 ptep = pte_offset_kernel(pmdp, addr);
1580
1581 return pte_val(*ptep) & mask;
1582 }
1583
1584 /* If not locked, zap it. */
1585 void __flush_tlb_all(void)
1586 {
1587 unsigned long pstate;
1588 int i;
1589
1590 __asm__ __volatile__("flushw\n\t"
1591 "rdpr %%pstate, %0\n\t"
1592 "wrpr %0, %1, %%pstate"
1593 : "=r" (pstate)
1594 : "i" (PSTATE_IE));
1595 if (tlb_type == spitfire) {
1596 for (i = 0; i < 64; i++) {
1597 /* Spitfire Errata #32 workaround */
1598 /* NOTE: Always runs on spitfire, so no
1599 * cheetah+ page size encodings.
1600 */
1601 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1602 "flush %%g6"
1603 : /* No outputs */
1604 : "r" (0),
1605 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1606
1607 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1608 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1609 "membar #Sync"
1610 : /* no outputs */
1611 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1612 spitfire_put_dtlb_data(i, 0x0UL);
1613 }
1614
1615 /* Spitfire Errata #32 workaround */
1616 /* NOTE: Always runs on spitfire, so no
1617 * cheetah+ page size encodings.
1618 */
1619 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1620 "flush %%g6"
1621 : /* No outputs */
1622 : "r" (0),
1623 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1624
1625 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1626 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1627 "membar #Sync"
1628 : /* no outputs */
1629 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1630 spitfire_put_itlb_data(i, 0x0UL);
1631 }
1632 }
1633 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1634 cheetah_flush_dtlb_all();
1635 cheetah_flush_itlb_all();
1636 }
1637 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1638 : : "r" (pstate));
1639 }
Linux kernel - Deliverables
This page took 0.088918 seconds and 5 git commands to generate.