arch/tile/include/asm/pci.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_PCI_H
  16 #define _ASM_TILE_PCI_H
  17
  18 #include <linux/dma-mapping.h>
  19 #include <linux/pci.h>
  20 #include <linux/numa.h>
  21 #include <asm-generic/pci_iomap.h>
  22
  23 #ifndef __tilegx__
  24
  25 /*
  26  * Structure of a PCI controller (host bridge)
  27  */
  28 struct pci_controller {
  29         int index;              /* PCI domain number */
  30         struct pci_bus *root_bus;
  31
  32         int first_busno;
  33         int last_busno;
  34
  35         int hv_cfg_fd[2];       /* config{0,1} fds for this PCIe controller */
  36         int hv_mem_fd;          /* fd to Hypervisor for MMIO operations */
  37
  38         struct pci_ops *ops;
  39
  40         int irq_base;           /* Base IRQ from the Hypervisor */
  41         int plx_gen1;           /* flag for PLX Gen 1 configuration */
  42
  43         /* Address ranges that are routed to this controller/bridge. */
  44         struct resource mem_resources[3];
  45 };
  46
  47 /*
  48  * This flag tells if the platform is TILEmpower that needs
  49  * special configuration for the PLX switch chip.
  50  */
  51 extern int tile_plx_gen1;
  52
  53 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
  54
  55 #define TILE_NUM_PCIE   2
  56
  57 /*
  58  * The hypervisor maps the entirety of CPA-space as bus addresses, so
  59  * bus addresses are physical addresses.  The networking and block
  60  * device layers use this boolean for bounce buffer decisions.
  61  */
  62 #define PCI_DMA_BUS_IS_PHYS     1
  63
  64 /* generic pci stuff */
  65 #include <asm-generic/pci.h>
  66
  67 #else
  68
  69 #include <asm/page.h>
  70 #include <gxio/trio.h>
  71
  72 /**
  73  * We reserve the hugepage-size address range at the top of the 64-bit address
  74  * space to serve as the PCI window, emulating the BAR0 space of an endpoint
  75  * device. This window is used by the chip-to-chip applications running on
  76  * the RC node. The reason for carving out this window is that Mem-Maps that
  77  * back up this window will not overlap with those that map the real physical
  78  * memory.
  79  */
  80 #define PCIE_HOST_BAR0_SIZE             HPAGE_SIZE
  81 #define PCIE_HOST_BAR0_START            HPAGE_MASK
  82
  83 /**
  84  * The first PAGE_SIZE of the above "BAR" window is mapped to the
  85  * gxpci_host_regs structure.
  86  */
  87 #define PCIE_HOST_REGS_SIZE             PAGE_SIZE
  88
  89 /*
  90  * This is the PCI address where the Mem-Map interrupt regions start.
  91  * We use the 2nd to the last huge page of the 64-bit address space.
  92  * The last huge page is used for the rootcomplex "bar", for C2C purpose.
  93  */
  94 #define MEM_MAP_INTR_REGIONS_BASE       (HPAGE_MASK - HPAGE_SIZE)
  95
  96 /*
  97  * Each Mem-Map interrupt region occupies 4KB.
  98  */
  99 #define MEM_MAP_INTR_REGION_SIZE        (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT)
 100
 101 /*
 102  * Allocate the PCI BAR window right below 4GB.
 103  */
 104 #define TILE_PCI_BAR_WINDOW_TOP         (1ULL << 32)
 105
 106 /*
 107  * Allocate 1GB for the PCI BAR window.
 108  */
 109 #define TILE_PCI_BAR_WINDOW_SIZE        (1 << 30)
 110
 111 /*
 112  * This is the highest bus address targeting the host memory that
 113  * can be generated by legacy PCI devices with 32-bit or less
 114  * DMA capability, dictated by the BAR window size and location.
 115  */
 116 #define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \
 117         (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1)
 118
 119 /*
 120  * We shift the PCI bus range for all the physical memory up by the whole PA
 121  * range. The corresponding CPA of an incoming PCI request will be the PCI
 122  * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies
 123  * that the 64-bit capable devices will be given DMA addresses as
 124  * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
 125  * devices, we create a separate map region that handles the low
 126  * 4GB.
 127  */
 128 #define TILE_PCI_MEM_MAP_BASE_OFFSET    (1ULL << CHIP_PA_WIDTH())
 129
 130 /*
 131  * End of the PCI memory resource.
 132  */
 133 #define TILE_PCI_MEM_END        \
 134                 ((1ULL << CHIP_PA_WIDTH()) + TILE_PCI_BAR_WINDOW_TOP)
 135
 136 /*
 137  * Start of the PCI memory resource.
 138  */
 139 #define TILE_PCI_MEM_START      (TILE_PCI_MEM_END - TILE_PCI_BAR_WINDOW_SIZE)
 140
 141 /*
 142  * Structure of a PCI controller (host bridge) on Gx.
 143  */
 144 struct pci_controller {
 145
 146         /* Pointer back to the TRIO that this PCIe port is connected to. */
 147         gxio_trio_context_t *trio;
 148         int mac;                /* PCIe mac index on the TRIO shim */
 149         int trio_index;         /* Index of TRIO shim that contains the MAC. */
 150
 151         int pio_mem_index;      /* PIO region index for memory access */
 152
 153         /*
 154          * Mem-Map regions for all the memory controllers so that Linux can
 155          * map all of its physical memory space to the PCI bus.
 156          */
 157         int mem_maps[MAX_NUMNODES];
 158
 159         int index;              /* PCI domain number */
 160         struct pci_bus *root_bus;
 161
 162         uint64_t mem_offset;    /* cpu->bus memory mapping offset. */
 163
 164         int last_busno;
 165
 166         struct pci_ops *ops;
 167
 168         /* Table that maps the INTx numbers to Linux irq numbers. */
 169         int irq_intx_table[4];
 170
 171         struct resource mem_space;
 172
 173         /* Address ranges that are routed to this controller/bridge. */
 174         struct resource mem_resources[3];
 175 };
 176
 177 extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
 178 extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
 179
 180 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 181
 182 extern void
 183 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 184                         struct resource *res);
 185
 186 extern void
 187 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 188                         struct pci_bus_region *region);
 189
 190 /*
 191  * The PCI address space does not equal the physical memory address
 192  * space (we have an IOMMU). The IDE and SCSI device layers use this
 193  * boolean for bounce buffer decisions.
 194  */
 195 #define PCI_DMA_BUS_IS_PHYS     0
 196
 197 #endif /* __tilegx__ */
 198
 199 int __init tile_pci_init(void);
 200 int __init pcibios_init(void);
 201
 202 void __devinit pcibios_fixup_bus(struct pci_bus *bus);
 203
 204 #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
 205
 206 /*
 207  * This decides whether to display the domain number in /proc.
 208  */
 209 static inline int pci_proc_domain(struct pci_bus *bus)
 210 {
 211         return 1;
 212 }
 213
 214 /*
 215  * pcibios_assign_all_busses() tells whether or not the bus numbers
 216  * should be reassigned, in case the BIOS didn't do it correctly, or
 217  * in case we don't have a BIOS and we want to let Linux do it.
 218  */
 219 static inline int pcibios_assign_all_busses(void)
 220 {
 221         return 1;
 222 }
 223
 224 #define PCIBIOS_MIN_MEM         0
 225 #define PCIBIOS_MIN_IO          0
 226
 227 /* Use any cpu for PCI. */
 228 #define cpumask_of_pcibus(bus) cpu_online_mask
 229
 230 /* implement the pci_ DMA API in terms of the generic device dma_ one */
 231 #include <asm-generic/pci-dma-compat.h>
 232
 233 #endif /* _ASM_TILE_PCI_H */