arch/tile/include/uapi/arch/opcode_tilegx.h

   1 /* TILE-Gx opcode information.
   2  *
   3  * Copyright 2011 Tilera Corporation. All Rights Reserved.
   4  *
   5  *   This program is free software; you can redistribute it and/or
   6  *   modify it under the terms of the GNU General Public License
   7  *   as published by the Free Software Foundation, version 2.
   8  *
   9  *   This program is distributed in the hope that it will be useful, but
  10  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *   NON INFRINGEMENT.  See the GNU General Public License for
  13  *   more details.
  14  *
  15  *
  16  *
  17  *
  18  *
  19  */
  20
  21 #ifndef __ARCH_OPCODE_H__
  22 #define __ARCH_OPCODE_H__
  23
  24 #ifndef __ASSEMBLER__
  25
  26 typedef unsigned long long tilegx_bundle_bits;
  27
  28 /* These are the bits that determine if a bundle is in the X encoding. */
  29 #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
  30
  31 enum
  32 {
  33   /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
  34   TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
  35
  36   /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
  37   TILEGX_NUM_PIPELINE_ENCODINGS = 5,
  38
  39   /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
  40   TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
  41
  42   /* Instructions take this many bytes. */
  43   TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
  44
  45   /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
  46   TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
  47
  48   /* Bundles should be aligned modulo this number of bytes. */
  49   TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
  50     (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
  51
  52   /* Number of registers (some are magic, such as network I/O). */
  53   TILEGX_NUM_REGISTERS = 64,
  54 };
  55
  56 /* Make a few "tile_" variables to simplify common code between
  57    architectures.  */
  58
  59 typedef tilegx_bundle_bits tile_bundle_bits;
  60 #define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
  61 #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
  62 #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
  63   TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
  64
  65 /* 64-bit pattern for a { bpt ; nop } bundle. */
  66 #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
  67
  68 static __inline unsigned int
  69 get_BFEnd_X0(tilegx_bundle_bits num)
  70 {
  71   const unsigned int n = (unsigned int)num;
  72   return (((n >> 12)) & 0x3f);
  73 }
  74
  75 static __inline unsigned int
  76 get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
  77 {
  78   const unsigned int n = (unsigned int)num;
  79   return (((n >> 24)) & 0xf);
  80 }
  81
  82 static __inline unsigned int
  83 get_BFStart_X0(tilegx_bundle_bits num)
  84 {
  85   const unsigned int n = (unsigned int)num;
  86   return (((n >> 18)) & 0x3f);
  87 }
  88
  89 static __inline unsigned int
  90 get_BrOff_X1(tilegx_bundle_bits n)
  91 {
  92   return (((unsigned int)(n >> 31)) & 0x0000003f) |
  93          (((unsigned int)(n >> 37)) & 0x0001ffc0);
  94 }
  95
  96 static __inline unsigned int
  97 get_BrType_X1(tilegx_bundle_bits n)
  98 {
  99   return (((unsigned int)(n >> 54)) & 0x1f);
 100 }
 101
 102 static __inline unsigned int
 103 get_Dest_Imm8_X1(tilegx_bundle_bits n)
 104 {
 105   return (((unsigned int)(n >> 31)) & 0x0000003f) |
 106          (((unsigned int)(n >> 43)) & 0x000000c0);
 107 }
 108
 109 static __inline unsigned int
 110 get_Dest_X0(tilegx_bundle_bits num)
 111 {
 112   const unsigned int n = (unsigned int)num;
 113   return (((n >> 0)) & 0x3f);
 114 }
 115
 116 static __inline unsigned int
 117 get_Dest_X1(tilegx_bundle_bits n)
 118 {
 119   return (((unsigned int)(n >> 31)) & 0x3f);
 120 }
 121
 122 static __inline unsigned int
 123 get_Dest_Y0(tilegx_bundle_bits num)
 124 {
 125   const unsigned int n = (unsigned int)num;
 126   return (((n >> 0)) & 0x3f);
 127 }
 128
 129 static __inline unsigned int
 130 get_Dest_Y1(tilegx_bundle_bits n)
 131 {
 132   return (((unsigned int)(n >> 31)) & 0x3f);
 133 }
 134
 135 static __inline unsigned int
 136 get_Imm16_X0(tilegx_bundle_bits num)
 137 {
 138   const unsigned int n = (unsigned int)num;
 139   return (((n >> 12)) & 0xffff);
 140 }
 141
 142 static __inline unsigned int
 143 get_Imm16_X1(tilegx_bundle_bits n)
 144 {
 145   return (((unsigned int)(n >> 43)) & 0xffff);
 146 }
 147
 148 static __inline unsigned int
 149 get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
 150 {
 151   const unsigned int n = (unsigned int)num;
 152   return (((n >> 20)) & 0xff);
 153 }
 154
 155 static __inline unsigned int
 156 get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
 157 {
 158   return (((unsigned int)(n >> 51)) & 0xff);
 159 }
 160
 161 static __inline unsigned int
 162 get_Imm8_X0(tilegx_bundle_bits num)
 163 {
 164   const unsigned int n = (unsigned int)num;
 165   return (((n >> 12)) & 0xff);
 166 }
 167
 168 static __inline unsigned int
 169 get_Imm8_X1(tilegx_bundle_bits n)
 170 {
 171   return (((unsigned int)(n >> 43)) & 0xff);
 172 }
 173
 174 static __inline unsigned int
 175 get_Imm8_Y0(tilegx_bundle_bits num)
 176 {
 177   const unsigned int n = (unsigned int)num;
 178   return (((n >> 12)) & 0xff);
 179 }
 180
 181 static __inline unsigned int
 182 get_Imm8_Y1(tilegx_bundle_bits n)
 183 {
 184   return (((unsigned int)(n >> 43)) & 0xff);
 185 }
 186
 187 static __inline unsigned int
 188 get_JumpOff_X1(tilegx_bundle_bits n)
 189 {
 190   return (((unsigned int)(n >> 31)) & 0x7ffffff);
 191 }
 192
 193 static __inline unsigned int
 194 get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
 195 {
 196   return (((unsigned int)(n >> 58)) & 0x1);
 197 }
 198
 199 static __inline unsigned int
 200 get_MF_Imm14_X1(tilegx_bundle_bits n)
 201 {
 202   return (((unsigned int)(n >> 37)) & 0x3fff);
 203 }
 204
 205 static __inline unsigned int
 206 get_MT_Imm14_X1(tilegx_bundle_bits n)
 207 {
 208   return (((unsigned int)(n >> 31)) & 0x0000003f) |
 209          (((unsigned int)(n >> 37)) & 0x00003fc0);
 210 }
 211
 212 static __inline unsigned int
 213 get_Mode(tilegx_bundle_bits n)
 214 {
 215   return (((unsigned int)(n >> 62)) & 0x3);
 216 }
 217
 218 static __inline unsigned int
 219 get_Opcode_X0(tilegx_bundle_bits num)
 220 {
 221   const unsigned int n = (unsigned int)num;
 222   return (((n >> 28)) & 0x7);
 223 }
 224
 225 static __inline unsigned int
 226 get_Opcode_X1(tilegx_bundle_bits n)
 227 {
 228   return (((unsigned int)(n >> 59)) & 0x7);
 229 }
 230
 231 static __inline unsigned int
 232 get_Opcode_Y0(tilegx_bundle_bits num)
 233 {
 234   const unsigned int n = (unsigned int)num;
 235   return (((n >> 27)) & 0xf);
 236 }
 237
 238 static __inline unsigned int
 239 get_Opcode_Y1(tilegx_bundle_bits n)
 240 {
 241   return (((unsigned int)(n >> 58)) & 0xf);
 242 }
 243
 244 static __inline unsigned int
 245 get_Opcode_Y2(tilegx_bundle_bits n)
 246 {
 247   return (((n >> 26)) & 0x00000001) |
 248          (((unsigned int)(n >> 56)) & 0x00000002);
 249 }
 250
 251 static __inline unsigned int
 252 get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
 253 {
 254   const unsigned int n = (unsigned int)num;
 255   return (((n >> 18)) & 0x3ff);
 256 }
 257
 258 static __inline unsigned int
 259 get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
 260 {
 261   return (((unsigned int)(n >> 49)) & 0x3ff);
 262 }
 263
 264 static __inline unsigned int
 265 get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
 266 {
 267   const unsigned int n = (unsigned int)num;
 268   return (((n >> 18)) & 0x3);
 269 }
 270
 271 static __inline unsigned int
 272 get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
 273 {
 274   return (((unsigned int)(n >> 49)) & 0x3);
 275 }
 276
 277 static __inline unsigned int
 278 get_ShAmt_X0(tilegx_bundle_bits num)
 279 {
 280   const unsigned int n = (unsigned int)num;
 281   return (((n >> 12)) & 0x3f);
 282 }
 283
 284 static __inline unsigned int
 285 get_ShAmt_X1(tilegx_bundle_bits n)
 286 {
 287   return (((unsigned int)(n >> 43)) & 0x3f);
 288 }
 289
 290 static __inline unsigned int
 291 get_ShAmt_Y0(tilegx_bundle_bits num)
 292 {
 293   const unsigned int n = (unsigned int)num;
 294   return (((n >> 12)) & 0x3f);
 295 }
 296
 297 static __inline unsigned int
 298 get_ShAmt_Y1(tilegx_bundle_bits n)
 299 {
 300   return (((unsigned int)(n >> 43)) & 0x3f);
 301 }
 302
 303 static __inline unsigned int
 304 get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
 305 {
 306   const unsigned int n = (unsigned int)num;
 307   return (((n >> 18)) & 0x3ff);
 308 }
 309
 310 static __inline unsigned int
 311 get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
 312 {
 313   return (((unsigned int)(n >> 49)) & 0x3ff);
 314 }
 315
 316 static __inline unsigned int
 317 get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
 318 {
 319   const unsigned int n = (unsigned int)num;
 320   return (((n >> 18)) & 0x3);
 321 }
 322
 323 static __inline unsigned int
 324 get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
 325 {
 326   return (((unsigned int)(n >> 49)) & 0x3);
 327 }
 328
 329 static __inline unsigned int
 330 get_SrcA_X0(tilegx_bundle_bits num)
 331 {
 332   const unsigned int n = (unsigned int)num;
 333   return (((n >> 6)) & 0x3f);
 334 }
 335
 336 static __inline unsigned int
 337 get_SrcA_X1(tilegx_bundle_bits n)
 338 {
 339   return (((unsigned int)(n >> 37)) & 0x3f);
 340 }
 341
 342 static __inline unsigned int
 343 get_SrcA_Y0(tilegx_bundle_bits num)
 344 {
 345   const unsigned int n = (unsigned int)num;
 346   return (((n >> 6)) & 0x3f);
 347 }
 348
 349 static __inline unsigned int
 350 get_SrcA_Y1(tilegx_bundle_bits n)
 351 {
 352   return (((unsigned int)(n >> 37)) & 0x3f);
 353 }
 354
 355 static __inline unsigned int
 356 get_SrcA_Y2(tilegx_bundle_bits num)
 357 {
 358   const unsigned int n = (unsigned int)num;
 359   return (((n >> 20)) & 0x3f);
 360 }
 361
 362 static __inline unsigned int
 363 get_SrcBDest_Y2(tilegx_bundle_bits n)
 364 {
 365   return (((unsigned int)(n >> 51)) & 0x3f);
 366 }
 367
 368 static __inline unsigned int
 369 get_SrcB_X0(tilegx_bundle_bits num)
 370 {
 371   const unsigned int n = (unsigned int)num;
 372   return (((n >> 12)) & 0x3f);
 373 }
 374
 375 static __inline unsigned int
 376 get_SrcB_X1(tilegx_bundle_bits n)
 377 {
 378   return (((unsigned int)(n >> 43)) & 0x3f);
 379 }
 380
 381 static __inline unsigned int
 382 get_SrcB_Y0(tilegx_bundle_bits num)
 383 {
 384   const unsigned int n = (unsigned int)num;
 385   return (((n >> 12)) & 0x3f);
 386 }
 387
 388 static __inline unsigned int
 389 get_SrcB_Y1(tilegx_bundle_bits n)
 390 {
 391   return (((unsigned int)(n >> 43)) & 0x3f);
 392 }
 393
 394 static __inline unsigned int
 395 get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
 396 {
 397   const unsigned int n = (unsigned int)num;
 398   return (((n >> 12)) & 0x3f);
 399 }
 400
 401 static __inline unsigned int
 402 get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
 403 {
 404   return (((unsigned int)(n >> 43)) & 0x3f);
 405 }
 406
 407 static __inline unsigned int
 408 get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
 409 {
 410   const unsigned int n = (unsigned int)num;
 411   return (((n >> 12)) & 0x3f);
 412 }
 413
 414 static __inline unsigned int
 415 get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
 416 {
 417   return (((unsigned int)(n >> 43)) & 0x3f);
 418 }
 419
 420
 421 static __inline int
 422 sign_extend(int n, int num_bits)
 423 {
 424   int shift = (int)(sizeof(int) * 8 - num_bits);
 425   return (n << shift) >> shift;
 426 }
 427
 428
 429
 430 static __inline tilegx_bundle_bits
 431 create_BFEnd_X0(int num)
 432 {
 433   const unsigned int n = (unsigned int)num;
 434   return ((n & 0x3f) << 12);
 435 }
 436
 437 static __inline tilegx_bundle_bits
 438 create_BFOpcodeExtension_X0(int num)
 439 {
 440   const unsigned int n = (unsigned int)num;
 441   return ((n & 0xf) << 24);
 442 }
 443
 444 static __inline tilegx_bundle_bits
 445 create_BFStart_X0(int num)
 446 {
 447   const unsigned int n = (unsigned int)num;
 448   return ((n & 0x3f) << 18);
 449 }
 450
 451 static __inline tilegx_bundle_bits
 452 create_BrOff_X1(int num)
 453 {
 454   const unsigned int n = (unsigned int)num;
 455   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
 456          (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
 457 }
 458
 459 static __inline tilegx_bundle_bits
 460 create_BrType_X1(int num)
 461 {
 462   const unsigned int n = (unsigned int)num;
 463   return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
 464 }
 465
 466 static __inline tilegx_bundle_bits
 467 create_Dest_Imm8_X1(int num)
 468 {
 469   const unsigned int n = (unsigned int)num;
 470   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
 471          (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
 472 }
 473
 474 static __inline tilegx_bundle_bits
 475 create_Dest_X0(int num)
 476 {
 477   const unsigned int n = (unsigned int)num;
 478   return ((n & 0x3f) << 0);
 479 }
 480
 481 static __inline tilegx_bundle_bits
 482 create_Dest_X1(int num)
 483 {
 484   const unsigned int n = (unsigned int)num;
 485   return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
 486 }
 487
 488 static __inline tilegx_bundle_bits
 489 create_Dest_Y0(int num)
 490 {
 491   const unsigned int n = (unsigned int)num;
 492   return ((n & 0x3f) << 0);
 493 }
 494
 495 static __inline tilegx_bundle_bits
 496 create_Dest_Y1(int num)
 497 {
 498   const unsigned int n = (unsigned int)num;
 499   return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
 500 }
 501
 502 static __inline tilegx_bundle_bits
 503 create_Imm16_X0(int num)
 504 {
 505   const unsigned int n = (unsigned int)num;
 506   return ((n & 0xffff) << 12);
 507 }
 508
 509 static __inline tilegx_bundle_bits
 510 create_Imm16_X1(int num)
 511 {
 512   const unsigned int n = (unsigned int)num;
 513   return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
 514 }
 515
 516 static __inline tilegx_bundle_bits
 517 create_Imm8OpcodeExtension_X0(int num)
 518 {
 519   const unsigned int n = (unsigned int)num;
 520   return ((n & 0xff) << 20);
 521 }
 522
 523 static __inline tilegx_bundle_bits
 524 create_Imm8OpcodeExtension_X1(int num)
 525 {
 526   const unsigned int n = (unsigned int)num;
 527   return (((tilegx_bundle_bits)(n & 0xff)) << 51);
 528 }
 529
 530 static __inline tilegx_bundle_bits
 531 create_Imm8_X0(int num)
 532 {
 533   const unsigned int n = (unsigned int)num;
 534   return ((n & 0xff) << 12);
 535 }
 536
 537 static __inline tilegx_bundle_bits
 538 create_Imm8_X1(int num)
 539 {
 540   const unsigned int n = (unsigned int)num;
 541   return (((tilegx_bundle_bits)(n & 0xff)) << 43);
 542 }
 543
 544 static __inline tilegx_bundle_bits
 545 create_Imm8_Y0(int num)
 546 {
 547   const unsigned int n = (unsigned int)num;
 548   return ((n & 0xff) << 12);
 549 }
 550
 551 static __inline tilegx_bundle_bits
 552 create_Imm8_Y1(int num)
 553 {
 554   const unsigned int n = (unsigned int)num;
 555   return (((tilegx_bundle_bits)(n & 0xff)) << 43);
 556 }
 557
 558 static __inline tilegx_bundle_bits
 559 create_JumpOff_X1(int num)
 560 {
 561   const unsigned int n = (unsigned int)num;
 562   return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
 563 }
 564
 565 static __inline tilegx_bundle_bits
 566 create_JumpOpcodeExtension_X1(int num)
 567 {
 568   const unsigned int n = (unsigned int)num;
 569   return (((tilegx_bundle_bits)(n & 0x1)) << 58);
 570 }
 571
 572 static __inline tilegx_bundle_bits
 573 create_MF_Imm14_X1(int num)
 574 {
 575   const unsigned int n = (unsigned int)num;
 576   return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
 577 }
 578
 579 static __inline tilegx_bundle_bits
 580 create_MT_Imm14_X1(int num)
 581 {
 582   const unsigned int n = (unsigned int)num;
 583   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
 584          (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
 585 }
 586
 587 static __inline tilegx_bundle_bits
 588 create_Mode(int num)
 589 {
 590   const unsigned int n = (unsigned int)num;
 591   return (((tilegx_bundle_bits)(n & 0x3)) << 62);
 592 }
 593
 594 static __inline tilegx_bundle_bits
 595 create_Opcode_X0(int num)
 596 {
 597   const unsigned int n = (unsigned int)num;
 598   return ((n & 0x7) << 28);
 599 }
 600
 601 static __inline tilegx_bundle_bits
 602 create_Opcode_X1(int num)
 603 {
 604   const unsigned int n = (unsigned int)num;
 605   return (((tilegx_bundle_bits)(n & 0x7)) << 59);
 606 }
 607
 608 static __inline tilegx_bundle_bits
 609 create_Opcode_Y0(int num)
 610 {
 611   const unsigned int n = (unsigned int)num;
 612   return ((n & 0xf) << 27);
 613 }
 614
 615 static __inline tilegx_bundle_bits
 616 create_Opcode_Y1(int num)
 617 {
 618   const unsigned int n = (unsigned int)num;
 619   return (((tilegx_bundle_bits)(n & 0xf)) << 58);
 620 }
 621
 622 static __inline tilegx_bundle_bits
 623 create_Opcode_Y2(int num)
 624 {
 625   const unsigned int n = (unsigned int)num;
 626   return ((n & 0x00000001) << 26) |
 627          (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
 628 }
 629
 630 static __inline tilegx_bundle_bits
 631 create_RRROpcodeExtension_X0(int num)
 632 {
 633   const unsigned int n = (unsigned int)num;
 634   return ((n & 0x3ff) << 18);
 635 }
 636
 637 static __inline tilegx_bundle_bits
 638 create_RRROpcodeExtension_X1(int num)
 639 {
 640   const unsigned int n = (unsigned int)num;
 641   return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
 642 }
 643
 644 static __inline tilegx_bundle_bits
 645 create_RRROpcodeExtension_Y0(int num)
 646 {
 647   const unsigned int n = (unsigned int)num;
 648   return ((n & 0x3) << 18);
 649 }
 650
 651 static __inline tilegx_bundle_bits
 652 create_RRROpcodeExtension_Y1(int num)
 653 {
 654   const unsigned int n = (unsigned int)num;
 655   return (((tilegx_bundle_bits)(n & 0x3)) << 49);
 656 }
 657
 658 static __inline tilegx_bundle_bits
 659 create_ShAmt_X0(int num)
 660 {
 661   const unsigned int n = (unsigned int)num;
 662   return ((n & 0x3f) << 12);
 663 }
 664
 665 static __inline tilegx_bundle_bits
 666 create_ShAmt_X1(int num)
 667 {
 668   const unsigned int n = (unsigned int)num;
 669   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 670 }
 671
 672 static __inline tilegx_bundle_bits
 673 create_ShAmt_Y0(int num)
 674 {
 675   const unsigned int n = (unsigned int)num;
 676   return ((n & 0x3f) << 12);
 677 }
 678
 679 static __inline tilegx_bundle_bits
 680 create_ShAmt_Y1(int num)
 681 {
 682   const unsigned int n = (unsigned int)num;
 683   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 684 }
 685
 686 static __inline tilegx_bundle_bits
 687 create_ShiftOpcodeExtension_X0(int num)
 688 {
 689   const unsigned int n = (unsigned int)num;
 690   return ((n & 0x3ff) << 18);
 691 }
 692
 693 static __inline tilegx_bundle_bits
 694 create_ShiftOpcodeExtension_X1(int num)
 695 {
 696   const unsigned int n = (unsigned int)num;
 697   return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
 698 }
 699
 700 static __inline tilegx_bundle_bits
 701 create_ShiftOpcodeExtension_Y0(int num)
 702 {
 703   const unsigned int n = (unsigned int)num;
 704   return ((n & 0x3) << 18);
 705 }
 706
 707 static __inline tilegx_bundle_bits
 708 create_ShiftOpcodeExtension_Y1(int num)
 709 {
 710   const unsigned int n = (unsigned int)num;
 711   return (((tilegx_bundle_bits)(n & 0x3)) << 49);
 712 }
 713
 714 static __inline tilegx_bundle_bits
 715 create_SrcA_X0(int num)
 716 {
 717   const unsigned int n = (unsigned int)num;
 718   return ((n & 0x3f) << 6);
 719 }
 720
 721 static __inline tilegx_bundle_bits
 722 create_SrcA_X1(int num)
 723 {
 724   const unsigned int n = (unsigned int)num;
 725   return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
 726 }
 727
 728 static __inline tilegx_bundle_bits
 729 create_SrcA_Y0(int num)
 730 {
 731   const unsigned int n = (unsigned int)num;
 732   return ((n & 0x3f) << 6);
 733 }
 734
 735 static __inline tilegx_bundle_bits
 736 create_SrcA_Y1(int num)
 737 {
 738   const unsigned int n = (unsigned int)num;
 739   return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
 740 }
 741
 742 static __inline tilegx_bundle_bits
 743 create_SrcA_Y2(int num)
 744 {
 745   const unsigned int n = (unsigned int)num;
 746   return ((n & 0x3f) << 20);
 747 }
 748
 749 static __inline tilegx_bundle_bits
 750 create_SrcBDest_Y2(int num)
 751 {
 752   const unsigned int n = (unsigned int)num;
 753   return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
 754 }
 755
 756 static __inline tilegx_bundle_bits
 757 create_SrcB_X0(int num)
 758 {
 759   const unsigned int n = (unsigned int)num;
 760   return ((n & 0x3f) << 12);
 761 }
 762
 763 static __inline tilegx_bundle_bits
 764 create_SrcB_X1(int num)
 765 {
 766   const unsigned int n = (unsigned int)num;
 767   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 768 }
 769
 770 static __inline tilegx_bundle_bits
 771 create_SrcB_Y0(int num)
 772 {
 773   const unsigned int n = (unsigned int)num;
 774   return ((n & 0x3f) << 12);
 775 }
 776
 777 static __inline tilegx_bundle_bits
 778 create_SrcB_Y1(int num)
 779 {
 780   const unsigned int n = (unsigned int)num;
 781   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 782 }
 783
 784 static __inline tilegx_bundle_bits
 785 create_UnaryOpcodeExtension_X0(int num)
 786 {
 787   const unsigned int n = (unsigned int)num;
 788   return ((n & 0x3f) << 12);
 789 }
 790
 791 static __inline tilegx_bundle_bits
 792 create_UnaryOpcodeExtension_X1(int num)
 793 {
 794   const unsigned int n = (unsigned int)num;
 795   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 796 }
 797
 798 static __inline tilegx_bundle_bits
 799 create_UnaryOpcodeExtension_Y0(int num)
 800 {
 801   const unsigned int n = (unsigned int)num;
 802   return ((n & 0x3f) << 12);
 803 }
 804
 805 static __inline tilegx_bundle_bits
 806 create_UnaryOpcodeExtension_Y1(int num)
 807 {
 808   const unsigned int n = (unsigned int)num;
 809   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 810 }
 811
 812
 813 enum
 814 {
 815   ADDI_IMM8_OPCODE_X0 = 1,
 816   ADDI_IMM8_OPCODE_X1 = 1,
 817   ADDI_OPCODE_Y0 = 0,
 818   ADDI_OPCODE_Y1 = 1,
 819   ADDLI_OPCODE_X0 = 1,
 820   ADDLI_OPCODE_X1 = 0,
 821   ADDXI_IMM8_OPCODE_X0 = 2,
 822   ADDXI_IMM8_OPCODE_X1 = 2,
 823   ADDXI_OPCODE_Y0 = 1,
 824   ADDXI_OPCODE_Y1 = 2,
 825   ADDXLI_OPCODE_X0 = 2,
 826   ADDXLI_OPCODE_X1 = 1,
 827   ADDXSC_RRR_0_OPCODE_X0 = 1,
 828   ADDXSC_RRR_0_OPCODE_X1 = 1,
 829   ADDX_RRR_0_OPCODE_X0 = 2,
 830   ADDX_RRR_0_OPCODE_X1 = 2,
 831   ADDX_RRR_0_OPCODE_Y0 = 0,
 832   ADDX_SPECIAL_0_OPCODE_Y1 = 0,
 833   ADD_RRR_0_OPCODE_X0 = 3,
 834   ADD_RRR_0_OPCODE_X1 = 3,
 835   ADD_RRR_0_OPCODE_Y0 = 1,
 836   ADD_SPECIAL_0_OPCODE_Y1 = 1,
 837   ANDI_IMM8_OPCODE_X0 = 3,
 838   ANDI_IMM8_OPCODE_X1 = 3,
 839   ANDI_OPCODE_Y0 = 2,
 840   ANDI_OPCODE_Y1 = 3,
 841   AND_RRR_0_OPCODE_X0 = 4,
 842   AND_RRR_0_OPCODE_X1 = 4,
 843   AND_RRR_5_OPCODE_Y0 = 0,
 844   AND_RRR_5_OPCODE_Y1 = 0,
 845   BEQZT_BRANCH_OPCODE_X1 = 16,
 846   BEQZ_BRANCH_OPCODE_X1 = 17,
 847   BFEXTS_BF_OPCODE_X0 = 4,
 848   BFEXTU_BF_OPCODE_X0 = 5,
 849   BFINS_BF_OPCODE_X0 = 6,
 850   BF_OPCODE_X0 = 3,
 851   BGEZT_BRANCH_OPCODE_X1 = 18,
 852   BGEZ_BRANCH_OPCODE_X1 = 19,
 853   BGTZT_BRANCH_OPCODE_X1 = 20,
 854   BGTZ_BRANCH_OPCODE_X1 = 21,
 855   BLBCT_BRANCH_OPCODE_X1 = 22,
 856   BLBC_BRANCH_OPCODE_X1 = 23,
 857   BLBST_BRANCH_OPCODE_X1 = 24,
 858   BLBS_BRANCH_OPCODE_X1 = 25,
 859   BLEZT_BRANCH_OPCODE_X1 = 26,
 860   BLEZ_BRANCH_OPCODE_X1 = 27,
 861   BLTZT_BRANCH_OPCODE_X1 = 28,
 862   BLTZ_BRANCH_OPCODE_X1 = 29,
 863   BNEZT_BRANCH_OPCODE_X1 = 30,
 864   BNEZ_BRANCH_OPCODE_X1 = 31,
 865   BRANCH_OPCODE_X1 = 2,
 866   CMOVEQZ_RRR_0_OPCODE_X0 = 5,
 867   CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
 868   CMOVNEZ_RRR_0_OPCODE_X0 = 6,
 869   CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
 870   CMPEQI_IMM8_OPCODE_X0 = 4,
 871   CMPEQI_IMM8_OPCODE_X1 = 4,
 872   CMPEQI_OPCODE_Y0 = 3,
 873   CMPEQI_OPCODE_Y1 = 4,
 874   CMPEQ_RRR_0_OPCODE_X0 = 7,
 875   CMPEQ_RRR_0_OPCODE_X1 = 5,
 876   CMPEQ_RRR_3_OPCODE_Y0 = 0,
 877   CMPEQ_RRR_3_OPCODE_Y1 = 2,
 878   CMPEXCH4_RRR_0_OPCODE_X1 = 6,
 879   CMPEXCH_RRR_0_OPCODE_X1 = 7,
 880   CMPLES_RRR_0_OPCODE_X0 = 8,
 881   CMPLES_RRR_0_OPCODE_X1 = 8,
 882   CMPLES_RRR_2_OPCODE_Y0 = 0,
 883   CMPLES_RRR_2_OPCODE_Y1 = 0,
 884   CMPLEU_RRR_0_OPCODE_X0 = 9,
 885   CMPLEU_RRR_0_OPCODE_X1 = 9,
 886   CMPLEU_RRR_2_OPCODE_Y0 = 1,
 887   CMPLEU_RRR_2_OPCODE_Y1 = 1,
 888   CMPLTSI_IMM8_OPCODE_X0 = 5,
 889   CMPLTSI_IMM8_OPCODE_X1 = 5,
 890   CMPLTSI_OPCODE_Y0 = 4,
 891   CMPLTSI_OPCODE_Y1 = 5,
 892   CMPLTS_RRR_0_OPCODE_X0 = 10,
 893   CMPLTS_RRR_0_OPCODE_X1 = 10,
 894   CMPLTS_RRR_2_OPCODE_Y0 = 2,
 895   CMPLTS_RRR_2_OPCODE_Y1 = 2,
 896   CMPLTUI_IMM8_OPCODE_X0 = 6,
 897   CMPLTUI_IMM8_OPCODE_X1 = 6,
 898   CMPLTU_RRR_0_OPCODE_X0 = 11,
 899   CMPLTU_RRR_0_OPCODE_X1 = 11,
 900   CMPLTU_RRR_2_OPCODE_Y0 = 3,
 901   CMPLTU_RRR_2_OPCODE_Y1 = 3,
 902   CMPNE_RRR_0_OPCODE_X0 = 12,
 903   CMPNE_RRR_0_OPCODE_X1 = 12,
 904   CMPNE_RRR_3_OPCODE_Y0 = 1,
 905   CMPNE_RRR_3_OPCODE_Y1 = 3,
 906   CMULAF_RRR_0_OPCODE_X0 = 13,
 907   CMULA_RRR_0_OPCODE_X0 = 14,
 908   CMULFR_RRR_0_OPCODE_X0 = 15,
 909   CMULF_RRR_0_OPCODE_X0 = 16,
 910   CMULHR_RRR_0_OPCODE_X0 = 17,
 911   CMULH_RRR_0_OPCODE_X0 = 18,
 912   CMUL_RRR_0_OPCODE_X0 = 19,
 913   CNTLZ_UNARY_OPCODE_X0 = 1,
 914   CNTLZ_UNARY_OPCODE_Y0 = 1,
 915   CNTTZ_UNARY_OPCODE_X0 = 2,
 916   CNTTZ_UNARY_OPCODE_Y0 = 2,
 917   CRC32_32_RRR_0_OPCODE_X0 = 20,
 918   CRC32_8_RRR_0_OPCODE_X0 = 21,
 919   DBLALIGN2_RRR_0_OPCODE_X0 = 22,
 920   DBLALIGN2_RRR_0_OPCODE_X1 = 13,
 921   DBLALIGN4_RRR_0_OPCODE_X0 = 23,
 922   DBLALIGN4_RRR_0_OPCODE_X1 = 14,
 923   DBLALIGN6_RRR_0_OPCODE_X0 = 24,
 924   DBLALIGN6_RRR_0_OPCODE_X1 = 15,
 925   DBLALIGN_RRR_0_OPCODE_X0 = 25,
 926   DRAIN_UNARY_OPCODE_X1 = 1,
 927   DTLBPR_UNARY_OPCODE_X1 = 2,
 928   EXCH4_RRR_0_OPCODE_X1 = 16,
 929   EXCH_RRR_0_OPCODE_X1 = 17,
 930   FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
 931   FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
 932   FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
 933   FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
 934   FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
 935   FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
 936   FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
 937   FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
 938   FETCHADD4_RRR_0_OPCODE_X1 = 18,
 939   FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
 940   FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
 941   FETCHADD_RRR_0_OPCODE_X1 = 21,
 942   FETCHAND4_RRR_0_OPCODE_X1 = 22,
 943   FETCHAND_RRR_0_OPCODE_X1 = 23,
 944   FETCHOR4_RRR_0_OPCODE_X1 = 24,
 945   FETCHOR_RRR_0_OPCODE_X1 = 25,
 946   FINV_UNARY_OPCODE_X1 = 3,
 947   FLUSHWB_UNARY_OPCODE_X1 = 4,
 948   FLUSH_UNARY_OPCODE_X1 = 5,
 949   FNOP_UNARY_OPCODE_X0 = 3,
 950   FNOP_UNARY_OPCODE_X1 = 6,
 951   FNOP_UNARY_OPCODE_Y0 = 3,
 952   FNOP_UNARY_OPCODE_Y1 = 8,
 953   FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
 954   FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
 955   FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
 956   FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
 957   FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
 958   FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
 959   FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
 960   FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
 961   ICOH_UNARY_OPCODE_X1 = 7,
 962   ILL_UNARY_OPCODE_X1 = 8,
 963   ILL_UNARY_OPCODE_Y1 = 9,
 964   IMM8_OPCODE_X0 = 4,
 965   IMM8_OPCODE_X1 = 3,
 966   INV_UNARY_OPCODE_X1 = 9,
 967   IRET_UNARY_OPCODE_X1 = 10,
 968   JALRP_UNARY_OPCODE_X1 = 11,
 969   JALRP_UNARY_OPCODE_Y1 = 10,
 970   JALR_UNARY_OPCODE_X1 = 12,
 971   JALR_UNARY_OPCODE_Y1 = 11,
 972   JAL_JUMP_OPCODE_X1 = 0,
 973   JRP_UNARY_OPCODE_X1 = 13,
 974   JRP_UNARY_OPCODE_Y1 = 12,
 975   JR_UNARY_OPCODE_X1 = 14,
 976   JR_UNARY_OPCODE_Y1 = 13,
 977   JUMP_OPCODE_X1 = 4,
 978   J_JUMP_OPCODE_X1 = 1,
 979   LD1S_ADD_IMM8_OPCODE_X1 = 7,
 980   LD1S_OPCODE_Y2 = 0,
 981   LD1S_UNARY_OPCODE_X1 = 15,
 982   LD1U_ADD_IMM8_OPCODE_X1 = 8,
 983   LD1U_OPCODE_Y2 = 1,
 984   LD1U_UNARY_OPCODE_X1 = 16,
 985   LD2S_ADD_IMM8_OPCODE_X1 = 9,
 986   LD2S_OPCODE_Y2 = 2,
 987   LD2S_UNARY_OPCODE_X1 = 17,
 988   LD2U_ADD_IMM8_OPCODE_X1 = 10,
 989   LD2U_OPCODE_Y2 = 3,
 990   LD2U_UNARY_OPCODE_X1 = 18,
 991   LD4S_ADD_IMM8_OPCODE_X1 = 11,
 992   LD4S_OPCODE_Y2 = 1,
 993   LD4S_UNARY_OPCODE_X1 = 19,
 994   LD4U_ADD_IMM8_OPCODE_X1 = 12,
 995   LD4U_OPCODE_Y2 = 2,
 996   LD4U_UNARY_OPCODE_X1 = 20,
 997   LDNA_UNARY_OPCODE_X1 = 21,
 998   LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
 999   LDNT1S_UNARY_OPCODE_X1 = 22,
1000   LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
1001   LDNT1U_UNARY_OPCODE_X1 = 23,
1002   LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
1003   LDNT2S_UNARY_OPCODE_X1 = 24,
1004   LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
1005   LDNT2U_UNARY_OPCODE_X1 = 25,
1006   LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
1007   LDNT4S_UNARY_OPCODE_X1 = 26,
1008   LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
1009   LDNT4U_UNARY_OPCODE_X1 = 27,
1010   LDNT_ADD_IMM8_OPCODE_X1 = 19,
1011   LDNT_UNARY_OPCODE_X1 = 28,
1012   LD_ADD_IMM8_OPCODE_X1 = 20,
1013   LD_OPCODE_Y2 = 3,
1014   LD_UNARY_OPCODE_X1 = 29,
1015   LNK_UNARY_OPCODE_X1 = 30,
1016   LNK_UNARY_OPCODE_Y1 = 14,
1017   LWNA_ADD_IMM8_OPCODE_X1 = 21,
1018   MFSPR_IMM8_OPCODE_X1 = 22,
1019   MF_UNARY_OPCODE_X1 = 31,
1020   MM_BF_OPCODE_X0 = 7,
1021   MNZ_RRR_0_OPCODE_X0 = 40,
1022   MNZ_RRR_0_OPCODE_X1 = 26,
1023   MNZ_RRR_4_OPCODE_Y0 = 2,
1024   MNZ_RRR_4_OPCODE_Y1 = 2,
1025   MODE_OPCODE_YA2 = 1,
1026   MODE_OPCODE_YB2 = 2,
1027   MODE_OPCODE_YC2 = 3,
1028   MTSPR_IMM8_OPCODE_X1 = 23,
1029   MULAX_RRR_0_OPCODE_X0 = 41,
1030   MULAX_RRR_3_OPCODE_Y0 = 2,
1031   MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
1032   MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
1033   MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
1034   MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
1035   MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
1036   MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
1037   MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
1038   MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
1039   MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
1040   MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
1041   MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
1042   MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
1043   MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
1044   MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
1045   MULX_RRR_0_OPCODE_X0 = 52,
1046   MULX_RRR_3_OPCODE_Y0 = 3,
1047   MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
1048   MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
1049   MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
1050   MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
1051   MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
1052   MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
1053   MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
1054   MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
1055   MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
1056   MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
1057   MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
1058   MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
1059   MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
1060   MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
1061   MZ_RRR_0_OPCODE_X0 = 63,
1062   MZ_RRR_0_OPCODE_X1 = 27,
1063   MZ_RRR_4_OPCODE_Y0 = 3,
1064   MZ_RRR_4_OPCODE_Y1 = 3,
1065   NAP_UNARY_OPCODE_X1 = 32,
1066   NOP_UNARY_OPCODE_X0 = 5,
1067   NOP_UNARY_OPCODE_X1 = 33,
1068   NOP_UNARY_OPCODE_Y0 = 5,
1069   NOP_UNARY_OPCODE_Y1 = 15,
1070   NOR_RRR_0_OPCODE_X0 = 64,
1071   NOR_RRR_0_OPCODE_X1 = 28,
1072   NOR_RRR_5_OPCODE_Y0 = 1,
1073   NOR_RRR_5_OPCODE_Y1 = 1,
1074   ORI_IMM8_OPCODE_X0 = 7,
1075   ORI_IMM8_OPCODE_X1 = 24,
1076   OR_RRR_0_OPCODE_X0 = 65,
1077   OR_RRR_0_OPCODE_X1 = 29,
1078   OR_RRR_5_OPCODE_Y0 = 2,
1079   OR_RRR_5_OPCODE_Y1 = 2,
1080   PCNT_UNARY_OPCODE_X0 = 6,
1081   PCNT_UNARY_OPCODE_Y0 = 6,
1082   REVBITS_UNARY_OPCODE_X0 = 7,
1083   REVBITS_UNARY_OPCODE_Y0 = 7,
1084   REVBYTES_UNARY_OPCODE_X0 = 8,
1085   REVBYTES_UNARY_OPCODE_Y0 = 8,
1086   ROTLI_SHIFT_OPCODE_X0 = 1,
1087   ROTLI_SHIFT_OPCODE_X1 = 1,
1088   ROTLI_SHIFT_OPCODE_Y0 = 0,
1089   ROTLI_SHIFT_OPCODE_Y1 = 0,
1090   ROTL_RRR_0_OPCODE_X0 = 66,
1091   ROTL_RRR_0_OPCODE_X1 = 30,
1092   ROTL_RRR_6_OPCODE_Y0 = 0,
1093   ROTL_RRR_6_OPCODE_Y1 = 0,
1094   RRR_0_OPCODE_X0 = 5,
1095   RRR_0_OPCODE_X1 = 5,
1096   RRR_0_OPCODE_Y0 = 5,
1097   RRR_0_OPCODE_Y1 = 6,
1098   RRR_1_OPCODE_Y0 = 6,
1099   RRR_1_OPCODE_Y1 = 7,
1100   RRR_2_OPCODE_Y0 = 7,
1101   RRR_2_OPCODE_Y1 = 8,
1102   RRR_3_OPCODE_Y0 = 8,
1103   RRR_3_OPCODE_Y1 = 9,
1104   RRR_4_OPCODE_Y0 = 9,
1105   RRR_4_OPCODE_Y1 = 10,
1106   RRR_5_OPCODE_Y0 = 10,
1107   RRR_5_OPCODE_Y1 = 11,
1108   RRR_6_OPCODE_Y0 = 11,
1109   RRR_6_OPCODE_Y1 = 12,
1110   RRR_7_OPCODE_Y0 = 12,
1111   RRR_7_OPCODE_Y1 = 13,
1112   RRR_8_OPCODE_Y0 = 13,
1113   RRR_9_OPCODE_Y0 = 14,
1114   SHIFT_OPCODE_X0 = 6,
1115   SHIFT_OPCODE_X1 = 6,
1116   SHIFT_OPCODE_Y0 = 15,
1117   SHIFT_OPCODE_Y1 = 14,
1118   SHL16INSLI_OPCODE_X0 = 7,
1119   SHL16INSLI_OPCODE_X1 = 7,
1120   SHL1ADDX_RRR_0_OPCODE_X0 = 67,
1121   SHL1ADDX_RRR_0_OPCODE_X1 = 31,
1122   SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
1123   SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
1124   SHL1ADD_RRR_0_OPCODE_X0 = 68,
1125   SHL1ADD_RRR_0_OPCODE_X1 = 32,
1126   SHL1ADD_RRR_1_OPCODE_Y0 = 0,
1127   SHL1ADD_RRR_1_OPCODE_Y1 = 0,
1128   SHL2ADDX_RRR_0_OPCODE_X0 = 69,
1129   SHL2ADDX_RRR_0_OPCODE_X1 = 33,
1130   SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
1131   SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
1132   SHL2ADD_RRR_0_OPCODE_X0 = 70,
1133   SHL2ADD_RRR_0_OPCODE_X1 = 34,
1134   SHL2ADD_RRR_1_OPCODE_Y0 = 1,
1135   SHL2ADD_RRR_1_OPCODE_Y1 = 1,
1136   SHL3ADDX_RRR_0_OPCODE_X0 = 71,
1137   SHL3ADDX_RRR_0_OPCODE_X1 = 35,
1138   SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
1139   SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
1140   SHL3ADD_RRR_0_OPCODE_X0 = 72,
1141   SHL3ADD_RRR_0_OPCODE_X1 = 36,
1142   SHL3ADD_RRR_1_OPCODE_Y0 = 2,
1143   SHL3ADD_RRR_1_OPCODE_Y1 = 2,
1144   SHLI_SHIFT_OPCODE_X0 = 2,
1145   SHLI_SHIFT_OPCODE_X1 = 2,
1146   SHLI_SHIFT_OPCODE_Y0 = 1,
1147   SHLI_SHIFT_OPCODE_Y1 = 1,
1148   SHLXI_SHIFT_OPCODE_X0 = 3,
1149   SHLXI_SHIFT_OPCODE_X1 = 3,
1150   SHLX_RRR_0_OPCODE_X0 = 73,
1151   SHLX_RRR_0_OPCODE_X1 = 37,
1152   SHL_RRR_0_OPCODE_X0 = 74,
1153   SHL_RRR_0_OPCODE_X1 = 38,
1154   SHL_RRR_6_OPCODE_Y0 = 1,
1155   SHL_RRR_6_OPCODE_Y1 = 1,
1156   SHRSI_SHIFT_OPCODE_X0 = 4,
1157   SHRSI_SHIFT_OPCODE_X1 = 4,
1158   SHRSI_SHIFT_OPCODE_Y0 = 2,
1159   SHRSI_SHIFT_OPCODE_Y1 = 2,
1160   SHRS_RRR_0_OPCODE_X0 = 75,
1161   SHRS_RRR_0_OPCODE_X1 = 39,
1162   SHRS_RRR_6_OPCODE_Y0 = 2,
1163   SHRS_RRR_6_OPCODE_Y1 = 2,
1164   SHRUI_SHIFT_OPCODE_X0 = 5,
1165   SHRUI_SHIFT_OPCODE_X1 = 5,
1166   SHRUI_SHIFT_OPCODE_Y0 = 3,
1167   SHRUI_SHIFT_OPCODE_Y1 = 3,
1168   SHRUXI_SHIFT_OPCODE_X0 = 6,
1169   SHRUXI_SHIFT_OPCODE_X1 = 6,
1170   SHRUX_RRR_0_OPCODE_X0 = 76,
1171   SHRUX_RRR_0_OPCODE_X1 = 40,
1172   SHRU_RRR_0_OPCODE_X0 = 77,
1173   SHRU_RRR_0_OPCODE_X1 = 41,
1174   SHRU_RRR_6_OPCODE_Y0 = 3,
1175   SHRU_RRR_6_OPCODE_Y1 = 3,
1176   SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
1177   ST1_ADD_IMM8_OPCODE_X1 = 25,
1178   ST1_OPCODE_Y2 = 0,
1179   ST1_RRR_0_OPCODE_X1 = 42,
1180   ST2_ADD_IMM8_OPCODE_X1 = 26,
1181   ST2_OPCODE_Y2 = 1,
1182   ST2_RRR_0_OPCODE_X1 = 43,
1183   ST4_ADD_IMM8_OPCODE_X1 = 27,
1184   ST4_OPCODE_Y2 = 2,
1185   ST4_RRR_0_OPCODE_X1 = 44,
1186   STNT1_ADD_IMM8_OPCODE_X1 = 28,
1187   STNT1_RRR_0_OPCODE_X1 = 45,
1188   STNT2_ADD_IMM8_OPCODE_X1 = 29,
1189   STNT2_RRR_0_OPCODE_X1 = 46,
1190   STNT4_ADD_IMM8_OPCODE_X1 = 30,
1191   STNT4_RRR_0_OPCODE_X1 = 47,
1192   STNT_ADD_IMM8_OPCODE_X1 = 31,
1193   STNT_RRR_0_OPCODE_X1 = 48,
1194   ST_ADD_IMM8_OPCODE_X1 = 32,
1195   ST_OPCODE_Y2 = 3,
1196   ST_RRR_0_OPCODE_X1 = 49,
1197   SUBXSC_RRR_0_OPCODE_X0 = 79,
1198   SUBXSC_RRR_0_OPCODE_X1 = 50,
1199   SUBX_RRR_0_OPCODE_X0 = 80,
1200   SUBX_RRR_0_OPCODE_X1 = 51,
1201   SUBX_RRR_0_OPCODE_Y0 = 2,
1202   SUBX_RRR_0_OPCODE_Y1 = 2,
1203   SUB_RRR_0_OPCODE_X0 = 81,
1204   SUB_RRR_0_OPCODE_X1 = 52,
1205   SUB_RRR_0_OPCODE_Y0 = 3,
1206   SUB_RRR_0_OPCODE_Y1 = 3,
1207   SWINT0_UNARY_OPCODE_X1 = 34,
1208   SWINT1_UNARY_OPCODE_X1 = 35,
1209   SWINT2_UNARY_OPCODE_X1 = 36,
1210   SWINT3_UNARY_OPCODE_X1 = 37,
1211   TBLIDXB0_UNARY_OPCODE_X0 = 9,
1212   TBLIDXB0_UNARY_OPCODE_Y0 = 9,
1213   TBLIDXB1_UNARY_OPCODE_X0 = 10,
1214   TBLIDXB1_UNARY_OPCODE_Y0 = 10,
1215   TBLIDXB2_UNARY_OPCODE_X0 = 11,
1216   TBLIDXB2_UNARY_OPCODE_Y0 = 11,
1217   TBLIDXB3_UNARY_OPCODE_X0 = 12,
1218   TBLIDXB3_UNARY_OPCODE_Y0 = 12,
1219   UNARY_RRR_0_OPCODE_X0 = 82,
1220   UNARY_RRR_0_OPCODE_X1 = 53,
1221   UNARY_RRR_1_OPCODE_Y0 = 3,
1222   UNARY_RRR_1_OPCODE_Y1 = 3,
1223   V1ADDI_IMM8_OPCODE_X0 = 8,
1224   V1ADDI_IMM8_OPCODE_X1 = 33,
1225   V1ADDUC_RRR_0_OPCODE_X0 = 83,
1226   V1ADDUC_RRR_0_OPCODE_X1 = 54,
1227   V1ADD_RRR_0_OPCODE_X0 = 84,
1228   V1ADD_RRR_0_OPCODE_X1 = 55,
1229   V1ADIFFU_RRR_0_OPCODE_X0 = 85,
1230   V1AVGU_RRR_0_OPCODE_X0 = 86,
1231   V1CMPEQI_IMM8_OPCODE_X0 = 9,
1232   V1CMPEQI_IMM8_OPCODE_X1 = 34,
1233   V1CMPEQ_RRR_0_OPCODE_X0 = 87,
1234   V1CMPEQ_RRR_0_OPCODE_X1 = 56,
1235   V1CMPLES_RRR_0_OPCODE_X0 = 88,
1236   V1CMPLES_RRR_0_OPCODE_X1 = 57,
1237   V1CMPLEU_RRR_0_OPCODE_X0 = 89,
1238   V1CMPLEU_RRR_0_OPCODE_X1 = 58,
1239   V1CMPLTSI_IMM8_OPCODE_X0 = 10,
1240   V1CMPLTSI_IMM8_OPCODE_X1 = 35,
1241   V1CMPLTS_RRR_0_OPCODE_X0 = 90,
1242   V1CMPLTS_RRR_0_OPCODE_X1 = 59,
1243   V1CMPLTUI_IMM8_OPCODE_X0 = 11,
1244   V1CMPLTUI_IMM8_OPCODE_X1 = 36,
1245   V1CMPLTU_RRR_0_OPCODE_X0 = 91,
1246   V1CMPLTU_RRR_0_OPCODE_X1 = 60,
1247   V1CMPNE_RRR_0_OPCODE_X0 = 92,
1248   V1CMPNE_RRR_0_OPCODE_X1 = 61,
1249   V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
1250   V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
1251   V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
1252   V1DDOTPU_RRR_0_OPCODE_X0 = 162,
1253   V1DOTPA_RRR_0_OPCODE_X0 = 95,
1254   V1DOTPUA_RRR_0_OPCODE_X0 = 163,
1255   V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
1256   V1DOTPUS_RRR_0_OPCODE_X0 = 97,
1257   V1DOTPU_RRR_0_OPCODE_X0 = 164,
1258   V1DOTP_RRR_0_OPCODE_X0 = 98,
1259   V1INT_H_RRR_0_OPCODE_X0 = 99,
1260   V1INT_H_RRR_0_OPCODE_X1 = 62,
1261   V1INT_L_RRR_0_OPCODE_X0 = 100,
1262   V1INT_L_RRR_0_OPCODE_X1 = 63,
1263   V1MAXUI_IMM8_OPCODE_X0 = 12,
1264   V1MAXUI_IMM8_OPCODE_X1 = 37,
1265   V1MAXU_RRR_0_OPCODE_X0 = 101,
1266   V1MAXU_RRR_0_OPCODE_X1 = 64,
1267   V1MINUI_IMM8_OPCODE_X0 = 13,
1268   V1MINUI_IMM8_OPCODE_X1 = 38,
1269   V1MINU_RRR_0_OPCODE_X0 = 102,
1270   V1MINU_RRR_0_OPCODE_X1 = 65,
1271   V1MNZ_RRR_0_OPCODE_X0 = 103,
1272   V1MNZ_RRR_0_OPCODE_X1 = 66,
1273   V1MULTU_RRR_0_OPCODE_X0 = 104,
1274   V1MULUS_RRR_0_OPCODE_X0 = 105,
1275   V1MULU_RRR_0_OPCODE_X0 = 106,
1276   V1MZ_RRR_0_OPCODE_X0 = 107,
1277   V1MZ_RRR_0_OPCODE_X1 = 67,
1278   V1SADAU_RRR_0_OPCODE_X0 = 108,
1279   V1SADU_RRR_0_OPCODE_X0 = 109,
1280   V1SHLI_SHIFT_OPCODE_X0 = 7,
1281   V1SHLI_SHIFT_OPCODE_X1 = 7,
1282   V1SHL_RRR_0_OPCODE_X0 = 110,
1283   V1SHL_RRR_0_OPCODE_X1 = 68,
1284   V1SHRSI_SHIFT_OPCODE_X0 = 8,
1285   V1SHRSI_SHIFT_OPCODE_X1 = 8,
1286   V1SHRS_RRR_0_OPCODE_X0 = 111,
1287   V1SHRS_RRR_0_OPCODE_X1 = 69,
1288   V1SHRUI_SHIFT_OPCODE_X0 = 9,
1289   V1SHRUI_SHIFT_OPCODE_X1 = 9,
1290   V1SHRU_RRR_0_OPCODE_X0 = 112,
1291   V1SHRU_RRR_0_OPCODE_X1 = 70,
1292   V1SUBUC_RRR_0_OPCODE_X0 = 113,
1293   V1SUBUC_RRR_0_OPCODE_X1 = 71,
1294   V1SUB_RRR_0_OPCODE_X0 = 114,
1295   V1SUB_RRR_0_OPCODE_X1 = 72,
1296   V2ADDI_IMM8_OPCODE_X0 = 14,
1297   V2ADDI_IMM8_OPCODE_X1 = 39,
1298   V2ADDSC_RRR_0_OPCODE_X0 = 115,
1299   V2ADDSC_RRR_0_OPCODE_X1 = 73,
1300   V2ADD_RRR_0_OPCODE_X0 = 116,
1301   V2ADD_RRR_0_OPCODE_X1 = 74,
1302   V2ADIFFS_RRR_0_OPCODE_X0 = 117,
1303   V2AVGS_RRR_0_OPCODE_X0 = 118,
1304   V2CMPEQI_IMM8_OPCODE_X0 = 15,
1305   V2CMPEQI_IMM8_OPCODE_X1 = 40,
1306   V2CMPEQ_RRR_0_OPCODE_X0 = 119,
1307   V2CMPEQ_RRR_0_OPCODE_X1 = 75,
1308   V2CMPLES_RRR_0_OPCODE_X0 = 120,
1309   V2CMPLES_RRR_0_OPCODE_X1 = 76,
1310   V2CMPLEU_RRR_0_OPCODE_X0 = 121,
1311   V2CMPLEU_RRR_0_OPCODE_X1 = 77,
1312   V2CMPLTSI_IMM8_OPCODE_X0 = 16,
1313   V2CMPLTSI_IMM8_OPCODE_X1 = 41,
1314   V2CMPLTS_RRR_0_OPCODE_X0 = 122,
1315   V2CMPLTS_RRR_0_OPCODE_X1 = 78,
1316   V2CMPLTUI_IMM8_OPCODE_X0 = 17,
1317   V2CMPLTUI_IMM8_OPCODE_X1 = 42,
1318   V2CMPLTU_RRR_0_OPCODE_X0 = 123,
1319   V2CMPLTU_RRR_0_OPCODE_X1 = 79,
1320   V2CMPNE_RRR_0_OPCODE_X0 = 124,
1321   V2CMPNE_RRR_0_OPCODE_X1 = 80,
1322   V2DOTPA_RRR_0_OPCODE_X0 = 125,
1323   V2DOTP_RRR_0_OPCODE_X0 = 126,
1324   V2INT_H_RRR_0_OPCODE_X0 = 127,
1325   V2INT_H_RRR_0_OPCODE_X1 = 81,
1326   V2INT_L_RRR_0_OPCODE_X0 = 128,
1327   V2INT_L_RRR_0_OPCODE_X1 = 82,
1328   V2MAXSI_IMM8_OPCODE_X0 = 18,
1329   V2MAXSI_IMM8_OPCODE_X1 = 43,
1330   V2MAXS_RRR_0_OPCODE_X0 = 129,
1331   V2MAXS_RRR_0_OPCODE_X1 = 83,
1332   V2MINSI_IMM8_OPCODE_X0 = 19,
1333   V2MINSI_IMM8_OPCODE_X1 = 44,
1334   V2MINS_RRR_0_OPCODE_X0 = 130,
1335   V2MINS_RRR_0_OPCODE_X1 = 84,
1336   V2MNZ_RRR_0_OPCODE_X0 = 131,
1337   V2MNZ_RRR_0_OPCODE_X1 = 85,
1338   V2MULFSC_RRR_0_OPCODE_X0 = 132,
1339   V2MULS_RRR_0_OPCODE_X0 = 133,
1340   V2MULTS_RRR_0_OPCODE_X0 = 134,
1341   V2MZ_RRR_0_OPCODE_X0 = 135,
1342   V2MZ_RRR_0_OPCODE_X1 = 86,
1343   V2PACKH_RRR_0_OPCODE_X0 = 136,
1344   V2PACKH_RRR_0_OPCODE_X1 = 87,
1345   V2PACKL_RRR_0_OPCODE_X0 = 137,
1346   V2PACKL_RRR_0_OPCODE_X1 = 88,
1347   V2PACKUC_RRR_0_OPCODE_X0 = 138,
1348   V2PACKUC_RRR_0_OPCODE_X1 = 89,
1349   V2SADAS_RRR_0_OPCODE_X0 = 139,
1350   V2SADAU_RRR_0_OPCODE_X0 = 140,
1351   V2SADS_RRR_0_OPCODE_X0 = 141,
1352   V2SADU_RRR_0_OPCODE_X0 = 142,
1353   V2SHLI_SHIFT_OPCODE_X0 = 10,
1354   V2SHLI_SHIFT_OPCODE_X1 = 10,
1355   V2SHLSC_RRR_0_OPCODE_X0 = 143,
1356   V2SHLSC_RRR_0_OPCODE_X1 = 90,
1357   V2SHL_RRR_0_OPCODE_X0 = 144,
1358   V2SHL_RRR_0_OPCODE_X1 = 91,
1359   V2SHRSI_SHIFT_OPCODE_X0 = 11,
1360   V2SHRSI_SHIFT_OPCODE_X1 = 11,
1361   V2SHRS_RRR_0_OPCODE_X0 = 145,
1362   V2SHRS_RRR_0_OPCODE_X1 = 92,
1363   V2SHRUI_SHIFT_OPCODE_X0 = 12,
1364   V2SHRUI_SHIFT_OPCODE_X1 = 12,
1365   V2SHRU_RRR_0_OPCODE_X0 = 146,
1366   V2SHRU_RRR_0_OPCODE_X1 = 93,
1367   V2SUBSC_RRR_0_OPCODE_X0 = 147,
1368   V2SUBSC_RRR_0_OPCODE_X1 = 94,
1369   V2SUB_RRR_0_OPCODE_X0 = 148,
1370   V2SUB_RRR_0_OPCODE_X1 = 95,
1371   V4ADDSC_RRR_0_OPCODE_X0 = 149,
1372   V4ADDSC_RRR_0_OPCODE_X1 = 96,
1373   V4ADD_RRR_0_OPCODE_X0 = 150,
1374   V4ADD_RRR_0_OPCODE_X1 = 97,
1375   V4INT_H_RRR_0_OPCODE_X0 = 151,
1376   V4INT_H_RRR_0_OPCODE_X1 = 98,
1377   V4INT_L_RRR_0_OPCODE_X0 = 152,
1378   V4INT_L_RRR_0_OPCODE_X1 = 99,
1379   V4PACKSC_RRR_0_OPCODE_X0 = 153,
1380   V4PACKSC_RRR_0_OPCODE_X1 = 100,
1381   V4SHLSC_RRR_0_OPCODE_X0 = 154,
1382   V4SHLSC_RRR_0_OPCODE_X1 = 101,
1383   V4SHL_RRR_0_OPCODE_X0 = 155,
1384   V4SHL_RRR_0_OPCODE_X1 = 102,
1385   V4SHRS_RRR_0_OPCODE_X0 = 156,
1386   V4SHRS_RRR_0_OPCODE_X1 = 103,
1387   V4SHRU_RRR_0_OPCODE_X0 = 157,
1388   V4SHRU_RRR_0_OPCODE_X1 = 104,
1389   V4SUBSC_RRR_0_OPCODE_X0 = 158,
1390   V4SUBSC_RRR_0_OPCODE_X1 = 105,
1391   V4SUB_RRR_0_OPCODE_X0 = 159,
1392   V4SUB_RRR_0_OPCODE_X1 = 106,
1393   WH64_UNARY_OPCODE_X1 = 38,
1394   XORI_IMM8_OPCODE_X0 = 20,
1395   XORI_IMM8_OPCODE_X1 = 45,
1396   XOR_RRR_0_OPCODE_X0 = 160,
1397   XOR_RRR_0_OPCODE_X1 = 107,
1398   XOR_RRR_5_OPCODE_Y0 = 3,
1399   XOR_RRR_5_OPCODE_Y1 = 3
1400 };
1401
1402
1403 #endif /* __ASSEMBLER__ */
1404
1405 #endif /* __ARCH_OPCODE_H__ */