arch/v850/kernel/rte_ma1_cb.c

   1 /*
   2  * arch/v850/kernel/rte_ma1_cb.c -- Midas labs RTE-V850E/MA1-CB board
   3  *
   4  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
   5  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
   6  *
   7  * This file is subject to the terms and conditions of the GNU General
   8  * Public License.  See the file COPYING in the main directory of this
   9  * archive for more details.
  10  *
  11  * Written by Miles Bader <miles@gnu.org>
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17
  18 #include <asm/atomic.h>
  19 #include <asm/page.h>
  20 #include <asm/ma1.h>
  21 #include <asm/rte_ma1_cb.h>
  22 #include <asm/v850e_timer_c.h>
  23
  24 #include "mach.h"
  25
  26
  27 /* SRAM and SDRAM are almost contiguous (with a small hole in between;
  28    see mach_reserve_bootmem for details), so just use both as one big area.  */
  29 #define RAM_START       SRAM_ADDR
  30 #define RAM_END         (SDRAM_ADDR + SDRAM_SIZE)
  31
  32
  33 void __init mach_early_init (void)
  34 {
  35         rte_cb_early_init ();
  36 }
  37
  38 void __init mach_get_physical_ram (unsigned long *ram_start,
  39                                    unsigned long *ram_len)
  40 {
  41         *ram_start = RAM_START;
  42         *ram_len = RAM_END - RAM_START;
  43 }
  44
  45 void __init mach_reserve_bootmem ()
  46 {
  47 #ifdef CONFIG_RTE_CB_MULTI
  48         /* Prevent the kernel from touching the monitor's scratch RAM.  */
  49         reserve_bootmem(MON_SCRATCH_ADDR, MON_SCRATCH_SIZE,
  50                         BOOTMEM_DEFAULT);
  51 #endif
  52
  53         /* The space between SRAM and SDRAM is filled with duplicate
  54            images of SRAM.  Prevent the kernel from using them.  */
  55         reserve_bootmem (SRAM_ADDR + SRAM_SIZE,
  56                          SDRAM_ADDR - (SRAM_ADDR + SRAM_SIZE),
  57                          BOOTMEM_DEFAULT);
  58 }
  59
  60 void mach_gettimeofday (struct timespec *tv)
  61 {
  62         tv->tv_sec = 0;
  63         tv->tv_nsec = 0;
  64 }
  65
  66 /* Called before configuring an on-chip UART.  */
  67 void rte_ma1_cb_uart_pre_configure (unsigned chan,
  68                                     unsigned cflags, unsigned baud)
  69 {
  70         /* The RTE-MA1-CB connects some general-purpose I/O pins on the
  71            CPU to the RTS/CTS lines of UART 0's serial connection.
  72            I/O pins P42 and P43 are RTS and CTS respectively.  */
  73         if (chan == 0) {
  74                 /* Put P42 & P43 in I/O port mode.  */
  75                 MA_PORT4_PMC &= ~0xC;
  76                 /* Make P42 an output, and P43 an input.  */
  77                 MA_PORT4_PM = (MA_PORT4_PM & ~0xC) | 0x8;
  78         }
  79
  80         /* Do pre-configuration for the actual UART.  */
  81         ma_uart_pre_configure (chan, cflags, baud);
  82 }
  83
  84 void __init mach_init_irqs (void)
  85 {
  86         unsigned tc;
  87
  88         /* Initialize interrupts.  */
  89         ma_init_irqs ();
  90         rte_cb_init_irqs ();
  91
  92         /* Use falling-edge-sensitivity for interrupts .  */
  93         V850E_TIMER_C_SESC (0) &= ~0xC;
  94         V850E_TIMER_C_SESC (1) &= ~0xF;
  95
  96         /* INTP000-INTP011 are shared with `Timer C', so we have to set
  97            up Timer C to pass them through as raw interrupts.  */
  98         for (tc = 0; tc < 2; tc++)
  99                 /* Turn on the timer.  */
 100                 V850E_TIMER_C_TMCC0 (tc) |= V850E_TIMER_C_TMCC0_CAE;
 101
 102         /* Make sure the relevant port0/port1 pins are assigned
 103            interrupt duty.  We used INTP001-INTP011 (don't screw with
 104            INTP000 because the monitor uses it).  */
 105         MA_PORT0_PMC |= 0x4;    /* P02 (INTP001) in IRQ mode.  */
 106         MA_PORT1_PMC |= 0x6;    /* P11 (INTP010) & P12 (INTP011) in IRQ mode.*/
 107 }