2 * Performance events - AMD Processor Power Reporting Mechanism
4 * Copyright (C) 2016 Advanced Micro Devices, Inc.
6 * Author: Huang Rui <ray.huang@amd.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/perf_event.h>
16 #include <asm/cpu_device_id.h>
17 #include "../perf_event.h"
19 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
20 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
21 #define MSR_F15H_PTSC 0xc0010280
23 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
24 #define AMD_POWER_EVENT_MASK 0xFFULL
27 * Accumulated power status counters.
29 #define AMD_POWER_EVENTSEL_PKG 1
32 * The ratio of compute unit power accumulator sample period to the
35 static unsigned int cpu_pwr_sample_ratio
;
37 /* Maximum accumulated power of a compute unit. */
38 static u64 max_cu_acc_power
;
40 static struct pmu pmu_class
;
43 * Accumulated power represents the sum of each compute unit's (CU) power
44 * consumption. On any core of each CU we read the total accumulated power from
45 * MSR_F15H_CU_PWR_ACCUMULATOR. cpu_mask represents CPU bit map of all cores
46 * which are picked to measure the power for the CUs they belong to.
48 static cpumask_t cpu_mask
;
50 static void event_update(struct perf_event
*event
)
52 struct hw_perf_event
*hwc
= &event
->hw
;
53 u64 prev_pwr_acc
, new_pwr_acc
, prev_ptsc
, new_ptsc
;
56 prev_pwr_acc
= hwc
->pwr_acc
;
57 prev_ptsc
= hwc
->ptsc
;
58 rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR
, new_pwr_acc
);
59 rdmsrl(MSR_F15H_PTSC
, new_ptsc
);
62 * Calculate the CU power consumption over a time period, the unit of
63 * final value (delta) is micro-Watts. Then add it to the event count.
65 if (new_pwr_acc
< prev_pwr_acc
) {
66 delta
= max_cu_acc_power
+ new_pwr_acc
;
67 delta
-= prev_pwr_acc
;
69 delta
= new_pwr_acc
- prev_pwr_acc
;
71 delta
*= cpu_pwr_sample_ratio
* 1000;
72 tdelta
= new_ptsc
- prev_ptsc
;
74 do_div(delta
, tdelta
);
75 local64_add(delta
, &event
->count
);
78 static void __pmu_event_start(struct perf_event
*event
)
80 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
85 rdmsrl(MSR_F15H_PTSC
, event
->hw
.ptsc
);
86 rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR
, event
->hw
.pwr_acc
);
89 static void pmu_event_start(struct perf_event
*event
, int mode
)
91 __pmu_event_start(event
);
94 static void pmu_event_stop(struct perf_event
*event
, int mode
)
96 struct hw_perf_event
*hwc
= &event
->hw
;
98 /* Mark event as deactivated and stopped. */
99 if (!(hwc
->state
& PERF_HES_STOPPED
))
100 hwc
->state
|= PERF_HES_STOPPED
;
102 /* Check if software counter update is necessary. */
103 if ((mode
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
105 * Drain the remaining delta count out of an event
106 * that we are disabling:
109 hwc
->state
|= PERF_HES_UPTODATE
;
113 static int pmu_event_add(struct perf_event
*event
, int mode
)
115 struct hw_perf_event
*hwc
= &event
->hw
;
117 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
119 if (mode
& PERF_EF_START
)
120 __pmu_event_start(event
);
125 static void pmu_event_del(struct perf_event
*event
, int flags
)
127 pmu_event_stop(event
, PERF_EF_UPDATE
);
130 static int pmu_event_init(struct perf_event
*event
)
132 u64 cfg
= event
->attr
.config
& AMD_POWER_EVENT_MASK
;
134 /* Only look at AMD power events. */
135 if (event
->attr
.type
!= pmu_class
.type
)
138 /* Unsupported modes and filters. */
139 if (event
->attr
.exclude_user
||
140 event
->attr
.exclude_kernel
||
141 event
->attr
.exclude_hv
||
142 event
->attr
.exclude_idle
||
143 event
->attr
.exclude_host
||
144 event
->attr
.exclude_guest
||
146 event
->attr
.sample_period
)
149 if (cfg
!= AMD_POWER_EVENTSEL_PKG
)
155 static void pmu_event_read(struct perf_event
*event
)
161 get_attr_cpumask(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
163 return cpumap_print_to_pagebuf(true, buf
, &cpu_mask
);
166 static DEVICE_ATTR(cpumask
, S_IRUGO
, get_attr_cpumask
, NULL
);
168 static struct attribute
*pmu_attrs
[] = {
169 &dev_attr_cpumask
.attr
,
173 static struct attribute_group pmu_attr_group
= {
178 * Currently it only supports to report the power of each
181 EVENT_ATTR_STR(power
-pkg
, power_pkg
, "event=0x01");
183 EVENT_ATTR_STR(power
-pkg
.unit
, power_pkg_unit
, "mWatts");
185 /* Convert the count from micro-Watts to milli-Watts. */
186 EVENT_ATTR_STR(power
-pkg
.scale
, power_pkg_scale
, "1.000000e-3");
188 static struct attribute
*events_attr
[] = {
189 EVENT_PTR(power_pkg
),
190 EVENT_PTR(power_pkg_unit
),
191 EVENT_PTR(power_pkg_scale
),
195 static struct attribute_group pmu_events_group
= {
197 .attrs
= events_attr
,
200 PMU_FORMAT_ATTR(event
, "config:0-7");
202 static struct attribute
*formats_attr
[] = {
203 &format_attr_event
.attr
,
207 static struct attribute_group pmu_format_group
= {
209 .attrs
= formats_attr
,
212 static const struct attribute_group
*attr_groups
[] = {
219 static struct pmu pmu_class
= {
220 .attr_groups
= attr_groups
,
221 /* system-wide only */
222 .task_ctx_nr
= perf_invalid_context
,
223 .event_init
= pmu_event_init
,
224 .add
= pmu_event_add
,
225 .del
= pmu_event_del
,
226 .start
= pmu_event_start
,
227 .stop
= pmu_event_stop
,
228 .read
= pmu_event_read
,
231 static void power_cpu_exit(int cpu
)
235 if (!cpumask_test_and_clear_cpu(cpu
, &cpu_mask
))
239 * Find a new CPU on the same compute unit, if was set in cpumask
240 * and still some CPUs on compute unit. Then migrate event and
241 * context to new CPU.
243 target
= cpumask_any_but(topology_sibling_cpumask(cpu
), cpu
);
244 if (target
< nr_cpumask_bits
) {
245 cpumask_set_cpu(target
, &cpu_mask
);
246 perf_pmu_migrate_context(&pmu_class
, cpu
, target
);
250 static void power_cpu_init(int cpu
)
255 * 1) If any CPU is set at cpu_mask in the same compute unit, do
257 * 2) If no CPU is set at cpu_mask in the same compute unit,
258 * set current STARTING CPU.
260 * Note: if there is a CPU aside of the new one already in the
261 * sibling mask, then it is also in cpu_mask.
263 target
= cpumask_any_but(topology_sibling_cpumask(cpu
), cpu
);
264 if (target
>= nr_cpumask_bits
)
265 cpumask_set_cpu(cpu
, &cpu_mask
);
269 power_cpu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
271 unsigned int cpu
= (long)hcpu
;
273 switch (action
& ~CPU_TASKS_FROZEN
) {
274 case CPU_DOWN_FAILED
:
278 case CPU_DOWN_PREPARE
:
288 static struct notifier_block power_cpu_notifier_nb
= {
289 .notifier_call
= power_cpu_notifier
,
290 .priority
= CPU_PRI_PERF
,
293 static const struct x86_cpu_id cpu_match
[] = {
294 { .vendor
= X86_VENDOR_AMD
, .family
= 0x15 },
298 static int __init
amd_power_pmu_init(void)
300 int cpu
, target
, ret
;
302 if (!x86_match_cpu(cpu_match
))
305 if (!boot_cpu_has(X86_FEATURE_ACC_POWER
))
308 cpu_pwr_sample_ratio
= cpuid_ecx(0x80000007);
310 if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR
, &max_cu_acc_power
)) {
311 pr_err("Failed to read max compute unit power accumulator MSR\n");
315 cpu_notifier_register_begin();
317 /* Choose one online core of each compute unit. */
318 for_each_online_cpu(cpu
) {
319 target
= cpumask_first(topology_sibling_cpumask(cpu
));
320 if (!cpumask_test_cpu(target
, &cpu_mask
))
321 cpumask_set_cpu(target
, &cpu_mask
);
324 ret
= perf_pmu_register(&pmu_class
, "power", -1);
326 pr_warn("AMD Power PMU registration failed\n");
330 __register_cpu_notifier(&power_cpu_notifier_nb
);
332 pr_info("AMD Power PMU detected\n");
335 cpu_notifier_register_done();
339 module_init(amd_power_pmu_init
);
341 static void __exit
amd_power_pmu_exit(void)
343 cpu_notifier_register_begin();
344 __unregister_cpu_notifier(&power_cpu_notifier_nb
);
345 cpu_notifier_register_done();
347 perf_pmu_unregister(&pmu_class
);
349 module_exit(amd_power_pmu_exit
);
351 MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
352 MODULE_DESCRIPTION("AMD Processor Power Reporting Mechanism");
353 MODULE_LICENSE("GPL v2");