2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly
;
44 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
48 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX
]
52 [PERF_COUNT_HW_CACHE_OP_MAX
]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64
x86_perf_event_update(struct perf_event
*event
)
66 struct hw_perf_event
*hwc
= &event
->hw
;
67 int shift
= 64 - x86_pmu
.cntval_bits
;
68 u64 prev_raw_count
, new_raw_count
;
72 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count
= local64_read(&hwc
->prev_count
);
84 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
86 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
87 new_raw_count
) != prev_raw_count
)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
101 local64_add(delta
, &event
->count
);
102 local64_sub(delta
, &hwc
->period_left
);
104 return new_raw_count
;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
112 struct hw_perf_event_extra
*reg
;
113 struct extra_reg
*er
;
115 reg
= &event
->hw
.extra_reg
;
117 if (!x86_pmu
.extra_regs
)
120 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
121 if (er
->event
!= (config
& er
->config_mask
))
123 if (event
->attr
.config1
& ~er
->valid_mask
)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er
->extra_msr_access
)
130 reg
->config
= event
->attr
.config1
;
137 static atomic_t active_events
;
138 static atomic_t pmc_refcount
;
139 static DEFINE_MUTEX(pmc_reserve_mutex
);
141 #ifdef CONFIG_X86_LOCAL_APIC
143 static bool reserve_pmc_hardware(void)
147 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
148 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
152 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
153 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
160 for (i
--; i
>= 0; i
--)
161 release_evntsel_nmi(x86_pmu_config_addr(i
));
163 i
= x86_pmu
.num_counters
;
166 for (i
--; i
>= 0; i
--)
167 release_perfctr_nmi(x86_pmu_event_addr(i
));
172 static void release_pmc_hardware(void)
176 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
177 release_perfctr_nmi(x86_pmu_event_addr(i
));
178 release_evntsel_nmi(x86_pmu_config_addr(i
));
184 static bool reserve_pmc_hardware(void) { return true; }
185 static void release_pmc_hardware(void) {}
189 static bool check_hw_exists(void)
191 u64 val
, val_fail
, val_new
= ~0;
192 int i
, reg
, reg_fail
, ret
= 0;
197 * Check to see if the BIOS enabled any of the counters, if so
200 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
201 reg
= x86_pmu_config_addr(i
);
202 ret
= rdmsrl_safe(reg
, &val
);
205 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
214 if (x86_pmu
.num_counters_fixed
) {
215 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
216 ret
= rdmsrl_safe(reg
, &val
);
219 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
220 if (val
& (0x03 << i
*4)) {
229 * If all the counters are enabled, the below test will always
230 * fail. The tools will also become useless in this scenario.
231 * Just fail and disable the hardware counters.
234 if (reg_safe
== -1) {
240 * Read the current value, change it and read it back to see if it
241 * matches, this is needed to detect certain hardware emulators
242 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
244 reg
= x86_pmu_event_addr(reg_safe
);
245 if (rdmsrl_safe(reg
, &val
))
248 ret
= wrmsrl_safe(reg
, val
);
249 ret
|= rdmsrl_safe(reg
, &val_new
);
250 if (ret
|| val
!= val_new
)
254 * We still allow the PMU driver to operate:
257 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
258 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
265 pr_cont("Broken PMU hardware detected, using software events only.\n");
266 pr_info("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
267 boot_cpu_has(X86_FEATURE_HYPERVISOR
) ? KERN_INFO
: KERN_ERR
,
273 static void hw_perf_event_destroy(struct perf_event
*event
)
275 x86_release_hardware();
276 atomic_dec(&active_events
);
279 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
281 hw_perf_event_destroy(event
);
283 /* undo the lbr/bts event accounting */
284 x86_del_exclusive(x86_lbr_exclusive_lbr
);
287 static inline int x86_pmu_initialized(void)
289 return x86_pmu
.handle_irq
!= NULL
;
293 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
295 struct perf_event_attr
*attr
= &event
->attr
;
296 unsigned int cache_type
, cache_op
, cache_result
;
299 config
= attr
->config
;
301 cache_type
= (config
>> 0) & 0xff;
302 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
305 cache_op
= (config
>> 8) & 0xff;
306 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
309 cache_result
= (config
>> 16) & 0xff;
310 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
313 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
322 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
323 return x86_pmu_extra_regs(val
, event
);
326 int x86_reserve_hardware(void)
330 if (!atomic_inc_not_zero(&pmc_refcount
)) {
331 mutex_lock(&pmc_reserve_mutex
);
332 if (atomic_read(&pmc_refcount
) == 0) {
333 if (!reserve_pmc_hardware())
336 reserve_ds_buffers();
339 atomic_inc(&pmc_refcount
);
340 mutex_unlock(&pmc_reserve_mutex
);
346 void x86_release_hardware(void)
348 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
349 release_pmc_hardware();
350 release_ds_buffers();
351 mutex_unlock(&pmc_reserve_mutex
);
356 * Check if we can create event of a certain type (that no conflicting events
359 int x86_add_exclusive(unsigned int what
)
363 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
364 mutex_lock(&pmc_reserve_mutex
);
365 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
366 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
369 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
370 mutex_unlock(&pmc_reserve_mutex
);
373 atomic_inc(&active_events
);
377 mutex_unlock(&pmc_reserve_mutex
);
381 void x86_del_exclusive(unsigned int what
)
383 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
384 atomic_dec(&active_events
);
387 int x86_setup_perfctr(struct perf_event
*event
)
389 struct perf_event_attr
*attr
= &event
->attr
;
390 struct hw_perf_event
*hwc
= &event
->hw
;
393 if (!is_sampling_event(event
)) {
394 hwc
->sample_period
= x86_pmu
.max_period
;
395 hwc
->last_period
= hwc
->sample_period
;
396 local64_set(&hwc
->period_left
, hwc
->sample_period
);
399 if (attr
->type
== PERF_TYPE_RAW
)
400 return x86_pmu_extra_regs(event
->attr
.config
, event
);
402 if (attr
->type
== PERF_TYPE_HW_CACHE
)
403 return set_ext_hw_attr(hwc
, event
);
405 if (attr
->config
>= x86_pmu
.max_events
)
411 config
= x86_pmu
.event_map(attr
->config
);
422 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
423 !attr
->freq
&& hwc
->sample_period
== 1) {
424 /* BTS is not supported by this architecture. */
425 if (!x86_pmu
.bts_active
)
428 /* BTS is currently only allowed for user-mode. */
429 if (!attr
->exclude_kernel
)
432 /* disallow bts if conflicting events are present */
433 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
436 event
->destroy
= hw_perf_lbr_event_destroy
;
439 hwc
->config
|= config
;
445 * check that branch_sample_type is compatible with
446 * settings needed for precise_ip > 1 which implies
447 * using the LBR to capture ALL taken branches at the
448 * priv levels of the measurement
450 static inline int precise_br_compat(struct perf_event
*event
)
452 u64 m
= event
->attr
.branch_sample_type
;
455 /* must capture all branches */
456 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
459 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
461 if (!event
->attr
.exclude_user
)
462 b
|= PERF_SAMPLE_BRANCH_USER
;
464 if (!event
->attr
.exclude_kernel
)
465 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
468 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
474 int x86_pmu_hw_config(struct perf_event
*event
)
476 if (event
->attr
.precise_ip
) {
479 /* Support for constant skid */
480 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
483 /* Support for IP fixup */
484 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
487 if (x86_pmu
.pebs_prec_dist
)
491 if (event
->attr
.precise_ip
> precise
)
495 * check that PEBS LBR correction does not conflict with
496 * whatever the user is asking with attr->branch_sample_type
498 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
499 u64
*br_type
= &event
->attr
.branch_sample_type
;
501 if (has_branch_stack(event
)) {
502 if (!precise_br_compat(event
))
505 /* branch_sample_type is compatible */
509 * user did not specify branch_sample_type
511 * For PEBS fixups, we capture all
512 * the branches at the priv level of the
515 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
517 if (!event
->attr
.exclude_user
)
518 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
520 if (!event
->attr
.exclude_kernel
)
521 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
525 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
526 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
530 * (keep 'enabled' bit clear for now)
532 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
535 * Count user and OS events unless requested not to
537 if (!event
->attr
.exclude_user
)
538 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
539 if (!event
->attr
.exclude_kernel
)
540 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
542 if (event
->attr
.type
== PERF_TYPE_RAW
)
543 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
545 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
546 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
547 event
->attr
.sample_period
)
551 return x86_setup_perfctr(event
);
555 * Setup the hardware configuration for a given attr_type
557 static int __x86_pmu_event_init(struct perf_event
*event
)
561 if (!x86_pmu_initialized())
564 err
= x86_reserve_hardware();
568 atomic_inc(&active_events
);
569 event
->destroy
= hw_perf_event_destroy
;
572 event
->hw
.last_cpu
= -1;
573 event
->hw
.last_tag
= ~0ULL;
576 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
577 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
579 return x86_pmu
.hw_config(event
);
582 void x86_pmu_disable_all(void)
584 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
587 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
590 if (!test_bit(idx
, cpuc
->active_mask
))
592 rdmsrl(x86_pmu_config_addr(idx
), val
);
593 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
595 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
596 wrmsrl(x86_pmu_config_addr(idx
), val
);
600 static void x86_pmu_disable(struct pmu
*pmu
)
602 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
604 if (!x86_pmu_initialized())
614 x86_pmu
.disable_all();
617 void x86_pmu_enable_all(int added
)
619 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
622 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
623 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
625 if (!test_bit(idx
, cpuc
->active_mask
))
628 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
632 static struct pmu pmu
;
634 static inline int is_x86_event(struct perf_event
*event
)
636 return event
->pmu
== &pmu
;
640 * Event scheduler state:
642 * Assign events iterating over all events and counters, beginning
643 * with events with least weights first. Keep the current iterator
644 * state in struct sched_state.
648 int event
; /* event index */
649 int counter
; /* counter index */
650 int unassigned
; /* number of events to be assigned left */
651 int nr_gp
; /* number of GP counters used */
652 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
655 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
656 #define SCHED_STATES_MAX 2
663 struct event_constraint
**constraints
;
664 struct sched_state state
;
665 struct sched_state saved
[SCHED_STATES_MAX
];
669 * Initialize interator that runs through all events and counters.
671 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
672 int num
, int wmin
, int wmax
, int gpmax
)
676 memset(sched
, 0, sizeof(*sched
));
677 sched
->max_events
= num
;
678 sched
->max_weight
= wmax
;
679 sched
->max_gp
= gpmax
;
680 sched
->constraints
= constraints
;
682 for (idx
= 0; idx
< num
; idx
++) {
683 if (constraints
[idx
]->weight
== wmin
)
687 sched
->state
.event
= idx
; /* start with min weight */
688 sched
->state
.weight
= wmin
;
689 sched
->state
.unassigned
= num
;
692 static void perf_sched_save_state(struct perf_sched
*sched
)
694 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
697 sched
->saved
[sched
->saved_states
] = sched
->state
;
698 sched
->saved_states
++;
701 static bool perf_sched_restore_state(struct perf_sched
*sched
)
703 if (!sched
->saved_states
)
706 sched
->saved_states
--;
707 sched
->state
= sched
->saved
[sched
->saved_states
];
709 /* continue with next counter: */
710 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
716 * Select a counter for the current event to schedule. Return true on
719 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
721 struct event_constraint
*c
;
724 if (!sched
->state
.unassigned
)
727 if (sched
->state
.event
>= sched
->max_events
)
730 c
= sched
->constraints
[sched
->state
.event
];
731 /* Prefer fixed purpose counters */
732 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
733 idx
= INTEL_PMC_IDX_FIXED
;
734 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
735 if (!__test_and_set_bit(idx
, sched
->state
.used
))
740 /* Grab the first unused counter starting with idx */
741 idx
= sched
->state
.counter
;
742 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
743 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
744 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
754 sched
->state
.counter
= idx
;
757 perf_sched_save_state(sched
);
762 static bool perf_sched_find_counter(struct perf_sched
*sched
)
764 while (!__perf_sched_find_counter(sched
)) {
765 if (!perf_sched_restore_state(sched
))
773 * Go through all unassigned events and find the next one to schedule.
774 * Take events with the least weight first. Return true on success.
776 static bool perf_sched_next_event(struct perf_sched
*sched
)
778 struct event_constraint
*c
;
780 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
785 sched
->state
.event
++;
786 if (sched
->state
.event
>= sched
->max_events
) {
788 sched
->state
.event
= 0;
789 sched
->state
.weight
++;
790 if (sched
->state
.weight
> sched
->max_weight
)
793 c
= sched
->constraints
[sched
->state
.event
];
794 } while (c
->weight
!= sched
->state
.weight
);
796 sched
->state
.counter
= 0; /* start with first counter */
802 * Assign a counter for each event.
804 int perf_assign_events(struct event_constraint
**constraints
, int n
,
805 int wmin
, int wmax
, int gpmax
, int *assign
)
807 struct perf_sched sched
;
809 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
812 if (!perf_sched_find_counter(&sched
))
815 assign
[sched
.state
.event
] = sched
.state
.counter
;
816 } while (perf_sched_next_event(&sched
));
818 return sched
.state
.unassigned
;
820 EXPORT_SYMBOL_GPL(perf_assign_events
);
822 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
824 struct event_constraint
*c
;
825 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
826 struct perf_event
*e
;
827 int i
, wmin
, wmax
, unsched
= 0;
828 struct hw_perf_event
*hwc
;
830 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
832 if (x86_pmu
.start_scheduling
)
833 x86_pmu
.start_scheduling(cpuc
);
835 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
836 cpuc
->event_constraint
[i
] = NULL
;
837 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
838 cpuc
->event_constraint
[i
] = c
;
840 wmin
= min(wmin
, c
->weight
);
841 wmax
= max(wmax
, c
->weight
);
845 * fastpath, try to reuse previous register
847 for (i
= 0; i
< n
; i
++) {
848 hwc
= &cpuc
->event_list
[i
]->hw
;
849 c
= cpuc
->event_constraint
[i
];
855 /* constraint still honored */
856 if (!test_bit(hwc
->idx
, c
->idxmsk
))
859 /* not already used */
860 if (test_bit(hwc
->idx
, used_mask
))
863 __set_bit(hwc
->idx
, used_mask
);
865 assign
[i
] = hwc
->idx
;
870 int gpmax
= x86_pmu
.num_counters
;
873 * Do not allow scheduling of more than half the available
876 * This helps avoid counter starvation of sibling thread by
877 * ensuring at most half the counters cannot be in exclusive
878 * mode. There is no designated counters for the limits. Any
879 * N/2 counters can be used. This helps with events with
880 * specific counter constraints.
882 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
883 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
886 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
887 wmax
, gpmax
, assign
);
891 * In case of success (unsched = 0), mark events as committed,
892 * so we do not put_constraint() in case new events are added
893 * and fail to be scheduled
895 * We invoke the lower level commit callback to lock the resource
897 * We do not need to do all of this in case we are called to
898 * validate an event group (assign == NULL)
900 if (!unsched
&& assign
) {
901 for (i
= 0; i
< n
; i
++) {
902 e
= cpuc
->event_list
[i
];
903 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
904 if (x86_pmu
.commit_scheduling
)
905 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
908 for (i
= 0; i
< n
; i
++) {
909 e
= cpuc
->event_list
[i
];
911 * do not put_constraint() on comitted events,
912 * because they are good to go
914 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
918 * release events that failed scheduling
920 if (x86_pmu
.put_event_constraints
)
921 x86_pmu
.put_event_constraints(cpuc
, e
);
925 if (x86_pmu
.stop_scheduling
)
926 x86_pmu
.stop_scheduling(cpuc
);
928 return unsched
? -EINVAL
: 0;
932 * dogrp: true if must collect siblings events (group)
933 * returns total number of events and error code
935 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
937 struct perf_event
*event
;
940 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
942 /* current number of events already accepted */
945 if (is_x86_event(leader
)) {
948 cpuc
->event_list
[n
] = leader
;
954 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
955 if (!is_x86_event(event
) ||
956 event
->state
<= PERF_EVENT_STATE_OFF
)
962 cpuc
->event_list
[n
] = event
;
968 static inline void x86_assign_hw_event(struct perf_event
*event
,
969 struct cpu_hw_events
*cpuc
, int i
)
971 struct hw_perf_event
*hwc
= &event
->hw
;
973 hwc
->idx
= cpuc
->assign
[i
];
974 hwc
->last_cpu
= smp_processor_id();
975 hwc
->last_tag
= ++cpuc
->tags
[i
];
977 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
978 hwc
->config_base
= 0;
980 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
981 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
982 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
983 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
985 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
986 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
987 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
991 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
992 struct cpu_hw_events
*cpuc
,
995 return hwc
->idx
== cpuc
->assign
[i
] &&
996 hwc
->last_cpu
== smp_processor_id() &&
997 hwc
->last_tag
== cpuc
->tags
[i
];
1000 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1002 static void x86_pmu_enable(struct pmu
*pmu
)
1004 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1005 struct perf_event
*event
;
1006 struct hw_perf_event
*hwc
;
1007 int i
, added
= cpuc
->n_added
;
1009 if (!x86_pmu_initialized())
1015 if (cpuc
->n_added
) {
1016 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1018 * apply assignment obtained either from
1019 * hw_perf_group_sched_in() or x86_pmu_enable()
1021 * step1: save events moving to new counters
1023 for (i
= 0; i
< n_running
; i
++) {
1024 event
= cpuc
->event_list
[i
];
1028 * we can avoid reprogramming counter if:
1029 * - assigned same counter as last time
1030 * - running on same CPU as last time
1031 * - no other event has used the counter since
1033 if (hwc
->idx
== -1 ||
1034 match_prev_assignment(hwc
, cpuc
, i
))
1038 * Ensure we don't accidentally enable a stopped
1039 * counter simply because we rescheduled.
1041 if (hwc
->state
& PERF_HES_STOPPED
)
1042 hwc
->state
|= PERF_HES_ARCH
;
1044 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1048 * step2: reprogram moved events into new counters
1050 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1051 event
= cpuc
->event_list
[i
];
1054 if (!match_prev_assignment(hwc
, cpuc
, i
))
1055 x86_assign_hw_event(event
, cpuc
, i
);
1056 else if (i
< n_running
)
1059 if (hwc
->state
& PERF_HES_ARCH
)
1062 x86_pmu_start(event
, PERF_EF_RELOAD
);
1065 perf_events_lapic_init();
1071 x86_pmu
.enable_all(added
);
1074 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1077 * Set the next IRQ period, based on the hwc->period_left value.
1078 * To be called with the event disabled in hw:
1080 int x86_perf_event_set_period(struct perf_event
*event
)
1082 struct hw_perf_event
*hwc
= &event
->hw
;
1083 s64 left
= local64_read(&hwc
->period_left
);
1084 s64 period
= hwc
->sample_period
;
1085 int ret
= 0, idx
= hwc
->idx
;
1087 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1091 * If we are way outside a reasonable range then just skip forward:
1093 if (unlikely(left
<= -period
)) {
1095 local64_set(&hwc
->period_left
, left
);
1096 hwc
->last_period
= period
;
1100 if (unlikely(left
<= 0)) {
1102 local64_set(&hwc
->period_left
, left
);
1103 hwc
->last_period
= period
;
1107 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1109 if (unlikely(left
< 2))
1112 if (left
> x86_pmu
.max_period
)
1113 left
= x86_pmu
.max_period
;
1115 if (x86_pmu
.limit_period
)
1116 left
= x86_pmu
.limit_period(event
, left
);
1118 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1120 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1121 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1123 * The hw event starts counting from this event offset,
1124 * mark it to be able to extra future deltas:
1126 local64_set(&hwc
->prev_count
, (u64
)-left
);
1128 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1132 * Due to erratum on certan cpu we need
1133 * a second write to be sure the register
1134 * is updated properly
1136 if (x86_pmu
.perfctr_second_write
) {
1137 wrmsrl(hwc
->event_base
,
1138 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1141 perf_event_update_userpage(event
);
1146 void x86_pmu_enable_event(struct perf_event
*event
)
1148 if (__this_cpu_read(cpu_hw_events
.enabled
))
1149 __x86_pmu_enable_event(&event
->hw
,
1150 ARCH_PERFMON_EVENTSEL_ENABLE
);
1154 * Add a single event to the PMU.
1156 * The event is added to the group of enabled events
1157 * but only if it can be scehduled with existing events.
1159 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1161 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1162 struct hw_perf_event
*hwc
;
1163 int assign
[X86_PMC_IDX_MAX
];
1168 n0
= cpuc
->n_events
;
1169 ret
= n
= collect_events(cpuc
, event
, false);
1173 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1174 if (!(flags
& PERF_EF_START
))
1175 hwc
->state
|= PERF_HES_ARCH
;
1178 * If group events scheduling transaction was started,
1179 * skip the schedulability test here, it will be performed
1180 * at commit time (->commit_txn) as a whole.
1182 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1185 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1189 * copy new assignment, now we know it is possible
1190 * will be used by hw_perf_enable()
1192 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1196 * Commit the collect_events() state. See x86_pmu_del() and
1200 cpuc
->n_added
+= n
- n0
;
1201 cpuc
->n_txn
+= n
- n0
;
1208 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1210 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1211 int idx
= event
->hw
.idx
;
1213 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1216 if (WARN_ON_ONCE(idx
== -1))
1219 if (flags
& PERF_EF_RELOAD
) {
1220 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1221 x86_perf_event_set_period(event
);
1224 event
->hw
.state
= 0;
1226 cpuc
->events
[idx
] = event
;
1227 __set_bit(idx
, cpuc
->active_mask
);
1228 __set_bit(idx
, cpuc
->running
);
1229 x86_pmu
.enable(event
);
1230 perf_event_update_userpage(event
);
1233 void perf_event_print_debug(void)
1235 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1237 struct cpu_hw_events
*cpuc
;
1238 unsigned long flags
;
1241 if (!x86_pmu
.num_counters
)
1244 local_irq_save(flags
);
1246 cpu
= smp_processor_id();
1247 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1249 if (x86_pmu
.version
>= 2) {
1250 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1251 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1252 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1253 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1256 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1257 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1258 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1259 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1260 if (x86_pmu
.pebs_constraints
) {
1261 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1262 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1264 if (x86_pmu
.lbr_nr
) {
1265 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1266 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1269 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1271 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1272 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1273 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1275 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1277 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1278 cpu
, idx
, pmc_ctrl
);
1279 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1280 cpu
, idx
, pmc_count
);
1281 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1282 cpu
, idx
, prev_left
);
1284 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1285 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1287 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1288 cpu
, idx
, pmc_count
);
1290 local_irq_restore(flags
);
1293 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1295 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1296 struct hw_perf_event
*hwc
= &event
->hw
;
1298 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1299 x86_pmu
.disable(event
);
1300 cpuc
->events
[hwc
->idx
] = NULL
;
1301 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1302 hwc
->state
|= PERF_HES_STOPPED
;
1305 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1307 * Drain the remaining delta count out of a event
1308 * that we are disabling:
1310 x86_perf_event_update(event
);
1311 hwc
->state
|= PERF_HES_UPTODATE
;
1315 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1317 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1321 * event is descheduled
1323 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1326 * If we're called during a txn, we don't need to do anything.
1327 * The events never got scheduled and ->cancel_txn will truncate
1330 * XXX assumes any ->del() called during a TXN will only be on
1331 * an event added during that same TXN.
1333 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1337 * Not a TXN, therefore cleanup properly.
1339 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1341 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1342 if (event
== cpuc
->event_list
[i
])
1346 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1349 /* If we have a newly added event; make sure to decrease n_added. */
1350 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1353 if (x86_pmu
.put_event_constraints
)
1354 x86_pmu
.put_event_constraints(cpuc
, event
);
1356 /* Delete the array entry. */
1357 while (++i
< cpuc
->n_events
) {
1358 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1359 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1363 perf_event_update_userpage(event
);
1366 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1368 struct perf_sample_data data
;
1369 struct cpu_hw_events
*cpuc
;
1370 struct perf_event
*event
;
1371 int idx
, handled
= 0;
1374 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1377 * Some chipsets need to unmask the LVTPC in a particular spot
1378 * inside the nmi handler. As a result, the unmasking was pushed
1379 * into all the nmi handlers.
1381 * This generic handler doesn't seem to have any issues where the
1382 * unmasking occurs so it was left at the top.
1384 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1386 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1387 if (!test_bit(idx
, cpuc
->active_mask
)) {
1389 * Though we deactivated the counter some cpus
1390 * might still deliver spurious interrupts still
1391 * in flight. Catch them:
1393 if (__test_and_clear_bit(idx
, cpuc
->running
))
1398 event
= cpuc
->events
[idx
];
1400 val
= x86_perf_event_update(event
);
1401 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1408 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1410 if (!x86_perf_event_set_period(event
))
1413 if (perf_event_overflow(event
, &data
, regs
))
1414 x86_pmu_stop(event
, 0);
1418 inc_irq_stat(apic_perf_irqs
);
1423 void perf_events_lapic_init(void)
1425 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1429 * Always use NMI for PMU
1431 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1435 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1442 * All PMUs/events that share this PMI handler should make sure to
1443 * increment active_events for their events.
1445 if (!atomic_read(&active_events
))
1448 start_clock
= sched_clock();
1449 ret
= x86_pmu
.handle_irq(regs
);
1450 finish_clock
= sched_clock();
1452 perf_sample_event_took(finish_clock
- start_clock
);
1456 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1458 struct event_constraint emptyconstraint
;
1459 struct event_constraint unconstrained
;
1462 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1464 unsigned int cpu
= (long)hcpu
;
1465 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1466 int i
, ret
= NOTIFY_OK
;
1468 switch (action
& ~CPU_TASKS_FROZEN
) {
1469 case CPU_UP_PREPARE
:
1470 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1471 cpuc
->kfree_on_online
[i
] = NULL
;
1472 if (x86_pmu
.cpu_prepare
)
1473 ret
= x86_pmu
.cpu_prepare(cpu
);
1477 if (x86_pmu
.cpu_starting
)
1478 x86_pmu
.cpu_starting(cpu
);
1482 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1483 kfree(cpuc
->kfree_on_online
[i
]);
1484 cpuc
->kfree_on_online
[i
] = NULL
;
1489 if (x86_pmu
.cpu_dying
)
1490 x86_pmu
.cpu_dying(cpu
);
1493 case CPU_UP_CANCELED
:
1495 if (x86_pmu
.cpu_dead
)
1496 x86_pmu
.cpu_dead(cpu
);
1506 static void __init
pmu_check_apic(void)
1512 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1513 pr_info("no hardware sampling interrupt available.\n");
1516 * If we have a PMU initialized but no APIC
1517 * interrupts, we cannot sample hardware
1518 * events (user-space has to fall back and
1519 * sample via a hrtimer based software event):
1521 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1525 static struct attribute_group x86_pmu_format_group
= {
1531 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1532 * out of events_attr attributes.
1534 static void __init
filter_events(struct attribute
**attrs
)
1536 struct device_attribute
*d
;
1537 struct perf_pmu_events_attr
*pmu_attr
;
1541 for (i
= 0; attrs
[i
]; i
++) {
1542 d
= (struct device_attribute
*)attrs
[i
];
1543 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1545 if (pmu_attr
->event_str
)
1547 if (x86_pmu
.event_map(i
+ offset
))
1550 for (j
= i
; attrs
[j
]; j
++)
1551 attrs
[j
] = attrs
[j
+ 1];
1553 /* Check the shifted attr. */
1557 * event_map() is index based, the attrs array is organized
1558 * by increasing event index. If we shift the events, then
1559 * we need to compensate for the event_map(), otherwise
1560 * we are looking up the wrong event in the map
1566 /* Merge two pointer arrays */
1567 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1569 struct attribute
**new;
1572 for (j
= 0; a
[j
]; j
++)
1574 for (i
= 0; b
[i
]; i
++)
1578 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1583 for (i
= 0; a
[i
]; i
++)
1585 for (i
= 0; b
[i
]; i
++)
1592 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1595 struct perf_pmu_events_attr
*pmu_attr
= \
1596 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1597 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1599 /* string trumps id */
1600 if (pmu_attr
->event_str
)
1601 return sprintf(page
, "%s", pmu_attr
->event_str
);
1603 return x86_pmu
.events_sysfs_show(page
, config
);
1606 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1607 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1608 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1609 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1610 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1611 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1612 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1613 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1614 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1615 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1617 static struct attribute
*empty_attrs
;
1619 static struct attribute
*events_attr
[] = {
1620 EVENT_PTR(CPU_CYCLES
),
1621 EVENT_PTR(INSTRUCTIONS
),
1622 EVENT_PTR(CACHE_REFERENCES
),
1623 EVENT_PTR(CACHE_MISSES
),
1624 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1625 EVENT_PTR(BRANCH_MISSES
),
1626 EVENT_PTR(BUS_CYCLES
),
1627 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1628 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1629 EVENT_PTR(REF_CPU_CYCLES
),
1633 static struct attribute_group x86_pmu_events_group
= {
1635 .attrs
= events_attr
,
1638 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1640 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1641 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1642 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1643 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1644 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1645 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1649 * We have whole page size to spend and just little data
1650 * to write, so we can safely use sprintf.
1652 ret
= sprintf(page
, "event=0x%02llx", event
);
1655 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1658 ret
+= sprintf(page
+ ret
, ",edge");
1661 ret
+= sprintf(page
+ ret
, ",pc");
1664 ret
+= sprintf(page
+ ret
, ",any");
1667 ret
+= sprintf(page
+ ret
, ",inv");
1670 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1672 ret
+= sprintf(page
+ ret
, "\n");
1677 static int __init
init_hw_perf_events(void)
1679 struct x86_pmu_quirk
*quirk
;
1682 pr_info("Performance Events: ");
1684 switch (boot_cpu_data
.x86_vendor
) {
1685 case X86_VENDOR_INTEL
:
1686 err
= intel_pmu_init();
1688 case X86_VENDOR_AMD
:
1689 err
= amd_pmu_init();
1695 pr_cont("no PMU driver, software events only.\n");
1701 /* sanity check that the hardware exists or is emulated */
1702 if (!check_hw_exists())
1705 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1707 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1709 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1712 if (!x86_pmu
.intel_ctrl
)
1713 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1715 perf_events_lapic_init();
1716 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1718 unconstrained
= (struct event_constraint
)
1719 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1720 0, x86_pmu
.num_counters
, 0, 0);
1722 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1724 if (x86_pmu
.event_attrs
)
1725 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1727 if (!x86_pmu
.events_sysfs_show
)
1728 x86_pmu_events_group
.attrs
= &empty_attrs
;
1730 filter_events(x86_pmu_events_group
.attrs
);
1732 if (x86_pmu
.cpu_events
) {
1733 struct attribute
**tmp
;
1735 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1737 x86_pmu_events_group
.attrs
= tmp
;
1740 pr_info("... version: %d\n", x86_pmu
.version
);
1741 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1742 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1743 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1744 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1745 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1746 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1748 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1749 perf_cpu_notifier(x86_pmu_notifier
);
1753 early_initcall(init_hw_perf_events
);
1755 static inline void x86_pmu_read(struct perf_event
*event
)
1757 x86_perf_event_update(event
);
1761 * Start group events scheduling transaction
1762 * Set the flag to make pmu::enable() not perform the
1763 * schedulability test, it will be performed at commit time
1765 * We only support PERF_PMU_TXN_ADD transactions. Save the
1766 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1769 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1771 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1773 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1775 cpuc
->txn_flags
= txn_flags
;
1776 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1779 perf_pmu_disable(pmu
);
1780 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1784 * Stop group events scheduling transaction
1785 * Clear the flag and pmu::enable() will perform the
1786 * schedulability test.
1788 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1790 unsigned int txn_flags
;
1791 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1793 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1795 txn_flags
= cpuc
->txn_flags
;
1796 cpuc
->txn_flags
= 0;
1797 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1801 * Truncate collected array by the number of events added in this
1802 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1804 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1805 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1806 perf_pmu_enable(pmu
);
1810 * Commit group events scheduling transaction
1811 * Perform the group schedulability test as a whole
1812 * Return 0 if success
1814 * Does not cancel the transaction on failure; expects the caller to do this.
1816 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1818 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1819 int assign
[X86_PMC_IDX_MAX
];
1822 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1824 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1825 cpuc
->txn_flags
= 0;
1831 if (!x86_pmu_initialized())
1834 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1839 * copy new assignment, now we know it is possible
1840 * will be used by hw_perf_enable()
1842 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1844 cpuc
->txn_flags
= 0;
1845 perf_pmu_enable(pmu
);
1849 * a fake_cpuc is used to validate event groups. Due to
1850 * the extra reg logic, we need to also allocate a fake
1851 * per_core and per_cpu structure. Otherwise, group events
1852 * using extra reg may conflict without the kernel being
1853 * able to catch this when the last event gets added to
1856 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1858 kfree(cpuc
->shared_regs
);
1862 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1864 struct cpu_hw_events
*cpuc
;
1865 int cpu
= raw_smp_processor_id();
1867 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1869 return ERR_PTR(-ENOMEM
);
1871 /* only needed, if we have extra_regs */
1872 if (x86_pmu
.extra_regs
) {
1873 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1874 if (!cpuc
->shared_regs
)
1880 free_fake_cpuc(cpuc
);
1881 return ERR_PTR(-ENOMEM
);
1885 * validate that we can schedule this event
1887 static int validate_event(struct perf_event
*event
)
1889 struct cpu_hw_events
*fake_cpuc
;
1890 struct event_constraint
*c
;
1893 fake_cpuc
= allocate_fake_cpuc();
1894 if (IS_ERR(fake_cpuc
))
1895 return PTR_ERR(fake_cpuc
);
1897 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
1899 if (!c
|| !c
->weight
)
1902 if (x86_pmu
.put_event_constraints
)
1903 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1905 free_fake_cpuc(fake_cpuc
);
1911 * validate a single event group
1913 * validation include:
1914 * - check events are compatible which each other
1915 * - events do not compete for the same counter
1916 * - number of events <= number of counters
1918 * validation ensures the group can be loaded onto the
1919 * PMU if it was the only group available.
1921 static int validate_group(struct perf_event
*event
)
1923 struct perf_event
*leader
= event
->group_leader
;
1924 struct cpu_hw_events
*fake_cpuc
;
1925 int ret
= -EINVAL
, n
;
1927 fake_cpuc
= allocate_fake_cpuc();
1928 if (IS_ERR(fake_cpuc
))
1929 return PTR_ERR(fake_cpuc
);
1931 * the event is not yet connected with its
1932 * siblings therefore we must first collect
1933 * existing siblings, then add the new event
1934 * before we can simulate the scheduling
1936 n
= collect_events(fake_cpuc
, leader
, true);
1940 fake_cpuc
->n_events
= n
;
1941 n
= collect_events(fake_cpuc
, event
, false);
1945 fake_cpuc
->n_events
= n
;
1947 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1950 free_fake_cpuc(fake_cpuc
);
1954 static int x86_pmu_event_init(struct perf_event
*event
)
1959 switch (event
->attr
.type
) {
1961 case PERF_TYPE_HARDWARE
:
1962 case PERF_TYPE_HW_CACHE
:
1969 err
= __x86_pmu_event_init(event
);
1972 * we temporarily connect event to its pmu
1973 * such that validate_group() can classify
1974 * it as an x86 event using is_x86_event()
1979 if (event
->group_leader
!= event
)
1980 err
= validate_group(event
);
1982 err
= validate_event(event
);
1988 event
->destroy(event
);
1991 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
1992 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
1997 static void refresh_pce(void *ignored
)
2000 load_mm_cr4(current
->mm
);
2003 static void x86_pmu_event_mapped(struct perf_event
*event
)
2005 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2008 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
2009 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2012 static void x86_pmu_event_unmapped(struct perf_event
*event
)
2017 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2020 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
2021 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2024 static int x86_pmu_event_idx(struct perf_event
*event
)
2026 int idx
= event
->hw
.idx
;
2028 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2031 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2032 idx
-= INTEL_PMC_IDX_FIXED
;
2039 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2040 struct device_attribute
*attr
,
2043 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2046 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2047 struct device_attribute
*attr
,
2048 const char *buf
, size_t count
)
2053 ret
= kstrtoul(buf
, 0, &val
);
2060 if (x86_pmu
.attr_rdpmc_broken
)
2063 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2065 * Changing into or out of always available, aka
2066 * perf-event-bypassing mode. This path is extremely slow,
2067 * but only root can trigger it, so it's okay.
2070 static_key_slow_inc(&rdpmc_always_available
);
2072 static_key_slow_dec(&rdpmc_always_available
);
2073 on_each_cpu(refresh_pce
, NULL
, 1);
2076 x86_pmu
.attr_rdpmc
= val
;
2081 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2083 static struct attribute
*x86_pmu_attrs
[] = {
2084 &dev_attr_rdpmc
.attr
,
2088 static struct attribute_group x86_pmu_attr_group
= {
2089 .attrs
= x86_pmu_attrs
,
2092 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2093 &x86_pmu_attr_group
,
2094 &x86_pmu_format_group
,
2095 &x86_pmu_events_group
,
2099 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2101 if (x86_pmu
.sched_task
)
2102 x86_pmu
.sched_task(ctx
, sched_in
);
2105 void perf_check_microcode(void)
2107 if (x86_pmu
.check_microcode
)
2108 x86_pmu
.check_microcode();
2110 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2112 static struct pmu pmu
= {
2113 .pmu_enable
= x86_pmu_enable
,
2114 .pmu_disable
= x86_pmu_disable
,
2116 .attr_groups
= x86_pmu_attr_groups
,
2118 .event_init
= x86_pmu_event_init
,
2120 .event_mapped
= x86_pmu_event_mapped
,
2121 .event_unmapped
= x86_pmu_event_unmapped
,
2125 .start
= x86_pmu_start
,
2126 .stop
= x86_pmu_stop
,
2127 .read
= x86_pmu_read
,
2129 .start_txn
= x86_pmu_start_txn
,
2130 .cancel_txn
= x86_pmu_cancel_txn
,
2131 .commit_txn
= x86_pmu_commit_txn
,
2133 .event_idx
= x86_pmu_event_idx
,
2134 .sched_task
= x86_pmu_sched_task
,
2135 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2138 void arch_perf_update_userpage(struct perf_event
*event
,
2139 struct perf_event_mmap_page
*userpg
, u64 now
)
2141 struct cyc2ns_data
*data
;
2143 userpg
->cap_user_time
= 0;
2144 userpg
->cap_user_time_zero
= 0;
2145 userpg
->cap_user_rdpmc
=
2146 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2147 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2149 if (!sched_clock_stable())
2152 data
= cyc2ns_read_begin();
2155 * Internal timekeeping for enabled/running/stopped times
2156 * is always in the local_clock domain.
2158 userpg
->cap_user_time
= 1;
2159 userpg
->time_mult
= data
->cyc2ns_mul
;
2160 userpg
->time_shift
= data
->cyc2ns_shift
;
2161 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2164 * cap_user_time_zero doesn't make sense when we're using a different
2165 * time base for the records.
2167 if (event
->clock
== &local_clock
) {
2168 userpg
->cap_user_time_zero
= 1;
2169 userpg
->time_zero
= data
->cyc2ns_offset
;
2172 cyc2ns_read_end(data
);
2179 static int backtrace_stack(void *data
, char *name
)
2184 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
2186 struct perf_callchain_entry
*entry
= data
;
2188 perf_callchain_store(entry
, addr
);
2191 static const struct stacktrace_ops backtrace_ops
= {
2192 .stack
= backtrace_stack
,
2193 .address
= backtrace_address
,
2194 .walk_stack
= print_context_stack_bp
,
2198 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2200 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2201 /* TODO: We don't support guest os callchain now */
2205 perf_callchain_store(entry
, regs
->ip
);
2207 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2211 valid_user_frame(const void __user
*fp
, unsigned long size
)
2213 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2216 static unsigned long get_segment_base(unsigned int segment
)
2218 struct desc_struct
*desc
;
2219 int idx
= segment
>> 3;
2221 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2222 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2223 struct ldt_struct
*ldt
;
2225 if (idx
> LDT_ENTRIES
)
2228 /* IRQs are off, so this synchronizes with smp_store_release */
2229 ldt
= lockless_dereference(current
->active_mm
->context
.ldt
);
2230 if (!ldt
|| idx
> ldt
->size
)
2233 desc
= &ldt
->entries
[idx
];
2238 if (idx
> GDT_ENTRIES
)
2241 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2244 return get_desc_base(desc
);
2247 #ifdef CONFIG_IA32_EMULATION
2249 #include <asm/compat.h>
2252 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2254 /* 32-bit process in 64-bit kernel. */
2255 unsigned long ss_base
, cs_base
;
2256 struct stack_frame_ia32 frame
;
2257 const void __user
*fp
;
2259 if (!test_thread_flag(TIF_IA32
))
2262 cs_base
= get_segment_base(regs
->cs
);
2263 ss_base
= get_segment_base(regs
->ss
);
2265 fp
= compat_ptr(ss_base
+ regs
->bp
);
2266 pagefault_disable();
2267 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2268 unsigned long bytes
;
2269 frame
.next_frame
= 0;
2270 frame
.return_address
= 0;
2272 if (!access_ok(VERIFY_READ
, fp
, 8))
2275 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2278 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2282 if (!valid_user_frame(fp
, sizeof(frame
)))
2285 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2286 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2293 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2300 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2302 struct stack_frame frame
;
2303 const void __user
*fp
;
2305 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2306 /* TODO: We don't support guest os callchain now */
2311 * We don't know what to do with VM86 stacks.. ignore them for now.
2313 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2316 fp
= (void __user
*)regs
->bp
;
2318 perf_callchain_store(entry
, regs
->ip
);
2323 if (perf_callchain_user32(regs
, entry
))
2326 pagefault_disable();
2327 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2328 unsigned long bytes
;
2329 frame
.next_frame
= NULL
;
2330 frame
.return_address
= 0;
2332 if (!access_ok(VERIFY_READ
, fp
, 16))
2335 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 8);
2338 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+8, 8);
2342 if (!valid_user_frame(fp
, sizeof(frame
)))
2345 perf_callchain_store(entry
, frame
.return_address
);
2346 fp
= (void __user
*)frame
.next_frame
;
2352 * Deal with code segment offsets for the various execution modes:
2354 * VM86 - the good olde 16 bit days, where the linear address is
2355 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2357 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2358 * to figure out what the 32bit base address is.
2360 * X32 - has TIF_X32 set, but is running in x86_64
2362 * X86_64 - CS,DS,SS,ES are all zero based.
2364 static unsigned long code_segment_base(struct pt_regs
*regs
)
2367 * For IA32 we look at the GDT/LDT segment base to convert the
2368 * effective IP to a linear address.
2371 #ifdef CONFIG_X86_32
2373 * If we are in VM86 mode, add the segment offset to convert to a
2376 if (regs
->flags
& X86_VM_MASK
)
2377 return 0x10 * regs
->cs
;
2379 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2380 return get_segment_base(regs
->cs
);
2382 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2383 regs
->cs
!= __USER32_CS
)
2384 return get_segment_base(regs
->cs
);
2389 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2391 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2392 return perf_guest_cbs
->get_guest_ip();
2394 return regs
->ip
+ code_segment_base(regs
);
2397 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2401 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2402 if (perf_guest_cbs
->is_user_mode())
2403 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2405 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2407 if (user_mode(regs
))
2408 misc
|= PERF_RECORD_MISC_USER
;
2410 misc
|= PERF_RECORD_MISC_KERNEL
;
2413 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2414 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2419 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2421 cap
->version
= x86_pmu
.version
;
2422 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2423 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2424 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2425 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2426 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2427 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2429 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);