2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched.h>
24 #include <linux/uaccess.h>
25 #include <linux/slab.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
28 #include <linux/device.h>
31 #include <asm/stacktrace.h>
34 #include <asm/alternative.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
37 #include <asm/timer.h>
41 #include "perf_event.h"
43 struct x86_pmu x86_pmu __read_mostly
;
45 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
49 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
51 u64 __read_mostly hw_cache_event_ids
52 [PERF_COUNT_HW_CACHE_MAX
]
53 [PERF_COUNT_HW_CACHE_OP_MAX
]
54 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
55 u64 __read_mostly hw_cache_extra_regs
56 [PERF_COUNT_HW_CACHE_MAX
]
57 [PERF_COUNT_HW_CACHE_OP_MAX
]
58 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
61 * Propagate event elapsed time into the generic event.
62 * Can only be executed on the CPU where the event is active.
63 * Returns the delta events processed.
65 u64
x86_perf_event_update(struct perf_event
*event
)
67 struct hw_perf_event
*hwc
= &event
->hw
;
68 int shift
= 64 - x86_pmu
.cntval_bits
;
69 u64 prev_raw_count
, new_raw_count
;
73 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
77 * Careful: an NMI might modify the previous event value.
79 * Our tactic to handle this is to first atomically read and
80 * exchange a new raw count - then add that new-prev delta
81 * count to the generic event atomically:
84 prev_raw_count
= local64_read(&hwc
->prev_count
);
85 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
87 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
88 new_raw_count
) != prev_raw_count
)
92 * Now we have the new raw value and have updated the prev
93 * timestamp already. We can now calculate the elapsed delta
94 * (event-)time and add that to the generic event.
96 * Careful, not all hw sign-extends above the physical width
99 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
102 local64_add(delta
, &event
->count
);
103 local64_sub(delta
, &hwc
->period_left
);
105 return new_raw_count
;
109 * Find and validate any extra registers to set up.
111 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
113 struct hw_perf_event_extra
*reg
;
114 struct extra_reg
*er
;
116 reg
= &event
->hw
.extra_reg
;
118 if (!x86_pmu
.extra_regs
)
121 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
122 if (er
->event
!= (config
& er
->config_mask
))
124 if (event
->attr
.config1
& ~er
->valid_mask
)
126 /* Check if the extra msrs can be safely accessed*/
127 if (!er
->extra_msr_access
)
131 reg
->config
= event
->attr
.config1
;
138 static atomic_t active_events
;
139 static atomic_t pmc_refcount
;
140 static DEFINE_MUTEX(pmc_reserve_mutex
);
142 #ifdef CONFIG_X86_LOCAL_APIC
144 static bool reserve_pmc_hardware(void)
148 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
149 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
153 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
154 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
161 for (i
--; i
>= 0; i
--)
162 release_evntsel_nmi(x86_pmu_config_addr(i
));
164 i
= x86_pmu
.num_counters
;
167 for (i
--; i
>= 0; i
--)
168 release_perfctr_nmi(x86_pmu_event_addr(i
));
173 static void release_pmc_hardware(void)
177 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
178 release_perfctr_nmi(x86_pmu_event_addr(i
));
179 release_evntsel_nmi(x86_pmu_config_addr(i
));
185 static bool reserve_pmc_hardware(void) { return true; }
186 static void release_pmc_hardware(void) {}
190 static bool check_hw_exists(void)
192 u64 val
, val_fail
, val_new
= ~0;
193 int i
, reg
, reg_fail
, ret
= 0;
198 * Check to see if the BIOS enabled any of the counters, if so
201 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
202 reg
= x86_pmu_config_addr(i
);
203 ret
= rdmsrl_safe(reg
, &val
);
206 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
215 if (x86_pmu
.num_counters_fixed
) {
216 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
217 ret
= rdmsrl_safe(reg
, &val
);
220 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
221 if (val
& (0x03 << i
*4)) {
230 * If all the counters are enabled, the below test will always
231 * fail. The tools will also become useless in this scenario.
232 * Just fail and disable the hardware counters.
235 if (reg_safe
== -1) {
241 * Read the current value, change it and read it back to see if it
242 * matches, this is needed to detect certain hardware emulators
243 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
245 reg
= x86_pmu_event_addr(reg_safe
);
246 if (rdmsrl_safe(reg
, &val
))
249 ret
= wrmsrl_safe(reg
, val
);
250 ret
|= rdmsrl_safe(reg
, &val_new
);
251 if (ret
|| val
!= val_new
)
255 * We still allow the PMU driver to operate:
258 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
259 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
266 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
267 pr_cont("PMU not available due to virtualization, using software events only.\n");
269 pr_cont("Broken PMU hardware detected, using software events only.\n");
270 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
277 static void hw_perf_event_destroy(struct perf_event
*event
)
279 x86_release_hardware();
280 atomic_dec(&active_events
);
283 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
285 hw_perf_event_destroy(event
);
287 /* undo the lbr/bts event accounting */
288 x86_del_exclusive(x86_lbr_exclusive_lbr
);
291 static inline int x86_pmu_initialized(void)
293 return x86_pmu
.handle_irq
!= NULL
;
297 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
299 struct perf_event_attr
*attr
= &event
->attr
;
300 unsigned int cache_type
, cache_op
, cache_result
;
303 config
= attr
->config
;
305 cache_type
= (config
>> 0) & 0xff;
306 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
309 cache_op
= (config
>> 8) & 0xff;
310 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
313 cache_result
= (config
>> 16) & 0xff;
314 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
317 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
326 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
327 return x86_pmu_extra_regs(val
, event
);
330 int x86_reserve_hardware(void)
334 if (!atomic_inc_not_zero(&pmc_refcount
)) {
335 mutex_lock(&pmc_reserve_mutex
);
336 if (atomic_read(&pmc_refcount
) == 0) {
337 if (!reserve_pmc_hardware())
340 reserve_ds_buffers();
343 atomic_inc(&pmc_refcount
);
344 mutex_unlock(&pmc_reserve_mutex
);
350 void x86_release_hardware(void)
352 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
353 release_pmc_hardware();
354 release_ds_buffers();
355 mutex_unlock(&pmc_reserve_mutex
);
360 * Check if we can create event of a certain type (that no conflicting events
363 int x86_add_exclusive(unsigned int what
)
367 if (x86_pmu
.lbr_pt_coexist
)
370 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
371 mutex_lock(&pmc_reserve_mutex
);
372 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
373 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
376 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
377 mutex_unlock(&pmc_reserve_mutex
);
380 atomic_inc(&active_events
);
384 mutex_unlock(&pmc_reserve_mutex
);
388 void x86_del_exclusive(unsigned int what
)
390 if (x86_pmu
.lbr_pt_coexist
)
393 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
394 atomic_dec(&active_events
);
397 int x86_setup_perfctr(struct perf_event
*event
)
399 struct perf_event_attr
*attr
= &event
->attr
;
400 struct hw_perf_event
*hwc
= &event
->hw
;
403 if (!is_sampling_event(event
)) {
404 hwc
->sample_period
= x86_pmu
.max_period
;
405 hwc
->last_period
= hwc
->sample_period
;
406 local64_set(&hwc
->period_left
, hwc
->sample_period
);
409 if (attr
->type
== PERF_TYPE_RAW
)
410 return x86_pmu_extra_regs(event
->attr
.config
, event
);
412 if (attr
->type
== PERF_TYPE_HW_CACHE
)
413 return set_ext_hw_attr(hwc
, event
);
415 if (attr
->config
>= x86_pmu
.max_events
)
421 config
= x86_pmu
.event_map(attr
->config
);
432 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
433 !attr
->freq
&& hwc
->sample_period
== 1) {
434 /* BTS is not supported by this architecture. */
435 if (!x86_pmu
.bts_active
)
438 /* BTS is currently only allowed for user-mode. */
439 if (!attr
->exclude_kernel
)
442 /* disallow bts if conflicting events are present */
443 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
446 event
->destroy
= hw_perf_lbr_event_destroy
;
449 hwc
->config
|= config
;
455 * check that branch_sample_type is compatible with
456 * settings needed for precise_ip > 1 which implies
457 * using the LBR to capture ALL taken branches at the
458 * priv levels of the measurement
460 static inline int precise_br_compat(struct perf_event
*event
)
462 u64 m
= event
->attr
.branch_sample_type
;
465 /* must capture all branches */
466 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
469 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
471 if (!event
->attr
.exclude_user
)
472 b
|= PERF_SAMPLE_BRANCH_USER
;
474 if (!event
->attr
.exclude_kernel
)
475 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
478 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
484 int x86_pmu_hw_config(struct perf_event
*event
)
486 if (event
->attr
.precise_ip
) {
489 /* Support for constant skid */
490 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
493 /* Support for IP fixup */
494 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
497 if (x86_pmu
.pebs_prec_dist
)
501 if (event
->attr
.precise_ip
> precise
)
505 * check that PEBS LBR correction does not conflict with
506 * whatever the user is asking with attr->branch_sample_type
508 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
509 u64
*br_type
= &event
->attr
.branch_sample_type
;
511 if (has_branch_stack(event
)) {
512 if (!precise_br_compat(event
))
515 /* branch_sample_type is compatible */
519 * user did not specify branch_sample_type
521 * For PEBS fixups, we capture all
522 * the branches at the priv level of the
525 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
527 if (!event
->attr
.exclude_user
)
528 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
530 if (!event
->attr
.exclude_kernel
)
531 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
535 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
536 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
540 * (keep 'enabled' bit clear for now)
542 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
545 * Count user and OS events unless requested not to
547 if (!event
->attr
.exclude_user
)
548 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
549 if (!event
->attr
.exclude_kernel
)
550 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
552 if (event
->attr
.type
== PERF_TYPE_RAW
)
553 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
555 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
556 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
557 event
->attr
.sample_period
)
561 return x86_setup_perfctr(event
);
565 * Setup the hardware configuration for a given attr_type
567 static int __x86_pmu_event_init(struct perf_event
*event
)
571 if (!x86_pmu_initialized())
574 err
= x86_reserve_hardware();
578 atomic_inc(&active_events
);
579 event
->destroy
= hw_perf_event_destroy
;
582 event
->hw
.last_cpu
= -1;
583 event
->hw
.last_tag
= ~0ULL;
586 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
587 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
589 return x86_pmu
.hw_config(event
);
592 void x86_pmu_disable_all(void)
594 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
597 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
600 if (!test_bit(idx
, cpuc
->active_mask
))
602 rdmsrl(x86_pmu_config_addr(idx
), val
);
603 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
605 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
606 wrmsrl(x86_pmu_config_addr(idx
), val
);
611 * There may be PMI landing after enabled=0. The PMI hitting could be before or
614 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
615 * It will not be re-enabled in the NMI handler again, because enabled=0. After
616 * handling the NMI, disable_all will be called, which will not change the
617 * state either. If PMI hits after disable_all, the PMU is already disabled
618 * before entering NMI handler. The NMI handler will not change the state
621 * So either situation is harmless.
623 static void x86_pmu_disable(struct pmu
*pmu
)
625 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
627 if (!x86_pmu_initialized())
637 x86_pmu
.disable_all();
640 void x86_pmu_enable_all(int added
)
642 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
645 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
646 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
648 if (!test_bit(idx
, cpuc
->active_mask
))
651 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
655 static struct pmu pmu
;
657 static inline int is_x86_event(struct perf_event
*event
)
659 return event
->pmu
== &pmu
;
663 * Event scheduler state:
665 * Assign events iterating over all events and counters, beginning
666 * with events with least weights first. Keep the current iterator
667 * state in struct sched_state.
671 int event
; /* event index */
672 int counter
; /* counter index */
673 int unassigned
; /* number of events to be assigned left */
674 int nr_gp
; /* number of GP counters used */
675 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
678 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
679 #define SCHED_STATES_MAX 2
686 struct event_constraint
**constraints
;
687 struct sched_state state
;
688 struct sched_state saved
[SCHED_STATES_MAX
];
692 * Initialize interator that runs through all events and counters.
694 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
695 int num
, int wmin
, int wmax
, int gpmax
)
699 memset(sched
, 0, sizeof(*sched
));
700 sched
->max_events
= num
;
701 sched
->max_weight
= wmax
;
702 sched
->max_gp
= gpmax
;
703 sched
->constraints
= constraints
;
705 for (idx
= 0; idx
< num
; idx
++) {
706 if (constraints
[idx
]->weight
== wmin
)
710 sched
->state
.event
= idx
; /* start with min weight */
711 sched
->state
.weight
= wmin
;
712 sched
->state
.unassigned
= num
;
715 static void perf_sched_save_state(struct perf_sched
*sched
)
717 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
720 sched
->saved
[sched
->saved_states
] = sched
->state
;
721 sched
->saved_states
++;
724 static bool perf_sched_restore_state(struct perf_sched
*sched
)
726 if (!sched
->saved_states
)
729 sched
->saved_states
--;
730 sched
->state
= sched
->saved
[sched
->saved_states
];
732 /* continue with next counter: */
733 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
739 * Select a counter for the current event to schedule. Return true on
742 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
744 struct event_constraint
*c
;
747 if (!sched
->state
.unassigned
)
750 if (sched
->state
.event
>= sched
->max_events
)
753 c
= sched
->constraints
[sched
->state
.event
];
754 /* Prefer fixed purpose counters */
755 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
756 idx
= INTEL_PMC_IDX_FIXED
;
757 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
758 if (!__test_and_set_bit(idx
, sched
->state
.used
))
763 /* Grab the first unused counter starting with idx */
764 idx
= sched
->state
.counter
;
765 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
766 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
767 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
777 sched
->state
.counter
= idx
;
780 perf_sched_save_state(sched
);
785 static bool perf_sched_find_counter(struct perf_sched
*sched
)
787 while (!__perf_sched_find_counter(sched
)) {
788 if (!perf_sched_restore_state(sched
))
796 * Go through all unassigned events and find the next one to schedule.
797 * Take events with the least weight first. Return true on success.
799 static bool perf_sched_next_event(struct perf_sched
*sched
)
801 struct event_constraint
*c
;
803 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
808 sched
->state
.event
++;
809 if (sched
->state
.event
>= sched
->max_events
) {
811 sched
->state
.event
= 0;
812 sched
->state
.weight
++;
813 if (sched
->state
.weight
> sched
->max_weight
)
816 c
= sched
->constraints
[sched
->state
.event
];
817 } while (c
->weight
!= sched
->state
.weight
);
819 sched
->state
.counter
= 0; /* start with first counter */
825 * Assign a counter for each event.
827 int perf_assign_events(struct event_constraint
**constraints
, int n
,
828 int wmin
, int wmax
, int gpmax
, int *assign
)
830 struct perf_sched sched
;
832 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
835 if (!perf_sched_find_counter(&sched
))
838 assign
[sched
.state
.event
] = sched
.state
.counter
;
839 } while (perf_sched_next_event(&sched
));
841 return sched
.state
.unassigned
;
843 EXPORT_SYMBOL_GPL(perf_assign_events
);
845 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
847 struct event_constraint
*c
;
848 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
849 struct perf_event
*e
;
850 int i
, wmin
, wmax
, unsched
= 0;
851 struct hw_perf_event
*hwc
;
853 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
855 if (x86_pmu
.start_scheduling
)
856 x86_pmu
.start_scheduling(cpuc
);
858 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
859 cpuc
->event_constraint
[i
] = NULL
;
860 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
861 cpuc
->event_constraint
[i
] = c
;
863 wmin
= min(wmin
, c
->weight
);
864 wmax
= max(wmax
, c
->weight
);
868 * fastpath, try to reuse previous register
870 for (i
= 0; i
< n
; i
++) {
871 hwc
= &cpuc
->event_list
[i
]->hw
;
872 c
= cpuc
->event_constraint
[i
];
878 /* constraint still honored */
879 if (!test_bit(hwc
->idx
, c
->idxmsk
))
882 /* not already used */
883 if (test_bit(hwc
->idx
, used_mask
))
886 __set_bit(hwc
->idx
, used_mask
);
888 assign
[i
] = hwc
->idx
;
893 int gpmax
= x86_pmu
.num_counters
;
896 * Do not allow scheduling of more than half the available
899 * This helps avoid counter starvation of sibling thread by
900 * ensuring at most half the counters cannot be in exclusive
901 * mode. There is no designated counters for the limits. Any
902 * N/2 counters can be used. This helps with events with
903 * specific counter constraints.
905 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
906 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
909 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
910 wmax
, gpmax
, assign
);
914 * In case of success (unsched = 0), mark events as committed,
915 * so we do not put_constraint() in case new events are added
916 * and fail to be scheduled
918 * We invoke the lower level commit callback to lock the resource
920 * We do not need to do all of this in case we are called to
921 * validate an event group (assign == NULL)
923 if (!unsched
&& assign
) {
924 for (i
= 0; i
< n
; i
++) {
925 e
= cpuc
->event_list
[i
];
926 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
927 if (x86_pmu
.commit_scheduling
)
928 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
931 for (i
= 0; i
< n
; i
++) {
932 e
= cpuc
->event_list
[i
];
934 * do not put_constraint() on comitted events,
935 * because they are good to go
937 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
941 * release events that failed scheduling
943 if (x86_pmu
.put_event_constraints
)
944 x86_pmu
.put_event_constraints(cpuc
, e
);
948 if (x86_pmu
.stop_scheduling
)
949 x86_pmu
.stop_scheduling(cpuc
);
951 return unsched
? -EINVAL
: 0;
955 * dogrp: true if must collect siblings events (group)
956 * returns total number of events and error code
958 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
960 struct perf_event
*event
;
963 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
965 /* current number of events already accepted */
968 if (is_x86_event(leader
)) {
971 cpuc
->event_list
[n
] = leader
;
977 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
978 if (!is_x86_event(event
) ||
979 event
->state
<= PERF_EVENT_STATE_OFF
)
985 cpuc
->event_list
[n
] = event
;
991 static inline void x86_assign_hw_event(struct perf_event
*event
,
992 struct cpu_hw_events
*cpuc
, int i
)
994 struct hw_perf_event
*hwc
= &event
->hw
;
996 hwc
->idx
= cpuc
->assign
[i
];
997 hwc
->last_cpu
= smp_processor_id();
998 hwc
->last_tag
= ++cpuc
->tags
[i
];
1000 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
1001 hwc
->config_base
= 0;
1002 hwc
->event_base
= 0;
1003 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
1004 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1005 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
1006 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
1008 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
1009 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1010 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1014 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1015 struct cpu_hw_events
*cpuc
,
1018 return hwc
->idx
== cpuc
->assign
[i
] &&
1019 hwc
->last_cpu
== smp_processor_id() &&
1020 hwc
->last_tag
== cpuc
->tags
[i
];
1023 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1025 static void x86_pmu_enable(struct pmu
*pmu
)
1027 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1028 struct perf_event
*event
;
1029 struct hw_perf_event
*hwc
;
1030 int i
, added
= cpuc
->n_added
;
1032 if (!x86_pmu_initialized())
1038 if (cpuc
->n_added
) {
1039 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1041 * apply assignment obtained either from
1042 * hw_perf_group_sched_in() or x86_pmu_enable()
1044 * step1: save events moving to new counters
1046 for (i
= 0; i
< n_running
; i
++) {
1047 event
= cpuc
->event_list
[i
];
1051 * we can avoid reprogramming counter if:
1052 * - assigned same counter as last time
1053 * - running on same CPU as last time
1054 * - no other event has used the counter since
1056 if (hwc
->idx
== -1 ||
1057 match_prev_assignment(hwc
, cpuc
, i
))
1061 * Ensure we don't accidentally enable a stopped
1062 * counter simply because we rescheduled.
1064 if (hwc
->state
& PERF_HES_STOPPED
)
1065 hwc
->state
|= PERF_HES_ARCH
;
1067 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1071 * step2: reprogram moved events into new counters
1073 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1074 event
= cpuc
->event_list
[i
];
1077 if (!match_prev_assignment(hwc
, cpuc
, i
))
1078 x86_assign_hw_event(event
, cpuc
, i
);
1079 else if (i
< n_running
)
1082 if (hwc
->state
& PERF_HES_ARCH
)
1085 x86_pmu_start(event
, PERF_EF_RELOAD
);
1088 perf_events_lapic_init();
1094 x86_pmu
.enable_all(added
);
1097 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1100 * Set the next IRQ period, based on the hwc->period_left value.
1101 * To be called with the event disabled in hw:
1103 int x86_perf_event_set_period(struct perf_event
*event
)
1105 struct hw_perf_event
*hwc
= &event
->hw
;
1106 s64 left
= local64_read(&hwc
->period_left
);
1107 s64 period
= hwc
->sample_period
;
1108 int ret
= 0, idx
= hwc
->idx
;
1110 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1114 * If we are way outside a reasonable range then just skip forward:
1116 if (unlikely(left
<= -period
)) {
1118 local64_set(&hwc
->period_left
, left
);
1119 hwc
->last_period
= period
;
1123 if (unlikely(left
<= 0)) {
1125 local64_set(&hwc
->period_left
, left
);
1126 hwc
->last_period
= period
;
1130 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1132 if (unlikely(left
< 2))
1135 if (left
> x86_pmu
.max_period
)
1136 left
= x86_pmu
.max_period
;
1138 if (x86_pmu
.limit_period
)
1139 left
= x86_pmu
.limit_period(event
, left
);
1141 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1143 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1144 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1146 * The hw event starts counting from this event offset,
1147 * mark it to be able to extra future deltas:
1149 local64_set(&hwc
->prev_count
, (u64
)-left
);
1151 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1155 * Due to erratum on certan cpu we need
1156 * a second write to be sure the register
1157 * is updated properly
1159 if (x86_pmu
.perfctr_second_write
) {
1160 wrmsrl(hwc
->event_base
,
1161 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1164 perf_event_update_userpage(event
);
1169 void x86_pmu_enable_event(struct perf_event
*event
)
1171 if (__this_cpu_read(cpu_hw_events
.enabled
))
1172 __x86_pmu_enable_event(&event
->hw
,
1173 ARCH_PERFMON_EVENTSEL_ENABLE
);
1177 * Add a single event to the PMU.
1179 * The event is added to the group of enabled events
1180 * but only if it can be scehduled with existing events.
1182 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1184 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1185 struct hw_perf_event
*hwc
;
1186 int assign
[X86_PMC_IDX_MAX
];
1191 n0
= cpuc
->n_events
;
1192 ret
= n
= collect_events(cpuc
, event
, false);
1196 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1197 if (!(flags
& PERF_EF_START
))
1198 hwc
->state
|= PERF_HES_ARCH
;
1201 * If group events scheduling transaction was started,
1202 * skip the schedulability test here, it will be performed
1203 * at commit time (->commit_txn) as a whole.
1205 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1208 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1212 * copy new assignment, now we know it is possible
1213 * will be used by hw_perf_enable()
1215 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1219 * Commit the collect_events() state. See x86_pmu_del() and
1223 cpuc
->n_added
+= n
- n0
;
1224 cpuc
->n_txn
+= n
- n0
;
1231 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1233 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1234 int idx
= event
->hw
.idx
;
1236 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1239 if (WARN_ON_ONCE(idx
== -1))
1242 if (flags
& PERF_EF_RELOAD
) {
1243 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1244 x86_perf_event_set_period(event
);
1247 event
->hw
.state
= 0;
1249 cpuc
->events
[idx
] = event
;
1250 __set_bit(idx
, cpuc
->active_mask
);
1251 __set_bit(idx
, cpuc
->running
);
1252 x86_pmu
.enable(event
);
1253 perf_event_update_userpage(event
);
1256 void perf_event_print_debug(void)
1258 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1260 struct cpu_hw_events
*cpuc
;
1261 unsigned long flags
;
1264 if (!x86_pmu
.num_counters
)
1267 local_irq_save(flags
);
1269 cpu
= smp_processor_id();
1270 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1272 if (x86_pmu
.version
>= 2) {
1273 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1274 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1275 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1276 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1279 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1280 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1281 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1282 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1283 if (x86_pmu
.pebs_constraints
) {
1284 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1285 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1287 if (x86_pmu
.lbr_nr
) {
1288 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1289 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1292 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1294 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1295 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1296 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1298 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1300 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1301 cpu
, idx
, pmc_ctrl
);
1302 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1303 cpu
, idx
, pmc_count
);
1304 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1305 cpu
, idx
, prev_left
);
1307 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1308 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1310 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1311 cpu
, idx
, pmc_count
);
1313 local_irq_restore(flags
);
1316 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1318 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1319 struct hw_perf_event
*hwc
= &event
->hw
;
1321 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1322 x86_pmu
.disable(event
);
1323 cpuc
->events
[hwc
->idx
] = NULL
;
1324 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1325 hwc
->state
|= PERF_HES_STOPPED
;
1328 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1330 * Drain the remaining delta count out of a event
1331 * that we are disabling:
1333 x86_perf_event_update(event
);
1334 hwc
->state
|= PERF_HES_UPTODATE
;
1338 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1340 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1344 * event is descheduled
1346 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1349 * If we're called during a txn, we don't need to do anything.
1350 * The events never got scheduled and ->cancel_txn will truncate
1353 * XXX assumes any ->del() called during a TXN will only be on
1354 * an event added during that same TXN.
1356 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1360 * Not a TXN, therefore cleanup properly.
1362 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1364 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1365 if (event
== cpuc
->event_list
[i
])
1369 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1372 /* If we have a newly added event; make sure to decrease n_added. */
1373 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1376 if (x86_pmu
.put_event_constraints
)
1377 x86_pmu
.put_event_constraints(cpuc
, event
);
1379 /* Delete the array entry. */
1380 while (++i
< cpuc
->n_events
) {
1381 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1382 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1386 perf_event_update_userpage(event
);
1389 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1391 struct perf_sample_data data
;
1392 struct cpu_hw_events
*cpuc
;
1393 struct perf_event
*event
;
1394 int idx
, handled
= 0;
1397 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1400 * Some chipsets need to unmask the LVTPC in a particular spot
1401 * inside the nmi handler. As a result, the unmasking was pushed
1402 * into all the nmi handlers.
1404 * This generic handler doesn't seem to have any issues where the
1405 * unmasking occurs so it was left at the top.
1407 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1409 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1410 if (!test_bit(idx
, cpuc
->active_mask
)) {
1412 * Though we deactivated the counter some cpus
1413 * might still deliver spurious interrupts still
1414 * in flight. Catch them:
1416 if (__test_and_clear_bit(idx
, cpuc
->running
))
1421 event
= cpuc
->events
[idx
];
1423 val
= x86_perf_event_update(event
);
1424 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1431 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1433 if (!x86_perf_event_set_period(event
))
1436 if (perf_event_overflow(event
, &data
, regs
))
1437 x86_pmu_stop(event
, 0);
1441 inc_irq_stat(apic_perf_irqs
);
1446 void perf_events_lapic_init(void)
1448 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1452 * Always use NMI for PMU
1454 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1458 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1465 * All PMUs/events that share this PMI handler should make sure to
1466 * increment active_events for their events.
1468 if (!atomic_read(&active_events
))
1471 start_clock
= sched_clock();
1472 ret
= x86_pmu
.handle_irq(regs
);
1473 finish_clock
= sched_clock();
1475 perf_sample_event_took(finish_clock
- start_clock
);
1479 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1481 struct event_constraint emptyconstraint
;
1482 struct event_constraint unconstrained
;
1484 static int x86_pmu_prepare_cpu(unsigned int cpu
)
1486 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1489 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1490 cpuc
->kfree_on_online
[i
] = NULL
;
1491 if (x86_pmu
.cpu_prepare
)
1492 return x86_pmu
.cpu_prepare(cpu
);
1496 static int x86_pmu_dead_cpu(unsigned int cpu
)
1498 if (x86_pmu
.cpu_dead
)
1499 x86_pmu
.cpu_dead(cpu
);
1503 static int x86_pmu_online_cpu(unsigned int cpu
)
1505 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1508 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1509 kfree(cpuc
->kfree_on_online
[i
]);
1510 cpuc
->kfree_on_online
[i
] = NULL
;
1515 static int x86_pmu_starting_cpu(unsigned int cpu
)
1517 if (x86_pmu
.cpu_starting
)
1518 x86_pmu
.cpu_starting(cpu
);
1522 static int x86_pmu_dying_cpu(unsigned int cpu
)
1524 if (x86_pmu
.cpu_dying
)
1525 x86_pmu
.cpu_dying(cpu
);
1529 static void __init
pmu_check_apic(void)
1531 if (boot_cpu_has(X86_FEATURE_APIC
))
1535 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1536 pr_info("no hardware sampling interrupt available.\n");
1539 * If we have a PMU initialized but no APIC
1540 * interrupts, we cannot sample hardware
1541 * events (user-space has to fall back and
1542 * sample via a hrtimer based software event):
1544 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1548 static struct attribute_group x86_pmu_format_group
= {
1554 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1555 * out of events_attr attributes.
1557 static void __init
filter_events(struct attribute
**attrs
)
1559 struct device_attribute
*d
;
1560 struct perf_pmu_events_attr
*pmu_attr
;
1564 for (i
= 0; attrs
[i
]; i
++) {
1565 d
= (struct device_attribute
*)attrs
[i
];
1566 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1568 if (pmu_attr
->event_str
)
1570 if (x86_pmu
.event_map(i
+ offset
))
1573 for (j
= i
; attrs
[j
]; j
++)
1574 attrs
[j
] = attrs
[j
+ 1];
1576 /* Check the shifted attr. */
1580 * event_map() is index based, the attrs array is organized
1581 * by increasing event index. If we shift the events, then
1582 * we need to compensate for the event_map(), otherwise
1583 * we are looking up the wrong event in the map
1589 /* Merge two pointer arrays */
1590 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1592 struct attribute
**new;
1595 for (j
= 0; a
[j
]; j
++)
1597 for (i
= 0; b
[i
]; i
++)
1601 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1606 for (i
= 0; a
[i
]; i
++)
1608 for (i
= 0; b
[i
]; i
++)
1615 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1617 struct perf_pmu_events_attr
*pmu_attr
= \
1618 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1619 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1621 /* string trumps id */
1622 if (pmu_attr
->event_str
)
1623 return sprintf(page
, "%s", pmu_attr
->event_str
);
1625 return x86_pmu
.events_sysfs_show(page
, config
);
1627 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1629 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1632 struct perf_pmu_events_ht_attr
*pmu_attr
=
1633 container_of(attr
, struct perf_pmu_events_ht_attr
, attr
);
1636 * Report conditional events depending on Hyper-Threading.
1638 * This is overly conservative as usually the HT special
1639 * handling is not needed if the other CPU thread is idle.
1641 * Note this does not (and cannot) handle the case when thread
1642 * siblings are invisible, for example with virtualization
1643 * if they are owned by some other guest. The user tool
1644 * has to re-read when a thread sibling gets onlined later.
1646 return sprintf(page
, "%s",
1647 topology_max_smt_threads() > 1 ?
1648 pmu_attr
->event_str_ht
:
1649 pmu_attr
->event_str_noht
);
1652 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1653 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1654 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1655 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1656 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1657 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1658 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1659 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1660 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1661 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1663 static struct attribute
*empty_attrs
;
1665 static struct attribute
*events_attr
[] = {
1666 EVENT_PTR(CPU_CYCLES
),
1667 EVENT_PTR(INSTRUCTIONS
),
1668 EVENT_PTR(CACHE_REFERENCES
),
1669 EVENT_PTR(CACHE_MISSES
),
1670 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1671 EVENT_PTR(BRANCH_MISSES
),
1672 EVENT_PTR(BUS_CYCLES
),
1673 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1674 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1675 EVENT_PTR(REF_CPU_CYCLES
),
1679 static struct attribute_group x86_pmu_events_group
= {
1681 .attrs
= events_attr
,
1684 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1686 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1687 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1688 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1689 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1690 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1691 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1695 * We have whole page size to spend and just little data
1696 * to write, so we can safely use sprintf.
1698 ret
= sprintf(page
, "event=0x%02llx", event
);
1701 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1704 ret
+= sprintf(page
+ ret
, ",edge");
1707 ret
+= sprintf(page
+ ret
, ",pc");
1710 ret
+= sprintf(page
+ ret
, ",any");
1713 ret
+= sprintf(page
+ ret
, ",inv");
1716 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1718 ret
+= sprintf(page
+ ret
, "\n");
1723 static int __init
init_hw_perf_events(void)
1725 struct x86_pmu_quirk
*quirk
;
1728 pr_info("Performance Events: ");
1730 switch (boot_cpu_data
.x86_vendor
) {
1731 case X86_VENDOR_INTEL
:
1732 err
= intel_pmu_init();
1734 case X86_VENDOR_AMD
:
1735 err
= amd_pmu_init();
1741 pr_cont("no PMU driver, software events only.\n");
1747 /* sanity check that the hardware exists or is emulated */
1748 if (!check_hw_exists())
1751 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1753 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1755 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1758 if (!x86_pmu
.intel_ctrl
)
1759 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1761 perf_events_lapic_init();
1762 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1764 unconstrained
= (struct event_constraint
)
1765 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1766 0, x86_pmu
.num_counters
, 0, 0);
1768 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1770 if (x86_pmu
.event_attrs
)
1771 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1773 if (!x86_pmu
.events_sysfs_show
)
1774 x86_pmu_events_group
.attrs
= &empty_attrs
;
1776 filter_events(x86_pmu_events_group
.attrs
);
1778 if (x86_pmu
.cpu_events
) {
1779 struct attribute
**tmp
;
1781 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1783 x86_pmu_events_group
.attrs
= tmp
;
1786 pr_info("... version: %d\n", x86_pmu
.version
);
1787 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1788 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1789 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1790 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1791 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1792 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1795 * Install callbacks. Core will call them for each online
1798 err
= cpuhp_setup_state(CPUHP_PERF_X86_PREPARE
, "PERF_X86_PREPARE",
1799 x86_pmu_prepare_cpu
, x86_pmu_dead_cpu
);
1803 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING
,
1804 "AP_PERF_X86_STARTING", x86_pmu_starting_cpu
,
1809 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE
, "AP_PERF_X86_ONLINE",
1810 x86_pmu_online_cpu
, NULL
);
1814 err
= perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1821 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE
);
1823 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING
);
1825 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE
);
1828 early_initcall(init_hw_perf_events
);
1830 static inline void x86_pmu_read(struct perf_event
*event
)
1832 x86_perf_event_update(event
);
1836 * Start group events scheduling transaction
1837 * Set the flag to make pmu::enable() not perform the
1838 * schedulability test, it will be performed at commit time
1840 * We only support PERF_PMU_TXN_ADD transactions. Save the
1841 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1844 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1846 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1848 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1850 cpuc
->txn_flags
= txn_flags
;
1851 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1854 perf_pmu_disable(pmu
);
1855 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1859 * Stop group events scheduling transaction
1860 * Clear the flag and pmu::enable() will perform the
1861 * schedulability test.
1863 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1865 unsigned int txn_flags
;
1866 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1868 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1870 txn_flags
= cpuc
->txn_flags
;
1871 cpuc
->txn_flags
= 0;
1872 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1876 * Truncate collected array by the number of events added in this
1877 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1879 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1880 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1881 perf_pmu_enable(pmu
);
1885 * Commit group events scheduling transaction
1886 * Perform the group schedulability test as a whole
1887 * Return 0 if success
1889 * Does not cancel the transaction on failure; expects the caller to do this.
1891 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1893 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1894 int assign
[X86_PMC_IDX_MAX
];
1897 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1899 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1900 cpuc
->txn_flags
= 0;
1906 if (!x86_pmu_initialized())
1909 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1914 * copy new assignment, now we know it is possible
1915 * will be used by hw_perf_enable()
1917 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1919 cpuc
->txn_flags
= 0;
1920 perf_pmu_enable(pmu
);
1924 * a fake_cpuc is used to validate event groups. Due to
1925 * the extra reg logic, we need to also allocate a fake
1926 * per_core and per_cpu structure. Otherwise, group events
1927 * using extra reg may conflict without the kernel being
1928 * able to catch this when the last event gets added to
1931 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1933 kfree(cpuc
->shared_regs
);
1937 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1939 struct cpu_hw_events
*cpuc
;
1940 int cpu
= raw_smp_processor_id();
1942 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1944 return ERR_PTR(-ENOMEM
);
1946 /* only needed, if we have extra_regs */
1947 if (x86_pmu
.extra_regs
) {
1948 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1949 if (!cpuc
->shared_regs
)
1955 free_fake_cpuc(cpuc
);
1956 return ERR_PTR(-ENOMEM
);
1960 * validate that we can schedule this event
1962 static int validate_event(struct perf_event
*event
)
1964 struct cpu_hw_events
*fake_cpuc
;
1965 struct event_constraint
*c
;
1968 fake_cpuc
= allocate_fake_cpuc();
1969 if (IS_ERR(fake_cpuc
))
1970 return PTR_ERR(fake_cpuc
);
1972 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
1974 if (!c
|| !c
->weight
)
1977 if (x86_pmu
.put_event_constraints
)
1978 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1980 free_fake_cpuc(fake_cpuc
);
1986 * validate a single event group
1988 * validation include:
1989 * - check events are compatible which each other
1990 * - events do not compete for the same counter
1991 * - number of events <= number of counters
1993 * validation ensures the group can be loaded onto the
1994 * PMU if it was the only group available.
1996 static int validate_group(struct perf_event
*event
)
1998 struct perf_event
*leader
= event
->group_leader
;
1999 struct cpu_hw_events
*fake_cpuc
;
2000 int ret
= -EINVAL
, n
;
2002 fake_cpuc
= allocate_fake_cpuc();
2003 if (IS_ERR(fake_cpuc
))
2004 return PTR_ERR(fake_cpuc
);
2006 * the event is not yet connected with its
2007 * siblings therefore we must first collect
2008 * existing siblings, then add the new event
2009 * before we can simulate the scheduling
2011 n
= collect_events(fake_cpuc
, leader
, true);
2015 fake_cpuc
->n_events
= n
;
2016 n
= collect_events(fake_cpuc
, event
, false);
2020 fake_cpuc
->n_events
= n
;
2022 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
2025 free_fake_cpuc(fake_cpuc
);
2029 static int x86_pmu_event_init(struct perf_event
*event
)
2034 switch (event
->attr
.type
) {
2036 case PERF_TYPE_HARDWARE
:
2037 case PERF_TYPE_HW_CACHE
:
2044 err
= __x86_pmu_event_init(event
);
2047 * we temporarily connect event to its pmu
2048 * such that validate_group() can classify
2049 * it as an x86 event using is_x86_event()
2054 if (event
->group_leader
!= event
)
2055 err
= validate_group(event
);
2057 err
= validate_event(event
);
2063 event
->destroy(event
);
2066 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
2067 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2072 static void refresh_pce(void *ignored
)
2075 load_mm_cr4(current
->mm
);
2078 static void x86_pmu_event_mapped(struct perf_event
*event
)
2080 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2083 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
2084 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2087 static void x86_pmu_event_unmapped(struct perf_event
*event
)
2092 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2095 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
2096 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2099 static int x86_pmu_event_idx(struct perf_event
*event
)
2101 int idx
= event
->hw
.idx
;
2103 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2106 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2107 idx
-= INTEL_PMC_IDX_FIXED
;
2114 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2115 struct device_attribute
*attr
,
2118 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2121 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2122 struct device_attribute
*attr
,
2123 const char *buf
, size_t count
)
2128 ret
= kstrtoul(buf
, 0, &val
);
2135 if (x86_pmu
.attr_rdpmc_broken
)
2138 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2140 * Changing into or out of always available, aka
2141 * perf-event-bypassing mode. This path is extremely slow,
2142 * but only root can trigger it, so it's okay.
2145 static_key_slow_inc(&rdpmc_always_available
);
2147 static_key_slow_dec(&rdpmc_always_available
);
2148 on_each_cpu(refresh_pce
, NULL
, 1);
2151 x86_pmu
.attr_rdpmc
= val
;
2156 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2158 static struct attribute
*x86_pmu_attrs
[] = {
2159 &dev_attr_rdpmc
.attr
,
2163 static struct attribute_group x86_pmu_attr_group
= {
2164 .attrs
= x86_pmu_attrs
,
2167 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2168 &x86_pmu_attr_group
,
2169 &x86_pmu_format_group
,
2170 &x86_pmu_events_group
,
2174 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2176 if (x86_pmu
.sched_task
)
2177 x86_pmu
.sched_task(ctx
, sched_in
);
2180 void perf_check_microcode(void)
2182 if (x86_pmu
.check_microcode
)
2183 x86_pmu
.check_microcode();
2185 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2187 static struct pmu pmu
= {
2188 .pmu_enable
= x86_pmu_enable
,
2189 .pmu_disable
= x86_pmu_disable
,
2191 .attr_groups
= x86_pmu_attr_groups
,
2193 .event_init
= x86_pmu_event_init
,
2195 .event_mapped
= x86_pmu_event_mapped
,
2196 .event_unmapped
= x86_pmu_event_unmapped
,
2200 .start
= x86_pmu_start
,
2201 .stop
= x86_pmu_stop
,
2202 .read
= x86_pmu_read
,
2204 .start_txn
= x86_pmu_start_txn
,
2205 .cancel_txn
= x86_pmu_cancel_txn
,
2206 .commit_txn
= x86_pmu_commit_txn
,
2208 .event_idx
= x86_pmu_event_idx
,
2209 .sched_task
= x86_pmu_sched_task
,
2210 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2213 void arch_perf_update_userpage(struct perf_event
*event
,
2214 struct perf_event_mmap_page
*userpg
, u64 now
)
2216 struct cyc2ns_data
*data
;
2218 userpg
->cap_user_time
= 0;
2219 userpg
->cap_user_time_zero
= 0;
2220 userpg
->cap_user_rdpmc
=
2221 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2222 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2224 if (!sched_clock_stable())
2227 data
= cyc2ns_read_begin();
2230 * Internal timekeeping for enabled/running/stopped times
2231 * is always in the local_clock domain.
2233 userpg
->cap_user_time
= 1;
2234 userpg
->time_mult
= data
->cyc2ns_mul
;
2235 userpg
->time_shift
= data
->cyc2ns_shift
;
2236 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2239 * cap_user_time_zero doesn't make sense when we're using a different
2240 * time base for the records.
2242 if (!event
->attr
.use_clockid
) {
2243 userpg
->cap_user_time_zero
= 1;
2244 userpg
->time_zero
= data
->cyc2ns_offset
;
2247 cyc2ns_read_end(data
);
2254 static int backtrace_stack(void *data
, char *name
)
2259 static int backtrace_address(void *data
, unsigned long addr
, int reliable
)
2261 struct perf_callchain_entry_ctx
*entry
= data
;
2263 return perf_callchain_store(entry
, addr
);
2266 static const struct stacktrace_ops backtrace_ops
= {
2267 .stack
= backtrace_stack
,
2268 .address
= backtrace_address
,
2269 .walk_stack
= print_context_stack_bp
,
2273 perf_callchain_kernel(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2275 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2276 /* TODO: We don't support guest os callchain now */
2280 perf_callchain_store(entry
, regs
->ip
);
2282 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2286 valid_user_frame(const void __user
*fp
, unsigned long size
)
2288 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2291 static unsigned long get_segment_base(unsigned int segment
)
2293 struct desc_struct
*desc
;
2294 int idx
= segment
>> 3;
2296 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2297 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2298 struct ldt_struct
*ldt
;
2300 if (idx
> LDT_ENTRIES
)
2303 /* IRQs are off, so this synchronizes with smp_store_release */
2304 ldt
= lockless_dereference(current
->active_mm
->context
.ldt
);
2305 if (!ldt
|| idx
> ldt
->size
)
2308 desc
= &ldt
->entries
[idx
];
2313 if (idx
> GDT_ENTRIES
)
2316 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2319 return get_desc_base(desc
);
2322 #ifdef CONFIG_IA32_EMULATION
2324 #include <asm/compat.h>
2327 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2329 /* 32-bit process in 64-bit kernel. */
2330 unsigned long ss_base
, cs_base
;
2331 struct stack_frame_ia32 frame
;
2332 const void __user
*fp
;
2334 if (!test_thread_flag(TIF_IA32
))
2337 cs_base
= get_segment_base(regs
->cs
);
2338 ss_base
= get_segment_base(regs
->ss
);
2340 fp
= compat_ptr(ss_base
+ regs
->bp
);
2341 pagefault_disable();
2342 while (entry
->nr
< entry
->max_stack
) {
2343 unsigned long bytes
;
2344 frame
.next_frame
= 0;
2345 frame
.return_address
= 0;
2347 if (!access_ok(VERIFY_READ
, fp
, 8))
2350 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2353 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2357 if (!valid_user_frame(fp
, sizeof(frame
)))
2360 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2361 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2368 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2375 perf_callchain_user(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2377 struct stack_frame frame
;
2378 const unsigned long __user
*fp
;
2380 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2381 /* TODO: We don't support guest os callchain now */
2386 * We don't know what to do with VM86 stacks.. ignore them for now.
2388 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2391 fp
= (unsigned long __user
*)regs
->bp
;
2393 perf_callchain_store(entry
, regs
->ip
);
2398 if (perf_callchain_user32(regs
, entry
))
2401 pagefault_disable();
2402 while (entry
->nr
< entry
->max_stack
) {
2403 unsigned long bytes
;
2405 frame
.next_frame
= NULL
;
2406 frame
.return_address
= 0;
2408 if (!access_ok(VERIFY_READ
, fp
, sizeof(*fp
) * 2))
2411 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, sizeof(*fp
));
2414 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+ 1, sizeof(*fp
));
2418 if (!valid_user_frame(fp
, sizeof(frame
)))
2421 perf_callchain_store(entry
, frame
.return_address
);
2422 fp
= (void __user
*)frame
.next_frame
;
2428 * Deal with code segment offsets for the various execution modes:
2430 * VM86 - the good olde 16 bit days, where the linear address is
2431 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2433 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2434 * to figure out what the 32bit base address is.
2436 * X32 - has TIF_X32 set, but is running in x86_64
2438 * X86_64 - CS,DS,SS,ES are all zero based.
2440 static unsigned long code_segment_base(struct pt_regs
*regs
)
2443 * For IA32 we look at the GDT/LDT segment base to convert the
2444 * effective IP to a linear address.
2447 #ifdef CONFIG_X86_32
2449 * If we are in VM86 mode, add the segment offset to convert to a
2452 if (regs
->flags
& X86_VM_MASK
)
2453 return 0x10 * regs
->cs
;
2455 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2456 return get_segment_base(regs
->cs
);
2458 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2459 regs
->cs
!= __USER32_CS
)
2460 return get_segment_base(regs
->cs
);
2465 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2467 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2468 return perf_guest_cbs
->get_guest_ip();
2470 return regs
->ip
+ code_segment_base(regs
);
2473 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2477 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2478 if (perf_guest_cbs
->is_user_mode())
2479 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2481 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2483 if (user_mode(regs
))
2484 misc
|= PERF_RECORD_MISC_USER
;
2486 misc
|= PERF_RECORD_MISC_KERNEL
;
2489 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2490 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2495 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2497 cap
->version
= x86_pmu
.version
;
2498 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2499 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2500 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2501 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2502 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2503 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2505 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);