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Merge tag 'pm-urgent-4.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / arch / x86 / events / intel / core.c
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/nmi.h>
16
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
19 #include <asm/intel-family.h>
20 #include <asm/apic.h>
21
22 #include "../perf_event.h"
23
24 /*
25 * Intel PerfMon, used on Core and later.
26 */
27 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
28 {
29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
37 };
38
39 static struct event_constraint intel_core_event_constraints[] __read_mostly =
40 {
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
47 EVENT_CONSTRAINT_END
48 };
49
50 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
51 {
52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
65 EVENT_CONSTRAINT_END
66 };
67
68 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
69 {
70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
81 EVENT_CONSTRAINT_END
82 };
83
84 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
85 {
86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
89 EVENT_EXTRA_END
90 };
91
92 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
93 {
94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
101 EVENT_CONSTRAINT_END
102 };
103
104 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
105 {
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118
119 /*
120 * When HT is off these events can only run on the bottom 4 counters
121 * When HT is on, they are impacted by the HT bug and require EXCL access
122 */
123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
127
128 EVENT_CONSTRAINT_END
129 };
130
131 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
132 {
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
146
147 /*
148 * When HT is off these events can only run on the bottom 4 counters
149 * When HT is on, they are impacted by the HT bug and require EXCL access
150 */
151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
155
156 EVENT_CONSTRAINT_END
157 };
158
159 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
160 {
161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
165 EVENT_EXTRA_END
166 };
167
168 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
169 {
170 EVENT_CONSTRAINT_END
171 };
172
173 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
174 {
175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
178 EVENT_CONSTRAINT_END
179 };
180
181 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
182 {
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
186 EVENT_CONSTRAINT_END
187 };
188
189 static struct event_constraint intel_skl_event_constraints[] = {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
194
195 /*
196 * when HT is off, these can only run on the bottom 4 counters
197 */
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
203
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
210 EVENT_EXTRA_END
211 };
212
213 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
218 EVENT_EXTRA_END
219 };
220
221 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
226 EVENT_EXTRA_END
227 };
228
229 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
233 /*
234 * Note the low 8 bits eventsel code is not a continuous field, containing
235 * some #GPing bits. These are masked out.
236 */
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
238 EVENT_EXTRA_END
239 };
240
241 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
242 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
243 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
244
245 static struct attribute *nhm_events_attrs[] = {
246 EVENT_PTR(mem_ld_nhm),
247 NULL,
248 };
249
250 /*
251 * topdown events for Intel Core CPUs.
252 *
253 * The events are all in slots, which is a free slot in a 4 wide
254 * pipeline. Some events are already reported in slots, for cycle
255 * events we multiply by the pipeline width (4).
256 *
257 * With Hyper Threading on, topdown metrics are either summed or averaged
258 * between the threads of a core: (count_t0 + count_t1).
259 *
260 * For the average case the metric is always scaled to pipeline width,
261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
262 */
263
264 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
267 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
268 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
269 "event=0xe,umask=0x1"); /* uops_issued.any */
270 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
272 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
274 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
277 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
278 "4", "2");
279
280 static struct attribute *snb_events_attrs[] = {
281 EVENT_PTR(mem_ld_snb),
282 EVENT_PTR(mem_st_snb),
283 EVENT_PTR(td_slots_issued),
284 EVENT_PTR(td_slots_retired),
285 EVENT_PTR(td_fetch_bubbles),
286 EVENT_PTR(td_total_slots),
287 EVENT_PTR(td_total_slots_scale),
288 EVENT_PTR(td_recovery_bubbles),
289 EVENT_PTR(td_recovery_bubbles_scale),
290 NULL,
291 };
292
293 static struct event_constraint intel_hsw_event_constraints[] = {
294 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
295 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
296 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
300 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
302 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
304 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
306
307 /*
308 * When HT is off these events can only run on the bottom 4 counters
309 * When HT is on, they are impacted by the HT bug and require EXCL access
310 */
311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
315
316 EVENT_CONSTRAINT_END
317 };
318
319 static struct event_constraint intel_bdw_event_constraints[] = {
320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
322 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
325 /*
326 * when HT is off, these can only run on the bottom 4 counters
327 */
328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
332 EVENT_CONSTRAINT_END
333 };
334
335 static u64 intel_pmu_event_map(int hw_event)
336 {
337 return intel_perfmon_event_map[hw_event];
338 }
339
340 /*
341 * Notes on the events:
342 * - data reads do not include code reads (comparable to earlier tables)
343 * - data counts include speculative execution (except L1 write, dtlb, bpu)
344 * - remote node access includes remote memory, remote cache, remote mmio.
345 * - prefetches are not included in the counts.
346 * - icache miss does not include decoded icache
347 */
348
349 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
350 #define SKL_DEMAND_RFO BIT_ULL(1)
351 #define SKL_ANY_RESPONSE BIT_ULL(16)
352 #define SKL_SUPPLIER_NONE BIT_ULL(17)
353 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
354 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
355 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
356 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
357 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
360 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
361 #define SKL_SPL_HIT BIT_ULL(30)
362 #define SKL_SNOOP_NONE BIT_ULL(31)
363 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
364 #define SKL_SNOOP_MISS BIT_ULL(33)
365 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
366 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
367 #define SKL_SNOOP_HITM BIT_ULL(36)
368 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
369 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
373 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
374 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
377 SKL_SNOOP_HITM|SKL_SPL_HIT)
378 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
379 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
380 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
382 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
383
384 static __initconst const u64 skl_hw_cache_event_ids
385 [PERF_COUNT_HW_CACHE_MAX]
386 [PERF_COUNT_HW_CACHE_OP_MAX]
387 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
388 {
389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
393 },
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS) ] = 0x0,
397 },
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
401 },
402 },
403 [ C(L1I ) ] = {
404 [ C(OP_READ) ] = {
405 [ C(RESULT_ACCESS) ] = 0x0,
406 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
407 },
408 [ C(OP_WRITE) ] = {
409 [ C(RESULT_ACCESS) ] = -1,
410 [ C(RESULT_MISS) ] = -1,
411 },
412 [ C(OP_PREFETCH) ] = {
413 [ C(RESULT_ACCESS) ] = 0x0,
414 [ C(RESULT_MISS) ] = 0x0,
415 },
416 },
417 [ C(LL ) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
420 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
421 },
422 [ C(OP_WRITE) ] = {
423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
425 },
426 [ C(OP_PREFETCH) ] = {
427 [ C(RESULT_ACCESS) ] = 0x0,
428 [ C(RESULT_MISS) ] = 0x0,
429 },
430 },
431 [ C(DTLB) ] = {
432 [ C(OP_READ) ] = {
433 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
434 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
435 },
436 [ C(OP_WRITE) ] = {
437 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
438 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
439 },
440 [ C(OP_PREFETCH) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x0,
443 },
444 },
445 [ C(ITLB) ] = {
446 [ C(OP_READ) ] = {
447 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
448 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
449 },
450 [ C(OP_WRITE) ] = {
451 [ C(RESULT_ACCESS) ] = -1,
452 [ C(RESULT_MISS) ] = -1,
453 },
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 },
459 [ C(BPU ) ] = {
460 [ C(OP_READ) ] = {
461 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
462 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
463 },
464 [ C(OP_WRITE) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
467 },
468 [ C(OP_PREFETCH) ] = {
469 [ C(RESULT_ACCESS) ] = -1,
470 [ C(RESULT_MISS) ] = -1,
471 },
472 },
473 [ C(NODE) ] = {
474 [ C(OP_READ) ] = {
475 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
476 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
477 },
478 [ C(OP_WRITE) ] = {
479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
481 },
482 [ C(OP_PREFETCH) ] = {
483 [ C(RESULT_ACCESS) ] = 0x0,
484 [ C(RESULT_MISS) ] = 0x0,
485 },
486 },
487 };
488
489 static __initconst const u64 skl_hw_cache_extra_regs
490 [PERF_COUNT_HW_CACHE_MAX]
491 [PERF_COUNT_HW_CACHE_OP_MAX]
492 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
493 {
494 [ C(LL ) ] = {
495 [ C(OP_READ) ] = {
496 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
497 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
498 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
499 SKL_L3_MISS|SKL_ANY_SNOOP|
500 SKL_SUPPLIER_NONE,
501 },
502 [ C(OP_WRITE) ] = {
503 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
504 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
505 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
506 SKL_L3_MISS|SKL_ANY_SNOOP|
507 SKL_SUPPLIER_NONE,
508 },
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
512 },
513 },
514 [ C(NODE) ] = {
515 [ C(OP_READ) ] = {
516 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
517 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
518 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
519 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
520 },
521 [ C(OP_WRITE) ] = {
522 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
523 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
524 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
525 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x0,
529 [ C(RESULT_MISS) ] = 0x0,
530 },
531 },
532 };
533
534 #define SNB_DMND_DATA_RD (1ULL << 0)
535 #define SNB_DMND_RFO (1ULL << 1)
536 #define SNB_DMND_IFETCH (1ULL << 2)
537 #define SNB_DMND_WB (1ULL << 3)
538 #define SNB_PF_DATA_RD (1ULL << 4)
539 #define SNB_PF_RFO (1ULL << 5)
540 #define SNB_PF_IFETCH (1ULL << 6)
541 #define SNB_LLC_DATA_RD (1ULL << 7)
542 #define SNB_LLC_RFO (1ULL << 8)
543 #define SNB_LLC_IFETCH (1ULL << 9)
544 #define SNB_BUS_LOCKS (1ULL << 10)
545 #define SNB_STRM_ST (1ULL << 11)
546 #define SNB_OTHER (1ULL << 15)
547 #define SNB_RESP_ANY (1ULL << 16)
548 #define SNB_NO_SUPP (1ULL << 17)
549 #define SNB_LLC_HITM (1ULL << 18)
550 #define SNB_LLC_HITE (1ULL << 19)
551 #define SNB_LLC_HITS (1ULL << 20)
552 #define SNB_LLC_HITF (1ULL << 21)
553 #define SNB_LOCAL (1ULL << 22)
554 #define SNB_REMOTE (0xffULL << 23)
555 #define SNB_SNP_NONE (1ULL << 31)
556 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
557 #define SNB_SNP_MISS (1ULL << 33)
558 #define SNB_NO_FWD (1ULL << 34)
559 #define SNB_SNP_FWD (1ULL << 35)
560 #define SNB_HITM (1ULL << 36)
561 #define SNB_NON_DRAM (1ULL << 37)
562
563 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
564 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
565 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
566
567 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
569 SNB_HITM)
570
571 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
572 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
573
574 #define SNB_L3_ACCESS SNB_RESP_ANY
575 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
576
577 static __initconst const u64 snb_hw_cache_extra_regs
578 [PERF_COUNT_HW_CACHE_MAX]
579 [PERF_COUNT_HW_CACHE_OP_MAX]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
581 {
582 [ C(LL ) ] = {
583 [ C(OP_READ) ] = {
584 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
585 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
586 },
587 [ C(OP_WRITE) ] = {
588 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
589 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
590 },
591 [ C(OP_PREFETCH) ] = {
592 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
593 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
594 },
595 },
596 [ C(NODE) ] = {
597 [ C(OP_READ) ] = {
598 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
599 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
600 },
601 [ C(OP_WRITE) ] = {
602 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
603 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
604 },
605 [ C(OP_PREFETCH) ] = {
606 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
607 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
608 },
609 },
610 };
611
612 static __initconst const u64 snb_hw_cache_event_ids
613 [PERF_COUNT_HW_CACHE_MAX]
614 [PERF_COUNT_HW_CACHE_OP_MAX]
615 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
616 {
617 [ C(L1D) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
620 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
621 },
622 [ C(OP_WRITE) ] = {
623 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
624 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
625 },
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
629 },
630 },
631 [ C(L1I ) ] = {
632 [ C(OP_READ) ] = {
633 [ C(RESULT_ACCESS) ] = 0x0,
634 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
635 },
636 [ C(OP_WRITE) ] = {
637 [ C(RESULT_ACCESS) ] = -1,
638 [ C(RESULT_MISS) ] = -1,
639 },
640 [ C(OP_PREFETCH) ] = {
641 [ C(RESULT_ACCESS) ] = 0x0,
642 [ C(RESULT_MISS) ] = 0x0,
643 },
644 },
645 [ C(LL ) ] = {
646 [ C(OP_READ) ] = {
647 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
650 [ C(RESULT_MISS) ] = 0x01b7,
651 },
652 [ C(OP_WRITE) ] = {
653 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
654 [ C(RESULT_ACCESS) ] = 0x01b7,
655 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
656 [ C(RESULT_MISS) ] = 0x01b7,
657 },
658 [ C(OP_PREFETCH) ] = {
659 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
660 [ C(RESULT_ACCESS) ] = 0x01b7,
661 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
662 [ C(RESULT_MISS) ] = 0x01b7,
663 },
664 },
665 [ C(DTLB) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
668 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
672 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x0,
677 },
678 },
679 [ C(ITLB) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
682 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = -1,
686 [ C(RESULT_MISS) ] = -1,
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
691 },
692 },
693 [ C(BPU ) ] = {
694 [ C(OP_READ) ] = {
695 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
696 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
697 },
698 [ C(OP_WRITE) ] = {
699 [ C(RESULT_ACCESS) ] = -1,
700 [ C(RESULT_MISS) ] = -1,
701 },
702 [ C(OP_PREFETCH) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
705 },
706 },
707 [ C(NODE) ] = {
708 [ C(OP_READ) ] = {
709 [ C(RESULT_ACCESS) ] = 0x01b7,
710 [ C(RESULT_MISS) ] = 0x01b7,
711 },
712 [ C(OP_WRITE) ] = {
713 [ C(RESULT_ACCESS) ] = 0x01b7,
714 [ C(RESULT_MISS) ] = 0x01b7,
715 },
716 [ C(OP_PREFETCH) ] = {
717 [ C(RESULT_ACCESS) ] = 0x01b7,
718 [ C(RESULT_MISS) ] = 0x01b7,
719 },
720 },
721
722 };
723
724 /*
725 * Notes on the events:
726 * - data reads do not include code reads (comparable to earlier tables)
727 * - data counts include speculative execution (except L1 write, dtlb, bpu)
728 * - remote node access includes remote memory, remote cache, remote mmio.
729 * - prefetches are not included in the counts because they are not
730 * reliably counted.
731 */
732
733 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
734 #define HSW_DEMAND_RFO BIT_ULL(1)
735 #define HSW_ANY_RESPONSE BIT_ULL(16)
736 #define HSW_SUPPLIER_NONE BIT_ULL(17)
737 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
738 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
739 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
740 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
741 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
743 HSW_L3_MISS_REMOTE_HOP2P)
744 #define HSW_SNOOP_NONE BIT_ULL(31)
745 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
746 #define HSW_SNOOP_MISS BIT_ULL(33)
747 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
748 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
749 #define HSW_SNOOP_HITM BIT_ULL(36)
750 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
751 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
755 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
756 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
757 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
758 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
760 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
761
762 #define BDW_L3_MISS_LOCAL BIT(26)
763 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
765 HSW_L3_MISS_REMOTE_HOP2P)
766
767
768 static __initconst const u64 hsw_hw_cache_event_ids
769 [PERF_COUNT_HW_CACHE_MAX]
770 [PERF_COUNT_HW_CACHE_OP_MAX]
771 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
772 {
773 [ C(L1D ) ] = {
774 [ C(OP_READ) ] = {
775 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
776 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
777 },
778 [ C(OP_WRITE) ] = {
779 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
780 [ C(RESULT_MISS) ] = 0x0,
781 },
782 [ C(OP_PREFETCH) ] = {
783 [ C(RESULT_ACCESS) ] = 0x0,
784 [ C(RESULT_MISS) ] = 0x0,
785 },
786 },
787 [ C(L1I ) ] = {
788 [ C(OP_READ) ] = {
789 [ C(RESULT_ACCESS) ] = 0x0,
790 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
791 },
792 [ C(OP_WRITE) ] = {
793 [ C(RESULT_ACCESS) ] = -1,
794 [ C(RESULT_MISS) ] = -1,
795 },
796 [ C(OP_PREFETCH) ] = {
797 [ C(RESULT_ACCESS) ] = 0x0,
798 [ C(RESULT_MISS) ] = 0x0,
799 },
800 },
801 [ C(LL ) ] = {
802 [ C(OP_READ) ] = {
803 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
804 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
805 },
806 [ C(OP_WRITE) ] = {
807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
809 },
810 [ C(OP_PREFETCH) ] = {
811 [ C(RESULT_ACCESS) ] = 0x0,
812 [ C(RESULT_MISS) ] = 0x0,
813 },
814 },
815 [ C(DTLB) ] = {
816 [ C(OP_READ) ] = {
817 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
818 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
822 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
823 },
824 [ C(OP_PREFETCH) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x0,
827 },
828 },
829 [ C(ITLB) ] = {
830 [ C(OP_READ) ] = {
831 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
832 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = -1,
836 [ C(RESULT_MISS) ] = -1,
837 },
838 [ C(OP_PREFETCH) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 },
843 [ C(BPU ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
846 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = -1,
850 [ C(RESULT_MISS) ] = -1,
851 },
852 [ C(OP_PREFETCH) ] = {
853 [ C(RESULT_ACCESS) ] = -1,
854 [ C(RESULT_MISS) ] = -1,
855 },
856 },
857 [ C(NODE) ] = {
858 [ C(OP_READ) ] = {
859 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
860 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
861 },
862 [ C(OP_WRITE) ] = {
863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
865 },
866 [ C(OP_PREFETCH) ] = {
867 [ C(RESULT_ACCESS) ] = 0x0,
868 [ C(RESULT_MISS) ] = 0x0,
869 },
870 },
871 };
872
873 static __initconst const u64 hsw_hw_cache_extra_regs
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877 {
878 [ C(LL ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
881 HSW_LLC_ACCESS,
882 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
883 HSW_L3_MISS|HSW_ANY_SNOOP,
884 },
885 [ C(OP_WRITE) ] = {
886 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
887 HSW_LLC_ACCESS,
888 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
889 HSW_L3_MISS|HSW_ANY_SNOOP,
890 },
891 [ C(OP_PREFETCH) ] = {
892 [ C(RESULT_ACCESS) ] = 0x0,
893 [ C(RESULT_MISS) ] = 0x0,
894 },
895 },
896 [ C(NODE) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
899 HSW_L3_MISS_LOCAL_DRAM|
900 HSW_SNOOP_DRAM,
901 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
902 HSW_L3_MISS_REMOTE|
903 HSW_SNOOP_DRAM,
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
907 HSW_L3_MISS_LOCAL_DRAM|
908 HSW_SNOOP_DRAM,
909 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
910 HSW_L3_MISS_REMOTE|
911 HSW_SNOOP_DRAM,
912 },
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = 0x0,
915 [ C(RESULT_MISS) ] = 0x0,
916 },
917 },
918 };
919
920 static __initconst const u64 westmere_hw_cache_event_ids
921 [PERF_COUNT_HW_CACHE_MAX]
922 [PERF_COUNT_HW_CACHE_OP_MAX]
923 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
924 {
925 [ C(L1D) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
929 },
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
932 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
933 },
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
936 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
937 },
938 },
939 [ C(L1I ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
942 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
943 },
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
947 },
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = 0x0,
950 [ C(RESULT_MISS) ] = 0x0,
951 },
952 },
953 [ C(LL ) ] = {
954 [ C(OP_READ) ] = {
955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
958 [ C(RESULT_MISS) ] = 0x01b7,
959 },
960 /*
961 * Use RFO, not WRITEBACK, because a write miss would typically occur
962 * on RFO.
963 */
964 [ C(OP_WRITE) ] = {
965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_PREFETCH) ] = {
971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
984 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
1033 };
1034
1035 /*
1036 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1037 * See IA32 SDM Vol 3B 30.6.1.3
1038 */
1039
1040 #define NHM_DMND_DATA_RD (1 << 0)
1041 #define NHM_DMND_RFO (1 << 1)
1042 #define NHM_DMND_IFETCH (1 << 2)
1043 #define NHM_DMND_WB (1 << 3)
1044 #define NHM_PF_DATA_RD (1 << 4)
1045 #define NHM_PF_DATA_RFO (1 << 5)
1046 #define NHM_PF_IFETCH (1 << 6)
1047 #define NHM_OFFCORE_OTHER (1 << 7)
1048 #define NHM_UNCORE_HIT (1 << 8)
1049 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1050 #define NHM_OTHER_CORE_HITM (1 << 10)
1051 /* reserved */
1052 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1053 #define NHM_REMOTE_DRAM (1 << 13)
1054 #define NHM_LOCAL_DRAM (1 << 14)
1055 #define NHM_NON_DRAM (1 << 15)
1056
1057 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1058 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1059
1060 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1061 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1062 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1063
1064 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1065 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1066 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1067
1068 static __initconst const u64 nehalem_hw_cache_extra_regs
1069 [PERF_COUNT_HW_CACHE_MAX]
1070 [PERF_COUNT_HW_CACHE_OP_MAX]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1072 {
1073 [ C(LL ) ] = {
1074 [ C(OP_READ) ] = {
1075 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1076 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1077 },
1078 [ C(OP_WRITE) ] = {
1079 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1080 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1081 },
1082 [ C(OP_PREFETCH) ] = {
1083 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1084 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1085 },
1086 },
1087 [ C(NODE) ] = {
1088 [ C(OP_READ) ] = {
1089 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1090 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1091 },
1092 [ C(OP_WRITE) ] = {
1093 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1094 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1095 },
1096 [ C(OP_PREFETCH) ] = {
1097 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1098 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1099 },
1100 },
1101 };
1102
1103 static __initconst const u64 nehalem_hw_cache_event_ids
1104 [PERF_COUNT_HW_CACHE_MAX]
1105 [PERF_COUNT_HW_CACHE_OP_MAX]
1106 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1107 {
1108 [ C(L1D) ] = {
1109 [ C(OP_READ) ] = {
1110 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1111 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1112 },
1113 [ C(OP_WRITE) ] = {
1114 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1115 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1116 },
1117 [ C(OP_PREFETCH) ] = {
1118 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1119 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1120 },
1121 },
1122 [ C(L1I ) ] = {
1123 [ C(OP_READ) ] = {
1124 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1125 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1126 },
1127 [ C(OP_WRITE) ] = {
1128 [ C(RESULT_ACCESS) ] = -1,
1129 [ C(RESULT_MISS) ] = -1,
1130 },
1131 [ C(OP_PREFETCH) ] = {
1132 [ C(RESULT_ACCESS) ] = 0x0,
1133 [ C(RESULT_MISS) ] = 0x0,
1134 },
1135 },
1136 [ C(LL ) ] = {
1137 [ C(OP_READ) ] = {
1138 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1141 [ C(RESULT_MISS) ] = 0x01b7,
1142 },
1143 /*
1144 * Use RFO, not WRITEBACK, because a write miss would typically occur
1145 * on RFO.
1146 */
1147 [ C(OP_WRITE) ] = {
1148 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1149 [ C(RESULT_ACCESS) ] = 0x01b7,
1150 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1151 [ C(RESULT_MISS) ] = 0x01b7,
1152 },
1153 [ C(OP_PREFETCH) ] = {
1154 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1155 [ C(RESULT_ACCESS) ] = 0x01b7,
1156 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1157 [ C(RESULT_MISS) ] = 0x01b7,
1158 },
1159 },
1160 [ C(DTLB) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1163 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1164 },
1165 [ C(OP_WRITE) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1167 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1168 },
1169 [ C(OP_PREFETCH) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0,
1171 [ C(RESULT_MISS) ] = 0x0,
1172 },
1173 },
1174 [ C(ITLB) ] = {
1175 [ C(OP_READ) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1177 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1178 },
1179 [ C(OP_WRITE) ] = {
1180 [ C(RESULT_ACCESS) ] = -1,
1181 [ C(RESULT_MISS) ] = -1,
1182 },
1183 [ C(OP_PREFETCH) ] = {
1184 [ C(RESULT_ACCESS) ] = -1,
1185 [ C(RESULT_MISS) ] = -1,
1186 },
1187 },
1188 [ C(BPU ) ] = {
1189 [ C(OP_READ) ] = {
1190 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1191 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1192 },
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = -1,
1195 [ C(RESULT_MISS) ] = -1,
1196 },
1197 [ C(OP_PREFETCH) ] = {
1198 [ C(RESULT_ACCESS) ] = -1,
1199 [ C(RESULT_MISS) ] = -1,
1200 },
1201 },
1202 [ C(NODE) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x01b7,
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x01b7,
1209 [ C(RESULT_MISS) ] = 0x01b7,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01b7,
1213 [ C(RESULT_MISS) ] = 0x01b7,
1214 },
1215 },
1216 };
1217
1218 static __initconst const u64 core2_hw_cache_event_ids
1219 [PERF_COUNT_HW_CACHE_MAX]
1220 [PERF_COUNT_HW_CACHE_OP_MAX]
1221 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1222 {
1223 [ C(L1D) ] = {
1224 [ C(OP_READ) ] = {
1225 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1226 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1227 },
1228 [ C(OP_WRITE) ] = {
1229 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1230 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1231 },
1232 [ C(OP_PREFETCH) ] = {
1233 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1234 [ C(RESULT_MISS) ] = 0,
1235 },
1236 },
1237 [ C(L1I ) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1240 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = -1,
1244 [ C(RESULT_MISS) ] = -1,
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0,
1248 [ C(RESULT_MISS) ] = 0,
1249 },
1250 },
1251 [ C(LL ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1254 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1258 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0,
1262 [ C(RESULT_MISS) ] = 0,
1263 },
1264 },
1265 [ C(DTLB) ] = {
1266 [ C(OP_READ) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1268 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1269 },
1270 [ C(OP_WRITE) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1272 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1273 },
1274 [ C(OP_PREFETCH) ] = {
1275 [ C(RESULT_ACCESS) ] = 0,
1276 [ C(RESULT_MISS) ] = 0,
1277 },
1278 },
1279 [ C(ITLB) ] = {
1280 [ C(OP_READ) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1282 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1283 },
1284 [ C(OP_WRITE) ] = {
1285 [ C(RESULT_ACCESS) ] = -1,
1286 [ C(RESULT_MISS) ] = -1,
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 },
1293 [ C(BPU ) ] = {
1294 [ C(OP_READ) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1296 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1297 },
1298 [ C(OP_WRITE) ] = {
1299 [ C(RESULT_ACCESS) ] = -1,
1300 [ C(RESULT_MISS) ] = -1,
1301 },
1302 [ C(OP_PREFETCH) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 },
1307 };
1308
1309 static __initconst const u64 atom_hw_cache_event_ids
1310 [PERF_COUNT_HW_CACHE_MAX]
1311 [PERF_COUNT_HW_CACHE_OP_MAX]
1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1313 {
1314 [ C(L1D) ] = {
1315 [ C(OP_READ) ] = {
1316 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1317 [ C(RESULT_MISS) ] = 0,
1318 },
1319 [ C(OP_WRITE) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1321 [ C(RESULT_MISS) ] = 0,
1322 },
1323 [ C(OP_PREFETCH) ] = {
1324 [ C(RESULT_ACCESS) ] = 0x0,
1325 [ C(RESULT_MISS) ] = 0,
1326 },
1327 },
1328 [ C(L1I ) ] = {
1329 [ C(OP_READ) ] = {
1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1332 },
1333 [ C(OP_WRITE) ] = {
1334 [ C(RESULT_ACCESS) ] = -1,
1335 [ C(RESULT_MISS) ] = -1,
1336 },
1337 [ C(OP_PREFETCH) ] = {
1338 [ C(RESULT_ACCESS) ] = 0,
1339 [ C(RESULT_MISS) ] = 0,
1340 },
1341 },
1342 [ C(LL ) ] = {
1343 [ C(OP_READ) ] = {
1344 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1345 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1346 },
1347 [ C(OP_WRITE) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1349 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1350 },
1351 [ C(OP_PREFETCH) ] = {
1352 [ C(RESULT_ACCESS) ] = 0,
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 },
1356 [ C(DTLB) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1359 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1363 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = 0,
1367 [ C(RESULT_MISS) ] = 0,
1368 },
1369 },
1370 [ C(ITLB) ] = {
1371 [ C(OP_READ) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1373 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1374 },
1375 [ C(OP_WRITE) ] = {
1376 [ C(RESULT_ACCESS) ] = -1,
1377 [ C(RESULT_MISS) ] = -1,
1378 },
1379 [ C(OP_PREFETCH) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 },
1384 [ C(BPU ) ] = {
1385 [ C(OP_READ) ] = {
1386 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1387 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1388 },
1389 [ C(OP_WRITE) ] = {
1390 [ C(RESULT_ACCESS) ] = -1,
1391 [ C(RESULT_MISS) ] = -1,
1392 },
1393 [ C(OP_PREFETCH) ] = {
1394 [ C(RESULT_ACCESS) ] = -1,
1395 [ C(RESULT_MISS) ] = -1,
1396 },
1397 },
1398 };
1399
1400 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1401 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1402 /* no_alloc_cycles.not_delivered */
1403 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1404 "event=0xca,umask=0x50");
1405 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1406 /* uops_retired.all */
1407 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1408 "event=0xc2,umask=0x10");
1409 /* uops_retired.all */
1410 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1411 "event=0xc2,umask=0x10");
1412
1413 static struct attribute *slm_events_attrs[] = {
1414 EVENT_PTR(td_total_slots_slm),
1415 EVENT_PTR(td_total_slots_scale_slm),
1416 EVENT_PTR(td_fetch_bubbles_slm),
1417 EVENT_PTR(td_fetch_bubbles_scale_slm),
1418 EVENT_PTR(td_slots_issued_slm),
1419 EVENT_PTR(td_slots_retired_slm),
1420 NULL
1421 };
1422
1423 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1424 {
1425 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1428 EVENT_EXTRA_END
1429 };
1430
1431 #define SLM_DMND_READ SNB_DMND_DATA_RD
1432 #define SLM_DMND_WRITE SNB_DMND_RFO
1433 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1434
1435 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1436 #define SLM_LLC_ACCESS SNB_RESP_ANY
1437 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1438
1439 static __initconst const u64 slm_hw_cache_extra_regs
1440 [PERF_COUNT_HW_CACHE_MAX]
1441 [PERF_COUNT_HW_CACHE_OP_MAX]
1442 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1443 {
1444 [ C(LL ) ] = {
1445 [ C(OP_READ) ] = {
1446 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1447 [ C(RESULT_MISS) ] = 0,
1448 },
1449 [ C(OP_WRITE) ] = {
1450 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1451 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1452 },
1453 [ C(OP_PREFETCH) ] = {
1454 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1455 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1456 },
1457 },
1458 };
1459
1460 static __initconst const u64 slm_hw_cache_event_ids
1461 [PERF_COUNT_HW_CACHE_MAX]
1462 [PERF_COUNT_HW_CACHE_OP_MAX]
1463 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1464 {
1465 [ C(L1D) ] = {
1466 [ C(OP_READ) ] = {
1467 [ C(RESULT_ACCESS) ] = 0,
1468 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1469 },
1470 [ C(OP_WRITE) ] = {
1471 [ C(RESULT_ACCESS) ] = 0,
1472 [ C(RESULT_MISS) ] = 0,
1473 },
1474 [ C(OP_PREFETCH) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1477 },
1478 },
1479 [ C(L1I ) ] = {
1480 [ C(OP_READ) ] = {
1481 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1482 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1483 },
1484 [ C(OP_WRITE) ] = {
1485 [ C(RESULT_ACCESS) ] = -1,
1486 [ C(RESULT_MISS) ] = -1,
1487 },
1488 [ C(OP_PREFETCH) ] = {
1489 [ C(RESULT_ACCESS) ] = 0,
1490 [ C(RESULT_MISS) ] = 0,
1491 },
1492 },
1493 [ C(LL ) ] = {
1494 [ C(OP_READ) ] = {
1495 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1496 [ C(RESULT_ACCESS) ] = 0x01b7,
1497 [ C(RESULT_MISS) ] = 0,
1498 },
1499 [ C(OP_WRITE) ] = {
1500 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1501 [ C(RESULT_ACCESS) ] = 0x01b7,
1502 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1503 [ C(RESULT_MISS) ] = 0x01b7,
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1507 [ C(RESULT_ACCESS) ] = 0x01b7,
1508 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1509 [ C(RESULT_MISS) ] = 0x01b7,
1510 },
1511 },
1512 [ C(DTLB) ] = {
1513 [ C(OP_READ) ] = {
1514 [ C(RESULT_ACCESS) ] = 0,
1515 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1516 },
1517 [ C(OP_WRITE) ] = {
1518 [ C(RESULT_ACCESS) ] = 0,
1519 [ C(RESULT_MISS) ] = 0,
1520 },
1521 [ C(OP_PREFETCH) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 },
1526 [ C(ITLB) ] = {
1527 [ C(OP_READ) ] = {
1528 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1529 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1530 },
1531 [ C(OP_WRITE) ] = {
1532 [ C(RESULT_ACCESS) ] = -1,
1533 [ C(RESULT_MISS) ] = -1,
1534 },
1535 [ C(OP_PREFETCH) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 },
1540 [ C(BPU ) ] = {
1541 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1543 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1544 },
1545 [ C(OP_WRITE) ] = {
1546 [ C(RESULT_ACCESS) ] = -1,
1547 [ C(RESULT_MISS) ] = -1,
1548 },
1549 [ C(OP_PREFETCH) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 },
1554 };
1555
1556 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1557 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1558 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1559 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1560 EVENT_EXTRA_END
1561 };
1562
1563 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1564 #define GLM_DEMAND_RFO BIT_ULL(1)
1565 #define GLM_ANY_RESPONSE BIT_ULL(16)
1566 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1567 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1568 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1569 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1570 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1571 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1572 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1573
1574 static __initconst const u64 glm_hw_cache_event_ids
1575 [PERF_COUNT_HW_CACHE_MAX]
1576 [PERF_COUNT_HW_CACHE_OP_MAX]
1577 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1578 [C(L1D)] = {
1579 [C(OP_READ)] = {
1580 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1581 [C(RESULT_MISS)] = 0x0,
1582 },
1583 [C(OP_WRITE)] = {
1584 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1585 [C(RESULT_MISS)] = 0x0,
1586 },
1587 [C(OP_PREFETCH)] = {
1588 [C(RESULT_ACCESS)] = 0x0,
1589 [C(RESULT_MISS)] = 0x0,
1590 },
1591 },
1592 [C(L1I)] = {
1593 [C(OP_READ)] = {
1594 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1595 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1596 },
1597 [C(OP_WRITE)] = {
1598 [C(RESULT_ACCESS)] = -1,
1599 [C(RESULT_MISS)] = -1,
1600 },
1601 [C(OP_PREFETCH)] = {
1602 [C(RESULT_ACCESS)] = 0x0,
1603 [C(RESULT_MISS)] = 0x0,
1604 },
1605 },
1606 [C(LL)] = {
1607 [C(OP_READ)] = {
1608 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1609 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1610 },
1611 [C(OP_WRITE)] = {
1612 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1613 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1614 },
1615 [C(OP_PREFETCH)] = {
1616 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1617 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1618 },
1619 },
1620 [C(DTLB)] = {
1621 [C(OP_READ)] = {
1622 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1623 [C(RESULT_MISS)] = 0x0,
1624 },
1625 [C(OP_WRITE)] = {
1626 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1627 [C(RESULT_MISS)] = 0x0,
1628 },
1629 [C(OP_PREFETCH)] = {
1630 [C(RESULT_ACCESS)] = 0x0,
1631 [C(RESULT_MISS)] = 0x0,
1632 },
1633 },
1634 [C(ITLB)] = {
1635 [C(OP_READ)] = {
1636 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1637 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1638 },
1639 [C(OP_WRITE)] = {
1640 [C(RESULT_ACCESS)] = -1,
1641 [C(RESULT_MISS)] = -1,
1642 },
1643 [C(OP_PREFETCH)] = {
1644 [C(RESULT_ACCESS)] = -1,
1645 [C(RESULT_MISS)] = -1,
1646 },
1647 },
1648 [C(BPU)] = {
1649 [C(OP_READ)] = {
1650 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1651 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1652 },
1653 [C(OP_WRITE)] = {
1654 [C(RESULT_ACCESS)] = -1,
1655 [C(RESULT_MISS)] = -1,
1656 },
1657 [C(OP_PREFETCH)] = {
1658 [C(RESULT_ACCESS)] = -1,
1659 [C(RESULT_MISS)] = -1,
1660 },
1661 },
1662 };
1663
1664 static __initconst const u64 glm_hw_cache_extra_regs
1665 [PERF_COUNT_HW_CACHE_MAX]
1666 [PERF_COUNT_HW_CACHE_OP_MAX]
1667 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1668 [C(LL)] = {
1669 [C(OP_READ)] = {
1670 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1671 GLM_LLC_ACCESS,
1672 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1673 GLM_LLC_MISS,
1674 },
1675 [C(OP_WRITE)] = {
1676 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1677 GLM_LLC_ACCESS,
1678 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1679 GLM_LLC_MISS,
1680 },
1681 [C(OP_PREFETCH)] = {
1682 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1683 GLM_LLC_ACCESS,
1684 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1685 GLM_LLC_MISS,
1686 },
1687 },
1688 };
1689
1690 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1691 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1692 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1693 #define KNL_MCDRAM_FAR BIT_ULL(22)
1694 #define KNL_DDR_LOCAL BIT_ULL(23)
1695 #define KNL_DDR_FAR BIT_ULL(24)
1696 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1697 KNL_DDR_LOCAL | KNL_DDR_FAR)
1698 #define KNL_L2_READ SLM_DMND_READ
1699 #define KNL_L2_WRITE SLM_DMND_WRITE
1700 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1701 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1702 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1703 KNL_DRAM_ANY | SNB_SNP_ANY | \
1704 SNB_NON_DRAM)
1705
1706 static __initconst const u64 knl_hw_cache_extra_regs
1707 [PERF_COUNT_HW_CACHE_MAX]
1708 [PERF_COUNT_HW_CACHE_OP_MAX]
1709 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1710 [C(LL)] = {
1711 [C(OP_READ)] = {
1712 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1713 [C(RESULT_MISS)] = 0,
1714 },
1715 [C(OP_WRITE)] = {
1716 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1717 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1718 },
1719 [C(OP_PREFETCH)] = {
1720 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1721 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1722 },
1723 },
1724 };
1725
1726 /*
1727 * Used from PMIs where the LBRs are already disabled.
1728 *
1729 * This function could be called consecutively. It is required to remain in
1730 * disabled state if called consecutively.
1731 *
1732 * During consecutive calls, the same disable value will be written to related
1733 * registers, so the PMU state remains unchanged. hw.state in
1734 * intel_bts_disable_local will remain PERF_HES_STOPPED too in consecutive
1735 * calls.
1736 */
1737 static void __intel_pmu_disable_all(void)
1738 {
1739 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1740
1741 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1742
1743 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1744 intel_pmu_disable_bts();
1745 else
1746 intel_bts_disable_local();
1747
1748 intel_pmu_pebs_disable_all();
1749 }
1750
1751 static void intel_pmu_disable_all(void)
1752 {
1753 __intel_pmu_disable_all();
1754 intel_pmu_lbr_disable_all();
1755 }
1756
1757 static void __intel_pmu_enable_all(int added, bool pmi)
1758 {
1759 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1760
1761 intel_pmu_pebs_enable_all();
1762 intel_pmu_lbr_enable_all(pmi);
1763 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1764 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1765
1766 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1767 struct perf_event *event =
1768 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1769
1770 if (WARN_ON_ONCE(!event))
1771 return;
1772
1773 intel_pmu_enable_bts(event->hw.config);
1774 } else
1775 intel_bts_enable_local();
1776 }
1777
1778 static void intel_pmu_enable_all(int added)
1779 {
1780 __intel_pmu_enable_all(added, false);
1781 }
1782
1783 /*
1784 * Workaround for:
1785 * Intel Errata AAK100 (model 26)
1786 * Intel Errata AAP53 (model 30)
1787 * Intel Errata BD53 (model 44)
1788 *
1789 * The official story:
1790 * These chips need to be 'reset' when adding counters by programming the
1791 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1792 * in sequence on the same PMC or on different PMCs.
1793 *
1794 * In practise it appears some of these events do in fact count, and
1795 * we need to programm all 4 events.
1796 */
1797 static void intel_pmu_nhm_workaround(void)
1798 {
1799 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1800 static const unsigned long nhm_magic[4] = {
1801 0x4300B5,
1802 0x4300D2,
1803 0x4300B1,
1804 0x4300B1
1805 };
1806 struct perf_event *event;
1807 int i;
1808
1809 /*
1810 * The Errata requires below steps:
1811 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1812 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1813 * the corresponding PMCx;
1814 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1815 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1816 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1817 */
1818
1819 /*
1820 * The real steps we choose are a little different from above.
1821 * A) To reduce MSR operations, we don't run step 1) as they
1822 * are already cleared before this function is called;
1823 * B) Call x86_perf_event_update to save PMCx before configuring
1824 * PERFEVTSELx with magic number;
1825 * C) With step 5), we do clear only when the PERFEVTSELx is
1826 * not used currently.
1827 * D) Call x86_perf_event_set_period to restore PMCx;
1828 */
1829
1830 /* We always operate 4 pairs of PERF Counters */
1831 for (i = 0; i < 4; i++) {
1832 event = cpuc->events[i];
1833 if (event)
1834 x86_perf_event_update(event);
1835 }
1836
1837 for (i = 0; i < 4; i++) {
1838 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1839 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1840 }
1841
1842 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1843 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1844
1845 for (i = 0; i < 4; i++) {
1846 event = cpuc->events[i];
1847
1848 if (event) {
1849 x86_perf_event_set_period(event);
1850 __x86_pmu_enable_event(&event->hw,
1851 ARCH_PERFMON_EVENTSEL_ENABLE);
1852 } else
1853 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1854 }
1855 }
1856
1857 static void intel_pmu_nhm_enable_all(int added)
1858 {
1859 if (added)
1860 intel_pmu_nhm_workaround();
1861 intel_pmu_enable_all(added);
1862 }
1863
1864 static inline u64 intel_pmu_get_status(void)
1865 {
1866 u64 status;
1867
1868 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1869
1870 return status;
1871 }
1872
1873 static inline void intel_pmu_ack_status(u64 ack)
1874 {
1875 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1876 }
1877
1878 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1879 {
1880 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1881 u64 ctrl_val, mask;
1882
1883 mask = 0xfULL << (idx * 4);
1884
1885 rdmsrl(hwc->config_base, ctrl_val);
1886 ctrl_val &= ~mask;
1887 wrmsrl(hwc->config_base, ctrl_val);
1888 }
1889
1890 static inline bool event_is_checkpointed(struct perf_event *event)
1891 {
1892 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1893 }
1894
1895 static void intel_pmu_disable_event(struct perf_event *event)
1896 {
1897 struct hw_perf_event *hwc = &event->hw;
1898 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1899
1900 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1901 intel_pmu_disable_bts();
1902 intel_pmu_drain_bts_buffer();
1903 return;
1904 }
1905
1906 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1907 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1908 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1909
1910 /*
1911 * must disable before any actual event
1912 * because any event may be combined with LBR
1913 */
1914 if (needs_branch_stack(event))
1915 intel_pmu_lbr_disable(event);
1916
1917 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1918 intel_pmu_disable_fixed(hwc);
1919 return;
1920 }
1921
1922 x86_pmu_disable_event(event);
1923
1924 if (unlikely(event->attr.precise_ip))
1925 intel_pmu_pebs_disable(event);
1926 }
1927
1928 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1929 {
1930 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1931 u64 ctrl_val, bits, mask;
1932
1933 /*
1934 * Enable IRQ generation (0x8),
1935 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1936 * if requested:
1937 */
1938 bits = 0x8ULL;
1939 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1940 bits |= 0x2;
1941 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1942 bits |= 0x1;
1943
1944 /*
1945 * ANY bit is supported in v3 and up
1946 */
1947 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1948 bits |= 0x4;
1949
1950 bits <<= (idx * 4);
1951 mask = 0xfULL << (idx * 4);
1952
1953 rdmsrl(hwc->config_base, ctrl_val);
1954 ctrl_val &= ~mask;
1955 ctrl_val |= bits;
1956 wrmsrl(hwc->config_base, ctrl_val);
1957 }
1958
1959 static void intel_pmu_enable_event(struct perf_event *event)
1960 {
1961 struct hw_perf_event *hwc = &event->hw;
1962 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1963
1964 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1965 if (!__this_cpu_read(cpu_hw_events.enabled))
1966 return;
1967
1968 intel_pmu_enable_bts(hwc->config);
1969 return;
1970 }
1971 /*
1972 * must enabled before any actual event
1973 * because any event may be combined with LBR
1974 */
1975 if (needs_branch_stack(event))
1976 intel_pmu_lbr_enable(event);
1977
1978 if (event->attr.exclude_host)
1979 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1980 if (event->attr.exclude_guest)
1981 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1982
1983 if (unlikely(event_is_checkpointed(event)))
1984 cpuc->intel_cp_status |= (1ull << hwc->idx);
1985
1986 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1987 intel_pmu_enable_fixed(hwc);
1988 return;
1989 }
1990
1991 if (unlikely(event->attr.precise_ip))
1992 intel_pmu_pebs_enable(event);
1993
1994 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1995 }
1996
1997 /*
1998 * Save and restart an expired event. Called by NMI contexts,
1999 * so it has to be careful about preempting normal event ops:
2000 */
2001 int intel_pmu_save_and_restart(struct perf_event *event)
2002 {
2003 x86_perf_event_update(event);
2004 /*
2005 * For a checkpointed counter always reset back to 0. This
2006 * avoids a situation where the counter overflows, aborts the
2007 * transaction and is then set back to shortly before the
2008 * overflow, and overflows and aborts again.
2009 */
2010 if (unlikely(event_is_checkpointed(event))) {
2011 /* No race with NMIs because the counter should not be armed */
2012 wrmsrl(event->hw.event_base, 0);
2013 local64_set(&event->hw.prev_count, 0);
2014 }
2015 return x86_perf_event_set_period(event);
2016 }
2017
2018 static void intel_pmu_reset(void)
2019 {
2020 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2021 unsigned long flags;
2022 int idx;
2023
2024 if (!x86_pmu.num_counters)
2025 return;
2026
2027 local_irq_save(flags);
2028
2029 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2030
2031 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2032 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2033 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2034 }
2035 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2036 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2037
2038 if (ds)
2039 ds->bts_index = ds->bts_buffer_base;
2040
2041 /* Ack all overflows and disable fixed counters */
2042 if (x86_pmu.version >= 2) {
2043 intel_pmu_ack_status(intel_pmu_get_status());
2044 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2045 }
2046
2047 /* Reset LBRs and LBR freezing */
2048 if (x86_pmu.lbr_nr) {
2049 update_debugctlmsr(get_debugctlmsr() &
2050 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2051 }
2052
2053 local_irq_restore(flags);
2054 }
2055
2056 /*
2057 * This handler is triggered by the local APIC, so the APIC IRQ handling
2058 * rules apply:
2059 */
2060 static int intel_pmu_handle_irq(struct pt_regs *regs)
2061 {
2062 struct perf_sample_data data;
2063 struct cpu_hw_events *cpuc;
2064 int bit, loops;
2065 u64 status;
2066 int handled;
2067
2068 cpuc = this_cpu_ptr(&cpu_hw_events);
2069
2070 /*
2071 * No known reason to not always do late ACK,
2072 * but just in case do it opt-in.
2073 */
2074 if (!x86_pmu.late_ack)
2075 apic_write(APIC_LVTPC, APIC_DM_NMI);
2076 __intel_pmu_disable_all();
2077 handled = intel_pmu_drain_bts_buffer();
2078 handled += intel_bts_interrupt();
2079 status = intel_pmu_get_status();
2080 if (!status)
2081 goto done;
2082
2083 loops = 0;
2084 again:
2085 intel_pmu_lbr_read();
2086 intel_pmu_ack_status(status);
2087 if (++loops > 100) {
2088 static bool warned = false;
2089 if (!warned) {
2090 WARN(1, "perfevents: irq loop stuck!\n");
2091 perf_event_print_debug();
2092 warned = true;
2093 }
2094 intel_pmu_reset();
2095 goto done;
2096 }
2097
2098 inc_irq_stat(apic_perf_irqs);
2099
2100
2101 /*
2102 * Ignore a range of extra bits in status that do not indicate
2103 * overflow by themselves.
2104 */
2105 status &= ~(GLOBAL_STATUS_COND_CHG |
2106 GLOBAL_STATUS_ASIF |
2107 GLOBAL_STATUS_LBRS_FROZEN);
2108 if (!status)
2109 goto done;
2110
2111 /*
2112 * PEBS overflow sets bit 62 in the global status register
2113 */
2114 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2115 handled++;
2116 x86_pmu.drain_pebs(regs);
2117 /*
2118 * There are cases where, even though, the PEBS ovfl bit is set
2119 * in GLOBAL_OVF_STATUS, the PEBS events may also have their
2120 * overflow bits set for their counters. We must clear them
2121 * here because they have been processed as exact samples in
2122 * the drain_pebs() routine. They must not be processed again
2123 * in the for_each_bit_set() loop for regular samples below.
2124 */
2125 status &= ~cpuc->pebs_enabled;
2126 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2127 }
2128
2129 /*
2130 * Intel PT
2131 */
2132 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2133 handled++;
2134 intel_pt_interrupt();
2135 }
2136
2137 /*
2138 * Checkpointed counters can lead to 'spurious' PMIs because the
2139 * rollback caused by the PMI will have cleared the overflow status
2140 * bit. Therefore always force probe these counters.
2141 */
2142 status |= cpuc->intel_cp_status;
2143
2144 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2145 struct perf_event *event = cpuc->events[bit];
2146
2147 handled++;
2148
2149 if (!test_bit(bit, cpuc->active_mask))
2150 continue;
2151
2152 if (!intel_pmu_save_and_restart(event))
2153 continue;
2154
2155 perf_sample_data_init(&data, 0, event->hw.last_period);
2156
2157 if (has_branch_stack(event))
2158 data.br_stack = &cpuc->lbr_stack;
2159
2160 if (perf_event_overflow(event, &data, regs))
2161 x86_pmu_stop(event, 0);
2162 }
2163
2164 /*
2165 * Repeat if there is more work to be done:
2166 */
2167 status = intel_pmu_get_status();
2168 if (status)
2169 goto again;
2170
2171 done:
2172 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2173 if (cpuc->enabled)
2174 __intel_pmu_enable_all(0, true);
2175
2176 /*
2177 * Only unmask the NMI after the overflow counters
2178 * have been reset. This avoids spurious NMIs on
2179 * Haswell CPUs.
2180 */
2181 if (x86_pmu.late_ack)
2182 apic_write(APIC_LVTPC, APIC_DM_NMI);
2183 return handled;
2184 }
2185
2186 static struct event_constraint *
2187 intel_bts_constraints(struct perf_event *event)
2188 {
2189 struct hw_perf_event *hwc = &event->hw;
2190 unsigned int hw_event, bts_event;
2191
2192 if (event->attr.freq)
2193 return NULL;
2194
2195 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2196 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
2197
2198 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
2199 return &bts_constraint;
2200
2201 return NULL;
2202 }
2203
2204 static int intel_alt_er(int idx, u64 config)
2205 {
2206 int alt_idx = idx;
2207
2208 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2209 return idx;
2210
2211 if (idx == EXTRA_REG_RSP_0)
2212 alt_idx = EXTRA_REG_RSP_1;
2213
2214 if (idx == EXTRA_REG_RSP_1)
2215 alt_idx = EXTRA_REG_RSP_0;
2216
2217 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2218 return idx;
2219
2220 return alt_idx;
2221 }
2222
2223 static void intel_fixup_er(struct perf_event *event, int idx)
2224 {
2225 event->hw.extra_reg.idx = idx;
2226
2227 if (idx == EXTRA_REG_RSP_0) {
2228 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2229 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2230 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2231 } else if (idx == EXTRA_REG_RSP_1) {
2232 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2233 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2234 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2235 }
2236 }
2237
2238 /*
2239 * manage allocation of shared extra msr for certain events
2240 *
2241 * sharing can be:
2242 * per-cpu: to be shared between the various events on a single PMU
2243 * per-core: per-cpu + shared by HT threads
2244 */
2245 static struct event_constraint *
2246 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2247 struct perf_event *event,
2248 struct hw_perf_event_extra *reg)
2249 {
2250 struct event_constraint *c = &emptyconstraint;
2251 struct er_account *era;
2252 unsigned long flags;
2253 int idx = reg->idx;
2254
2255 /*
2256 * reg->alloc can be set due to existing state, so for fake cpuc we
2257 * need to ignore this, otherwise we might fail to allocate proper fake
2258 * state for this extra reg constraint. Also see the comment below.
2259 */
2260 if (reg->alloc && !cpuc->is_fake)
2261 return NULL; /* call x86_get_event_constraint() */
2262
2263 again:
2264 era = &cpuc->shared_regs->regs[idx];
2265 /*
2266 * we use spin_lock_irqsave() to avoid lockdep issues when
2267 * passing a fake cpuc
2268 */
2269 raw_spin_lock_irqsave(&era->lock, flags);
2270
2271 if (!atomic_read(&era->ref) || era->config == reg->config) {
2272
2273 /*
2274 * If its a fake cpuc -- as per validate_{group,event}() we
2275 * shouldn't touch event state and we can avoid doing so
2276 * since both will only call get_event_constraints() once
2277 * on each event, this avoids the need for reg->alloc.
2278 *
2279 * Not doing the ER fixup will only result in era->reg being
2280 * wrong, but since we won't actually try and program hardware
2281 * this isn't a problem either.
2282 */
2283 if (!cpuc->is_fake) {
2284 if (idx != reg->idx)
2285 intel_fixup_er(event, idx);
2286
2287 /*
2288 * x86_schedule_events() can call get_event_constraints()
2289 * multiple times on events in the case of incremental
2290 * scheduling(). reg->alloc ensures we only do the ER
2291 * allocation once.
2292 */
2293 reg->alloc = 1;
2294 }
2295
2296 /* lock in msr value */
2297 era->config = reg->config;
2298 era->reg = reg->reg;
2299
2300 /* one more user */
2301 atomic_inc(&era->ref);
2302
2303 /*
2304 * need to call x86_get_event_constraint()
2305 * to check if associated event has constraints
2306 */
2307 c = NULL;
2308 } else {
2309 idx = intel_alt_er(idx, reg->config);
2310 if (idx != reg->idx) {
2311 raw_spin_unlock_irqrestore(&era->lock, flags);
2312 goto again;
2313 }
2314 }
2315 raw_spin_unlock_irqrestore(&era->lock, flags);
2316
2317 return c;
2318 }
2319
2320 static void
2321 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2322 struct hw_perf_event_extra *reg)
2323 {
2324 struct er_account *era;
2325
2326 /*
2327 * Only put constraint if extra reg was actually allocated. Also takes
2328 * care of event which do not use an extra shared reg.
2329 *
2330 * Also, if this is a fake cpuc we shouldn't touch any event state
2331 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2332 * either since it'll be thrown out.
2333 */
2334 if (!reg->alloc || cpuc->is_fake)
2335 return;
2336
2337 era = &cpuc->shared_regs->regs[reg->idx];
2338
2339 /* one fewer user */
2340 atomic_dec(&era->ref);
2341
2342 /* allocate again next time */
2343 reg->alloc = 0;
2344 }
2345
2346 static struct event_constraint *
2347 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2348 struct perf_event *event)
2349 {
2350 struct event_constraint *c = NULL, *d;
2351 struct hw_perf_event_extra *xreg, *breg;
2352
2353 xreg = &event->hw.extra_reg;
2354 if (xreg->idx != EXTRA_REG_NONE) {
2355 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2356 if (c == &emptyconstraint)
2357 return c;
2358 }
2359 breg = &event->hw.branch_reg;
2360 if (breg->idx != EXTRA_REG_NONE) {
2361 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2362 if (d == &emptyconstraint) {
2363 __intel_shared_reg_put_constraints(cpuc, xreg);
2364 c = d;
2365 }
2366 }
2367 return c;
2368 }
2369
2370 struct event_constraint *
2371 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2372 struct perf_event *event)
2373 {
2374 struct event_constraint *c;
2375
2376 if (x86_pmu.event_constraints) {
2377 for_each_event_constraint(c, x86_pmu.event_constraints) {
2378 if ((event->hw.config & c->cmask) == c->code) {
2379 event->hw.flags |= c->flags;
2380 return c;
2381 }
2382 }
2383 }
2384
2385 return &unconstrained;
2386 }
2387
2388 static struct event_constraint *
2389 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2390 struct perf_event *event)
2391 {
2392 struct event_constraint *c;
2393
2394 c = intel_bts_constraints(event);
2395 if (c)
2396 return c;
2397
2398 c = intel_shared_regs_constraints(cpuc, event);
2399 if (c)
2400 return c;
2401
2402 c = intel_pebs_constraints(event);
2403 if (c)
2404 return c;
2405
2406 return x86_get_event_constraints(cpuc, idx, event);
2407 }
2408
2409 static void
2410 intel_start_scheduling(struct cpu_hw_events *cpuc)
2411 {
2412 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2413 struct intel_excl_states *xl;
2414 int tid = cpuc->excl_thread_id;
2415
2416 /*
2417 * nothing needed if in group validation mode
2418 */
2419 if (cpuc->is_fake || !is_ht_workaround_enabled())
2420 return;
2421
2422 /*
2423 * no exclusion needed
2424 */
2425 if (WARN_ON_ONCE(!excl_cntrs))
2426 return;
2427
2428 xl = &excl_cntrs->states[tid];
2429
2430 xl->sched_started = true;
2431 /*
2432 * lock shared state until we are done scheduling
2433 * in stop_event_scheduling()
2434 * makes scheduling appear as a transaction
2435 */
2436 raw_spin_lock(&excl_cntrs->lock);
2437 }
2438
2439 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2440 {
2441 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2442 struct event_constraint *c = cpuc->event_constraint[idx];
2443 struct intel_excl_states *xl;
2444 int tid = cpuc->excl_thread_id;
2445
2446 if (cpuc->is_fake || !is_ht_workaround_enabled())
2447 return;
2448
2449 if (WARN_ON_ONCE(!excl_cntrs))
2450 return;
2451
2452 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2453 return;
2454
2455 xl = &excl_cntrs->states[tid];
2456
2457 lockdep_assert_held(&excl_cntrs->lock);
2458
2459 if (c->flags & PERF_X86_EVENT_EXCL)
2460 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2461 else
2462 xl->state[cntr] = INTEL_EXCL_SHARED;
2463 }
2464
2465 static void
2466 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2467 {
2468 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2469 struct intel_excl_states *xl;
2470 int tid = cpuc->excl_thread_id;
2471
2472 /*
2473 * nothing needed if in group validation mode
2474 */
2475 if (cpuc->is_fake || !is_ht_workaround_enabled())
2476 return;
2477 /*
2478 * no exclusion needed
2479 */
2480 if (WARN_ON_ONCE(!excl_cntrs))
2481 return;
2482
2483 xl = &excl_cntrs->states[tid];
2484
2485 xl->sched_started = false;
2486 /*
2487 * release shared state lock (acquired in intel_start_scheduling())
2488 */
2489 raw_spin_unlock(&excl_cntrs->lock);
2490 }
2491
2492 static struct event_constraint *
2493 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2494 int idx, struct event_constraint *c)
2495 {
2496 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2497 struct intel_excl_states *xlo;
2498 int tid = cpuc->excl_thread_id;
2499 int is_excl, i;
2500
2501 /*
2502 * validating a group does not require
2503 * enforcing cross-thread exclusion
2504 */
2505 if (cpuc->is_fake || !is_ht_workaround_enabled())
2506 return c;
2507
2508 /*
2509 * no exclusion needed
2510 */
2511 if (WARN_ON_ONCE(!excl_cntrs))
2512 return c;
2513
2514 /*
2515 * because we modify the constraint, we need
2516 * to make a copy. Static constraints come
2517 * from static const tables.
2518 *
2519 * only needed when constraint has not yet
2520 * been cloned (marked dynamic)
2521 */
2522 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2523 struct event_constraint *cx;
2524
2525 /*
2526 * grab pre-allocated constraint entry
2527 */
2528 cx = &cpuc->constraint_list[idx];
2529
2530 /*
2531 * initialize dynamic constraint
2532 * with static constraint
2533 */
2534 *cx = *c;
2535
2536 /*
2537 * mark constraint as dynamic, so we
2538 * can free it later on
2539 */
2540 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2541 c = cx;
2542 }
2543
2544 /*
2545 * From here on, the constraint is dynamic.
2546 * Either it was just allocated above, or it
2547 * was allocated during a earlier invocation
2548 * of this function
2549 */
2550
2551 /*
2552 * state of sibling HT
2553 */
2554 xlo = &excl_cntrs->states[tid ^ 1];
2555
2556 /*
2557 * event requires exclusive counter access
2558 * across HT threads
2559 */
2560 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2561 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2562 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2563 if (!cpuc->n_excl++)
2564 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2565 }
2566
2567 /*
2568 * Modify static constraint with current dynamic
2569 * state of thread
2570 *
2571 * EXCLUSIVE: sibling counter measuring exclusive event
2572 * SHARED : sibling counter measuring non-exclusive event
2573 * UNUSED : sibling counter unused
2574 */
2575 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2576 /*
2577 * exclusive event in sibling counter
2578 * our corresponding counter cannot be used
2579 * regardless of our event
2580 */
2581 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2582 __clear_bit(i, c->idxmsk);
2583 /*
2584 * if measuring an exclusive event, sibling
2585 * measuring non-exclusive, then counter cannot
2586 * be used
2587 */
2588 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2589 __clear_bit(i, c->idxmsk);
2590 }
2591
2592 /*
2593 * recompute actual bit weight for scheduling algorithm
2594 */
2595 c->weight = hweight64(c->idxmsk64);
2596
2597 /*
2598 * if we return an empty mask, then switch
2599 * back to static empty constraint to avoid
2600 * the cost of freeing later on
2601 */
2602 if (c->weight == 0)
2603 c = &emptyconstraint;
2604
2605 return c;
2606 }
2607
2608 static struct event_constraint *
2609 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2610 struct perf_event *event)
2611 {
2612 struct event_constraint *c1 = NULL;
2613 struct event_constraint *c2;
2614
2615 if (idx >= 0) /* fake does < 0 */
2616 c1 = cpuc->event_constraint[idx];
2617
2618 /*
2619 * first time only
2620 * - static constraint: no change across incremental scheduling calls
2621 * - dynamic constraint: handled by intel_get_excl_constraints()
2622 */
2623 c2 = __intel_get_event_constraints(cpuc, idx, event);
2624 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2625 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2626 c1->weight = c2->weight;
2627 c2 = c1;
2628 }
2629
2630 if (cpuc->excl_cntrs)
2631 return intel_get_excl_constraints(cpuc, event, idx, c2);
2632
2633 return c2;
2634 }
2635
2636 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2637 struct perf_event *event)
2638 {
2639 struct hw_perf_event *hwc = &event->hw;
2640 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2641 int tid = cpuc->excl_thread_id;
2642 struct intel_excl_states *xl;
2643
2644 /*
2645 * nothing needed if in group validation mode
2646 */
2647 if (cpuc->is_fake)
2648 return;
2649
2650 if (WARN_ON_ONCE(!excl_cntrs))
2651 return;
2652
2653 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2654 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2655 if (!--cpuc->n_excl)
2656 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2657 }
2658
2659 /*
2660 * If event was actually assigned, then mark the counter state as
2661 * unused now.
2662 */
2663 if (hwc->idx >= 0) {
2664 xl = &excl_cntrs->states[tid];
2665
2666 /*
2667 * put_constraint may be called from x86_schedule_events()
2668 * which already has the lock held so here make locking
2669 * conditional.
2670 */
2671 if (!xl->sched_started)
2672 raw_spin_lock(&excl_cntrs->lock);
2673
2674 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2675
2676 if (!xl->sched_started)
2677 raw_spin_unlock(&excl_cntrs->lock);
2678 }
2679 }
2680
2681 static void
2682 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2683 struct perf_event *event)
2684 {
2685 struct hw_perf_event_extra *reg;
2686
2687 reg = &event->hw.extra_reg;
2688 if (reg->idx != EXTRA_REG_NONE)
2689 __intel_shared_reg_put_constraints(cpuc, reg);
2690
2691 reg = &event->hw.branch_reg;
2692 if (reg->idx != EXTRA_REG_NONE)
2693 __intel_shared_reg_put_constraints(cpuc, reg);
2694 }
2695
2696 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2697 struct perf_event *event)
2698 {
2699 intel_put_shared_regs_event_constraints(cpuc, event);
2700
2701 /*
2702 * is PMU has exclusive counter restrictions, then
2703 * all events are subject to and must call the
2704 * put_excl_constraints() routine
2705 */
2706 if (cpuc->excl_cntrs)
2707 intel_put_excl_constraints(cpuc, event);
2708 }
2709
2710 static void intel_pebs_aliases_core2(struct perf_event *event)
2711 {
2712 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2713 /*
2714 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2715 * (0x003c) so that we can use it with PEBS.
2716 *
2717 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2718 * PEBS capable. However we can use INST_RETIRED.ANY_P
2719 * (0x00c0), which is a PEBS capable event, to get the same
2720 * count.
2721 *
2722 * INST_RETIRED.ANY_P counts the number of cycles that retires
2723 * CNTMASK instructions. By setting CNTMASK to a value (16)
2724 * larger than the maximum number of instructions that can be
2725 * retired per cycle (4) and then inverting the condition, we
2726 * count all cycles that retire 16 or less instructions, which
2727 * is every cycle.
2728 *
2729 * Thereby we gain a PEBS capable cycle counter.
2730 */
2731 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2732
2733 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2734 event->hw.config = alt_config;
2735 }
2736 }
2737
2738 static void intel_pebs_aliases_snb(struct perf_event *event)
2739 {
2740 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2741 /*
2742 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2743 * (0x003c) so that we can use it with PEBS.
2744 *
2745 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2746 * PEBS capable. However we can use UOPS_RETIRED.ALL
2747 * (0x01c2), which is a PEBS capable event, to get the same
2748 * count.
2749 *
2750 * UOPS_RETIRED.ALL counts the number of cycles that retires
2751 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2752 * larger than the maximum number of micro-ops that can be
2753 * retired per cycle (4) and then inverting the condition, we
2754 * count all cycles that retire 16 or less micro-ops, which
2755 * is every cycle.
2756 *
2757 * Thereby we gain a PEBS capable cycle counter.
2758 */
2759 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2760
2761 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2762 event->hw.config = alt_config;
2763 }
2764 }
2765
2766 static void intel_pebs_aliases_precdist(struct perf_event *event)
2767 {
2768 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2769 /*
2770 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2771 * (0x003c) so that we can use it with PEBS.
2772 *
2773 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2774 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2775 * (0x01c0), which is a PEBS capable event, to get the same
2776 * count.
2777 *
2778 * The PREC_DIST event has special support to minimize sample
2779 * shadowing effects. One drawback is that it can be
2780 * only programmed on counter 1, but that seems like an
2781 * acceptable trade off.
2782 */
2783 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2784
2785 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2786 event->hw.config = alt_config;
2787 }
2788 }
2789
2790 static void intel_pebs_aliases_ivb(struct perf_event *event)
2791 {
2792 if (event->attr.precise_ip < 3)
2793 return intel_pebs_aliases_snb(event);
2794 return intel_pebs_aliases_precdist(event);
2795 }
2796
2797 static void intel_pebs_aliases_skl(struct perf_event *event)
2798 {
2799 if (event->attr.precise_ip < 3)
2800 return intel_pebs_aliases_core2(event);
2801 return intel_pebs_aliases_precdist(event);
2802 }
2803
2804 static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2805 {
2806 unsigned long flags = x86_pmu.free_running_flags;
2807
2808 if (event->attr.use_clockid)
2809 flags &= ~PERF_SAMPLE_TIME;
2810 return flags;
2811 }
2812
2813 static int intel_pmu_hw_config(struct perf_event *event)
2814 {
2815 int ret = x86_pmu_hw_config(event);
2816
2817 if (ret)
2818 return ret;
2819
2820 if (event->attr.precise_ip) {
2821 if (!event->attr.freq) {
2822 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2823 if (!(event->attr.sample_type &
2824 ~intel_pmu_free_running_flags(event)))
2825 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2826 }
2827 if (x86_pmu.pebs_aliases)
2828 x86_pmu.pebs_aliases(event);
2829 }
2830
2831 if (needs_branch_stack(event)) {
2832 ret = intel_pmu_setup_lbr_filter(event);
2833 if (ret)
2834 return ret;
2835
2836 /*
2837 * BTS is set up earlier in this path, so don't account twice
2838 */
2839 if (!intel_pmu_has_bts(event)) {
2840 /* disallow lbr if conflicting events are present */
2841 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2842 return -EBUSY;
2843
2844 event->destroy = hw_perf_lbr_event_destroy;
2845 }
2846 }
2847
2848 if (event->attr.type != PERF_TYPE_RAW)
2849 return 0;
2850
2851 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2852 return 0;
2853
2854 if (x86_pmu.version < 3)
2855 return -EINVAL;
2856
2857 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2858 return -EACCES;
2859
2860 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2861
2862 return 0;
2863 }
2864
2865 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2866 {
2867 if (x86_pmu.guest_get_msrs)
2868 return x86_pmu.guest_get_msrs(nr);
2869 *nr = 0;
2870 return NULL;
2871 }
2872 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2873
2874 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2875 {
2876 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2877 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2878
2879 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2880 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2881 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2882 /*
2883 * If PMU counter has PEBS enabled it is not enough to disable counter
2884 * on a guest entry since PEBS memory write can overshoot guest entry
2885 * and corrupt guest memory. Disabling PEBS solves the problem.
2886 */
2887 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2888 arr[1].host = cpuc->pebs_enabled;
2889 arr[1].guest = 0;
2890
2891 *nr = 2;
2892 return arr;
2893 }
2894
2895 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2896 {
2897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2898 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2899 int idx;
2900
2901 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2902 struct perf_event *event = cpuc->events[idx];
2903
2904 arr[idx].msr = x86_pmu_config_addr(idx);
2905 arr[idx].host = arr[idx].guest = 0;
2906
2907 if (!test_bit(idx, cpuc->active_mask))
2908 continue;
2909
2910 arr[idx].host = arr[idx].guest =
2911 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2912
2913 if (event->attr.exclude_host)
2914 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2915 else if (event->attr.exclude_guest)
2916 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2917 }
2918
2919 *nr = x86_pmu.num_counters;
2920 return arr;
2921 }
2922
2923 static void core_pmu_enable_event(struct perf_event *event)
2924 {
2925 if (!event->attr.exclude_host)
2926 x86_pmu_enable_event(event);
2927 }
2928
2929 static void core_pmu_enable_all(int added)
2930 {
2931 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2932 int idx;
2933
2934 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2935 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2936
2937 if (!test_bit(idx, cpuc->active_mask) ||
2938 cpuc->events[idx]->attr.exclude_host)
2939 continue;
2940
2941 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2942 }
2943 }
2944
2945 static int hsw_hw_config(struct perf_event *event)
2946 {
2947 int ret = intel_pmu_hw_config(event);
2948
2949 if (ret)
2950 return ret;
2951 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2952 return 0;
2953 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2954
2955 /*
2956 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2957 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2958 * this combination.
2959 */
2960 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2961 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2962 event->attr.precise_ip > 0))
2963 return -EOPNOTSUPP;
2964
2965 if (event_is_checkpointed(event)) {
2966 /*
2967 * Sampling of checkpointed events can cause situations where
2968 * the CPU constantly aborts because of a overflow, which is
2969 * then checkpointed back and ignored. Forbid checkpointing
2970 * for sampling.
2971 *
2972 * But still allow a long sampling period, so that perf stat
2973 * from KVM works.
2974 */
2975 if (event->attr.sample_period > 0 &&
2976 event->attr.sample_period < 0x7fffffff)
2977 return -EOPNOTSUPP;
2978 }
2979 return 0;
2980 }
2981
2982 static struct event_constraint counter2_constraint =
2983 EVENT_CONSTRAINT(0, 0x4, 0);
2984
2985 static struct event_constraint *
2986 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2987 struct perf_event *event)
2988 {
2989 struct event_constraint *c;
2990
2991 c = intel_get_event_constraints(cpuc, idx, event);
2992
2993 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2994 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2995 if (c->idxmsk64 & (1U << 2))
2996 return &counter2_constraint;
2997 return &emptyconstraint;
2998 }
2999
3000 return c;
3001 }
3002
3003 /*
3004 * Broadwell:
3005 *
3006 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3007 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3008 * the two to enforce a minimum period of 128 (the smallest value that has bits
3009 * 0-5 cleared and >= 100).
3010 *
3011 * Because of how the code in x86_perf_event_set_period() works, the truncation
3012 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3013 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3014 *
3015 * Therefore the effective (average) period matches the requested period,
3016 * despite coarser hardware granularity.
3017 */
3018 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
3019 {
3020 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3021 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3022 if (left < 128)
3023 left = 128;
3024 left &= ~0x3fu;
3025 }
3026 return left;
3027 }
3028
3029 PMU_FORMAT_ATTR(event, "config:0-7" );
3030 PMU_FORMAT_ATTR(umask, "config:8-15" );
3031 PMU_FORMAT_ATTR(edge, "config:18" );
3032 PMU_FORMAT_ATTR(pc, "config:19" );
3033 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3034 PMU_FORMAT_ATTR(inv, "config:23" );
3035 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3036 PMU_FORMAT_ATTR(in_tx, "config:32");
3037 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3038
3039 static struct attribute *intel_arch_formats_attr[] = {
3040 &format_attr_event.attr,
3041 &format_attr_umask.attr,
3042 &format_attr_edge.attr,
3043 &format_attr_pc.attr,
3044 &format_attr_inv.attr,
3045 &format_attr_cmask.attr,
3046 NULL,
3047 };
3048
3049 ssize_t intel_event_sysfs_show(char *page, u64 config)
3050 {
3051 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3052
3053 return x86_event_sysfs_show(page, config, event);
3054 }
3055
3056 struct intel_shared_regs *allocate_shared_regs(int cpu)
3057 {
3058 struct intel_shared_regs *regs;
3059 int i;
3060
3061 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3062 GFP_KERNEL, cpu_to_node(cpu));
3063 if (regs) {
3064 /*
3065 * initialize the locks to keep lockdep happy
3066 */
3067 for (i = 0; i < EXTRA_REG_MAX; i++)
3068 raw_spin_lock_init(&regs->regs[i].lock);
3069
3070 regs->core_id = -1;
3071 }
3072 return regs;
3073 }
3074
3075 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3076 {
3077 struct intel_excl_cntrs *c;
3078
3079 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3080 GFP_KERNEL, cpu_to_node(cpu));
3081 if (c) {
3082 raw_spin_lock_init(&c->lock);
3083 c->core_id = -1;
3084 }
3085 return c;
3086 }
3087
3088 static int intel_pmu_cpu_prepare(int cpu)
3089 {
3090 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3091
3092 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3093 cpuc->shared_regs = allocate_shared_regs(cpu);
3094 if (!cpuc->shared_regs)
3095 goto err;
3096 }
3097
3098 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3099 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3100
3101 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3102 if (!cpuc->constraint_list)
3103 goto err_shared_regs;
3104
3105 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3106 if (!cpuc->excl_cntrs)
3107 goto err_constraint_list;
3108
3109 cpuc->excl_thread_id = 0;
3110 }
3111
3112 return 0;
3113
3114 err_constraint_list:
3115 kfree(cpuc->constraint_list);
3116 cpuc->constraint_list = NULL;
3117
3118 err_shared_regs:
3119 kfree(cpuc->shared_regs);
3120 cpuc->shared_regs = NULL;
3121
3122 err:
3123 return -ENOMEM;
3124 }
3125
3126 static void intel_pmu_cpu_starting(int cpu)
3127 {
3128 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3129 int core_id = topology_core_id(cpu);
3130 int i;
3131
3132 init_debug_store_on_cpu(cpu);
3133 /*
3134 * Deal with CPUs that don't clear their LBRs on power-up.
3135 */
3136 intel_pmu_lbr_reset();
3137
3138 cpuc->lbr_sel = NULL;
3139
3140 if (!cpuc->shared_regs)
3141 return;
3142
3143 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3144 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3145 struct intel_shared_regs *pc;
3146
3147 pc = per_cpu(cpu_hw_events, i).shared_regs;
3148 if (pc && pc->core_id == core_id) {
3149 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3150 cpuc->shared_regs = pc;
3151 break;
3152 }
3153 }
3154 cpuc->shared_regs->core_id = core_id;
3155 cpuc->shared_regs->refcnt++;
3156 }
3157
3158 if (x86_pmu.lbr_sel_map)
3159 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3160
3161 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3162 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3163 struct intel_excl_cntrs *c;
3164
3165 c = per_cpu(cpu_hw_events, i).excl_cntrs;
3166 if (c && c->core_id == core_id) {
3167 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3168 cpuc->excl_cntrs = c;
3169 cpuc->excl_thread_id = 1;
3170 break;
3171 }
3172 }
3173 cpuc->excl_cntrs->core_id = core_id;
3174 cpuc->excl_cntrs->refcnt++;
3175 }
3176 }
3177
3178 static void free_excl_cntrs(int cpu)
3179 {
3180 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3181 struct intel_excl_cntrs *c;
3182
3183 c = cpuc->excl_cntrs;
3184 if (c) {
3185 if (c->core_id == -1 || --c->refcnt == 0)
3186 kfree(c);
3187 cpuc->excl_cntrs = NULL;
3188 kfree(cpuc->constraint_list);
3189 cpuc->constraint_list = NULL;
3190 }
3191 }
3192
3193 static void intel_pmu_cpu_dying(int cpu)
3194 {
3195 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3196 struct intel_shared_regs *pc;
3197
3198 pc = cpuc->shared_regs;
3199 if (pc) {
3200 if (pc->core_id == -1 || --pc->refcnt == 0)
3201 kfree(pc);
3202 cpuc->shared_regs = NULL;
3203 }
3204
3205 free_excl_cntrs(cpu);
3206
3207 fini_debug_store_on_cpu(cpu);
3208 }
3209
3210 static void intel_pmu_sched_task(struct perf_event_context *ctx,
3211 bool sched_in)
3212 {
3213 if (x86_pmu.pebs_active)
3214 intel_pmu_pebs_sched_task(ctx, sched_in);
3215 if (x86_pmu.lbr_nr)
3216 intel_pmu_lbr_sched_task(ctx, sched_in);
3217 }
3218
3219 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3220
3221 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3222
3223 PMU_FORMAT_ATTR(frontend, "config1:0-23");
3224
3225 static struct attribute *intel_arch3_formats_attr[] = {
3226 &format_attr_event.attr,
3227 &format_attr_umask.attr,
3228 &format_attr_edge.attr,
3229 &format_attr_pc.attr,
3230 &format_attr_any.attr,
3231 &format_attr_inv.attr,
3232 &format_attr_cmask.attr,
3233 &format_attr_in_tx.attr,
3234 &format_attr_in_tx_cp.attr,
3235
3236 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
3237 &format_attr_ldlat.attr, /* PEBS load latency */
3238 NULL,
3239 };
3240
3241 static struct attribute *skl_format_attr[] = {
3242 &format_attr_frontend.attr,
3243 NULL,
3244 };
3245
3246 static __initconst const struct x86_pmu core_pmu = {
3247 .name = "core",
3248 .handle_irq = x86_pmu_handle_irq,
3249 .disable_all = x86_pmu_disable_all,
3250 .enable_all = core_pmu_enable_all,
3251 .enable = core_pmu_enable_event,
3252 .disable = x86_pmu_disable_event,
3253 .hw_config = x86_pmu_hw_config,
3254 .schedule_events = x86_schedule_events,
3255 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3256 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3257 .event_map = intel_pmu_event_map,
3258 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3259 .apic = 1,
3260 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3261
3262 /*
3263 * Intel PMCs cannot be accessed sanely above 32-bit width,
3264 * so we install an artificial 1<<31 period regardless of
3265 * the generic event period:
3266 */
3267 .max_period = (1ULL<<31) - 1,
3268 .get_event_constraints = intel_get_event_constraints,
3269 .put_event_constraints = intel_put_event_constraints,
3270 .event_constraints = intel_core_event_constraints,
3271 .guest_get_msrs = core_guest_get_msrs,
3272 .format_attrs = intel_arch_formats_attr,
3273 .events_sysfs_show = intel_event_sysfs_show,
3274
3275 /*
3276 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3277 * together with PMU version 1 and thus be using core_pmu with
3278 * shared_regs. We need following callbacks here to allocate
3279 * it properly.
3280 */
3281 .cpu_prepare = intel_pmu_cpu_prepare,
3282 .cpu_starting = intel_pmu_cpu_starting,
3283 .cpu_dying = intel_pmu_cpu_dying,
3284 };
3285
3286 static __initconst const struct x86_pmu intel_pmu = {
3287 .name = "Intel",
3288 .handle_irq = intel_pmu_handle_irq,
3289 .disable_all = intel_pmu_disable_all,
3290 .enable_all = intel_pmu_enable_all,
3291 .enable = intel_pmu_enable_event,
3292 .disable = intel_pmu_disable_event,
3293 .hw_config = intel_pmu_hw_config,
3294 .schedule_events = x86_schedule_events,
3295 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3296 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3297 .event_map = intel_pmu_event_map,
3298 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3299 .apic = 1,
3300 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3301 /*
3302 * Intel PMCs cannot be accessed sanely above 32 bit width,
3303 * so we install an artificial 1<<31 period regardless of
3304 * the generic event period:
3305 */
3306 .max_period = (1ULL << 31) - 1,
3307 .get_event_constraints = intel_get_event_constraints,
3308 .put_event_constraints = intel_put_event_constraints,
3309 .pebs_aliases = intel_pebs_aliases_core2,
3310
3311 .format_attrs = intel_arch3_formats_attr,
3312 .events_sysfs_show = intel_event_sysfs_show,
3313
3314 .cpu_prepare = intel_pmu_cpu_prepare,
3315 .cpu_starting = intel_pmu_cpu_starting,
3316 .cpu_dying = intel_pmu_cpu_dying,
3317 .guest_get_msrs = intel_guest_get_msrs,
3318 .sched_task = intel_pmu_sched_task,
3319 };
3320
3321 static __init void intel_clovertown_quirk(void)
3322 {
3323 /*
3324 * PEBS is unreliable due to:
3325 *
3326 * AJ67 - PEBS may experience CPL leaks
3327 * AJ68 - PEBS PMI may be delayed by one event
3328 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3329 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3330 *
3331 * AJ67 could be worked around by restricting the OS/USR flags.
3332 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3333 *
3334 * AJ106 could possibly be worked around by not allowing LBR
3335 * usage from PEBS, including the fixup.
3336 * AJ68 could possibly be worked around by always programming
3337 * a pebs_event_reset[0] value and coping with the lost events.
3338 *
3339 * But taken together it might just make sense to not enable PEBS on
3340 * these chips.
3341 */
3342 pr_warn("PEBS disabled due to CPU errata\n");
3343 x86_pmu.pebs = 0;
3344 x86_pmu.pebs_constraints = NULL;
3345 }
3346
3347 static int intel_snb_pebs_broken(int cpu)
3348 {
3349 u32 rev = UINT_MAX; /* default to broken for unknown models */
3350
3351 switch (cpu_data(cpu).x86_model) {
3352 case INTEL_FAM6_SANDYBRIDGE:
3353 rev = 0x28;
3354 break;
3355
3356 case INTEL_FAM6_SANDYBRIDGE_X:
3357 switch (cpu_data(cpu).x86_mask) {
3358 case 6: rev = 0x618; break;
3359 case 7: rev = 0x70c; break;
3360 }
3361 }
3362
3363 return (cpu_data(cpu).microcode < rev);
3364 }
3365
3366 static void intel_snb_check_microcode(void)
3367 {
3368 int pebs_broken = 0;
3369 int cpu;
3370
3371 get_online_cpus();
3372 for_each_online_cpu(cpu) {
3373 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3374 break;
3375 }
3376 put_online_cpus();
3377
3378 if (pebs_broken == x86_pmu.pebs_broken)
3379 return;
3380
3381 /*
3382 * Serialized by the microcode lock..
3383 */
3384 if (x86_pmu.pebs_broken) {
3385 pr_info("PEBS enabled due to microcode update\n");
3386 x86_pmu.pebs_broken = 0;
3387 } else {
3388 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3389 x86_pmu.pebs_broken = 1;
3390 }
3391 }
3392
3393 static bool is_lbr_from(unsigned long msr)
3394 {
3395 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
3396
3397 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
3398 }
3399
3400 /*
3401 * Under certain circumstances, access certain MSR may cause #GP.
3402 * The function tests if the input MSR can be safely accessed.
3403 */
3404 static bool check_msr(unsigned long msr, u64 mask)
3405 {
3406 u64 val_old, val_new, val_tmp;
3407
3408 /*
3409 * Read the current value, change it and read it back to see if it
3410 * matches, this is needed to detect certain hardware emulators
3411 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3412 */
3413 if (rdmsrl_safe(msr, &val_old))
3414 return false;
3415
3416 /*
3417 * Only change the bits which can be updated by wrmsrl.
3418 */
3419 val_tmp = val_old ^ mask;
3420
3421 if (is_lbr_from(msr))
3422 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
3423
3424 if (wrmsrl_safe(msr, val_tmp) ||
3425 rdmsrl_safe(msr, &val_new))
3426 return false;
3427
3428 /*
3429 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
3430 * should equal rdmsrl()'s even with the quirk.
3431 */
3432 if (val_new != val_tmp)
3433 return false;
3434
3435 if (is_lbr_from(msr))
3436 val_old = lbr_from_signext_quirk_wr(val_old);
3437
3438 /* Here it's sure that the MSR can be safely accessed.
3439 * Restore the old value and return.
3440 */
3441 wrmsrl(msr, val_old);
3442
3443 return true;
3444 }
3445
3446 static __init void intel_sandybridge_quirk(void)
3447 {
3448 x86_pmu.check_microcode = intel_snb_check_microcode;
3449 intel_snb_check_microcode();
3450 }
3451
3452 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3453 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3454 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3455 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3456 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3457 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3458 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3459 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3460 };
3461
3462 static __init void intel_arch_events_quirk(void)
3463 {
3464 int bit;
3465
3466 /* disable event that reported as not presend by cpuid */
3467 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3468 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3469 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3470 intel_arch_events_map[bit].name);
3471 }
3472 }
3473
3474 static __init void intel_nehalem_quirk(void)
3475 {
3476 union cpuid10_ebx ebx;
3477
3478 ebx.full = x86_pmu.events_maskl;
3479 if (ebx.split.no_branch_misses_retired) {
3480 /*
3481 * Erratum AAJ80 detected, we work it around by using
3482 * the BR_MISP_EXEC.ANY event. This will over-count
3483 * branch-misses, but it's still much better than the
3484 * architectural event which is often completely bogus:
3485 */
3486 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3487 ebx.split.no_branch_misses_retired = 0;
3488 x86_pmu.events_maskl = ebx.full;
3489 pr_info("CPU erratum AAJ80 worked around\n");
3490 }
3491 }
3492
3493 /*
3494 * enable software workaround for errata:
3495 * SNB: BJ122
3496 * IVB: BV98
3497 * HSW: HSD29
3498 *
3499 * Only needed when HT is enabled. However detecting
3500 * if HT is enabled is difficult (model specific). So instead,
3501 * we enable the workaround in the early boot, and verify if
3502 * it is needed in a later initcall phase once we have valid
3503 * topology information to check if HT is actually enabled
3504 */
3505 static __init void intel_ht_bug(void)
3506 {
3507 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3508
3509 x86_pmu.start_scheduling = intel_start_scheduling;
3510 x86_pmu.commit_scheduling = intel_commit_scheduling;
3511 x86_pmu.stop_scheduling = intel_stop_scheduling;
3512 }
3513
3514 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3515 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
3516
3517 /* Haswell special events */
3518 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3519 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3520 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3521 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3522 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3523 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3524 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3525 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3526 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3527 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3528 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3529 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
3530
3531 static struct attribute *hsw_events_attrs[] = {
3532 EVENT_PTR(tx_start),
3533 EVENT_PTR(tx_commit),
3534 EVENT_PTR(tx_abort),
3535 EVENT_PTR(tx_capacity),
3536 EVENT_PTR(tx_conflict),
3537 EVENT_PTR(el_start),
3538 EVENT_PTR(el_commit),
3539 EVENT_PTR(el_abort),
3540 EVENT_PTR(el_capacity),
3541 EVENT_PTR(el_conflict),
3542 EVENT_PTR(cycles_t),
3543 EVENT_PTR(cycles_ct),
3544 EVENT_PTR(mem_ld_hsw),
3545 EVENT_PTR(mem_st_hsw),
3546 EVENT_PTR(td_slots_issued),
3547 EVENT_PTR(td_slots_retired),
3548 EVENT_PTR(td_fetch_bubbles),
3549 EVENT_PTR(td_total_slots),
3550 EVENT_PTR(td_total_slots_scale),
3551 EVENT_PTR(td_recovery_bubbles),
3552 EVENT_PTR(td_recovery_bubbles_scale),
3553 NULL
3554 };
3555
3556 __init int intel_pmu_init(void)
3557 {
3558 union cpuid10_edx edx;
3559 union cpuid10_eax eax;
3560 union cpuid10_ebx ebx;
3561 struct event_constraint *c;
3562 unsigned int unused;
3563 struct extra_reg *er;
3564 int version, i;
3565
3566 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
3567 switch (boot_cpu_data.x86) {
3568 case 0x6:
3569 return p6_pmu_init();
3570 case 0xb:
3571 return knc_pmu_init();
3572 case 0xf:
3573 return p4_pmu_init();
3574 }
3575 return -ENODEV;
3576 }
3577
3578 /*
3579 * Check whether the Architectural PerfMon supports
3580 * Branch Misses Retired hw_event or not.
3581 */
3582 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3583 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
3584 return -ENODEV;
3585
3586 version = eax.split.version_id;
3587 if (version < 2)
3588 x86_pmu = core_pmu;
3589 else
3590 x86_pmu = intel_pmu;
3591
3592 x86_pmu.version = version;
3593 x86_pmu.num_counters = eax.split.num_counters;
3594 x86_pmu.cntval_bits = eax.split.bit_width;
3595 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
3596
3597 x86_pmu.events_maskl = ebx.full;
3598 x86_pmu.events_mask_len = eax.split.mask_length;
3599
3600 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3601
3602 /*
3603 * Quirk: v2 perfmon does not report fixed-purpose events, so
3604 * assume at least 3 events:
3605 */
3606 if (version > 1)
3607 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
3608
3609 if (boot_cpu_has(X86_FEATURE_PDCM)) {
3610 u64 capabilities;
3611
3612 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3613 x86_pmu.intel_cap.capabilities = capabilities;
3614 }
3615
3616 intel_ds_init();
3617
3618 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3619
3620 /*
3621 * Install the hw-cache-events table:
3622 */
3623 switch (boot_cpu_data.x86_model) {
3624 case INTEL_FAM6_CORE_YONAH:
3625 pr_cont("Core events, ");
3626 break;
3627
3628 case INTEL_FAM6_CORE2_MEROM:
3629 x86_add_quirk(intel_clovertown_quirk);
3630 case INTEL_FAM6_CORE2_MEROM_L:
3631 case INTEL_FAM6_CORE2_PENRYN:
3632 case INTEL_FAM6_CORE2_DUNNINGTON:
3633 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3634 sizeof(hw_cache_event_ids));
3635
3636 intel_pmu_lbr_init_core();
3637
3638 x86_pmu.event_constraints = intel_core2_event_constraints;
3639 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3640 pr_cont("Core2 events, ");
3641 break;
3642
3643 case INTEL_FAM6_NEHALEM:
3644 case INTEL_FAM6_NEHALEM_EP:
3645 case INTEL_FAM6_NEHALEM_EX:
3646 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3647 sizeof(hw_cache_event_ids));
3648 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3649 sizeof(hw_cache_extra_regs));
3650
3651 intel_pmu_lbr_init_nhm();
3652
3653 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3654 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3655 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3656 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3657
3658 x86_pmu.cpu_events = nhm_events_attrs;
3659
3660 /* UOPS_ISSUED.STALLED_CYCLES */
3661 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3662 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3663 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3664 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3665 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3666
3667 intel_pmu_pebs_data_source_nhm();
3668 x86_add_quirk(intel_nehalem_quirk);
3669
3670 pr_cont("Nehalem events, ");
3671 break;
3672
3673 case INTEL_FAM6_ATOM_PINEVIEW:
3674 case INTEL_FAM6_ATOM_LINCROFT:
3675 case INTEL_FAM6_ATOM_PENWELL:
3676 case INTEL_FAM6_ATOM_CLOVERVIEW:
3677 case INTEL_FAM6_ATOM_CEDARVIEW:
3678 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3679 sizeof(hw_cache_event_ids));
3680
3681 intel_pmu_lbr_init_atom();
3682
3683 x86_pmu.event_constraints = intel_gen_event_constraints;
3684 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3685 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
3686 pr_cont("Atom events, ");
3687 break;
3688
3689 case INTEL_FAM6_ATOM_SILVERMONT1:
3690 case INTEL_FAM6_ATOM_SILVERMONT2:
3691 case INTEL_FAM6_ATOM_AIRMONT:
3692 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3693 sizeof(hw_cache_event_ids));
3694 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3695 sizeof(hw_cache_extra_regs));
3696
3697 intel_pmu_lbr_init_slm();
3698
3699 x86_pmu.event_constraints = intel_slm_event_constraints;
3700 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3701 x86_pmu.extra_regs = intel_slm_extra_regs;
3702 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3703 x86_pmu.cpu_events = slm_events_attrs;
3704 pr_cont("Silvermont events, ");
3705 break;
3706
3707 case INTEL_FAM6_ATOM_GOLDMONT:
3708 case INTEL_FAM6_ATOM_DENVERTON:
3709 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
3710 sizeof(hw_cache_event_ids));
3711 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
3712 sizeof(hw_cache_extra_regs));
3713
3714 intel_pmu_lbr_init_skl();
3715
3716 x86_pmu.event_constraints = intel_slm_event_constraints;
3717 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
3718 x86_pmu.extra_regs = intel_glm_extra_regs;
3719 /*
3720 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
3721 * for precise cycles.
3722 * :pp is identical to :ppp
3723 */
3724 x86_pmu.pebs_aliases = NULL;
3725 x86_pmu.pebs_prec_dist = true;
3726 x86_pmu.lbr_pt_coexist = true;
3727 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3728 pr_cont("Goldmont events, ");
3729 break;
3730
3731 case INTEL_FAM6_WESTMERE:
3732 case INTEL_FAM6_WESTMERE_EP:
3733 case INTEL_FAM6_WESTMERE_EX:
3734 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3735 sizeof(hw_cache_event_ids));
3736 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3737 sizeof(hw_cache_extra_regs));
3738
3739 intel_pmu_lbr_init_nhm();
3740
3741 x86_pmu.event_constraints = intel_westmere_event_constraints;
3742 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3743 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3744 x86_pmu.extra_regs = intel_westmere_extra_regs;
3745 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3746
3747 x86_pmu.cpu_events = nhm_events_attrs;
3748
3749 /* UOPS_ISSUED.STALLED_CYCLES */
3750 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3751 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3752 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3753 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3754 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3755
3756 intel_pmu_pebs_data_source_nhm();
3757 pr_cont("Westmere events, ");
3758 break;
3759
3760 case INTEL_FAM6_SANDYBRIDGE:
3761 case INTEL_FAM6_SANDYBRIDGE_X:
3762 x86_add_quirk(intel_sandybridge_quirk);
3763 x86_add_quirk(intel_ht_bug);
3764 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3765 sizeof(hw_cache_event_ids));
3766 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3767 sizeof(hw_cache_extra_regs));
3768
3769 intel_pmu_lbr_init_snb();
3770
3771 x86_pmu.event_constraints = intel_snb_event_constraints;
3772 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3773 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3774 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
3775 x86_pmu.extra_regs = intel_snbep_extra_regs;
3776 else
3777 x86_pmu.extra_regs = intel_snb_extra_regs;
3778
3779
3780 /* all extra regs are per-cpu when HT is on */
3781 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3782 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3783
3784 x86_pmu.cpu_events = snb_events_attrs;
3785
3786 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3787 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3788 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3789 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3790 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3791 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3792
3793 pr_cont("SandyBridge events, ");
3794 break;
3795
3796 case INTEL_FAM6_IVYBRIDGE:
3797 case INTEL_FAM6_IVYBRIDGE_X:
3798 x86_add_quirk(intel_ht_bug);
3799 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3800 sizeof(hw_cache_event_ids));
3801 /* dTLB-load-misses on IVB is different than SNB */
3802 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3803
3804 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3805 sizeof(hw_cache_extra_regs));
3806
3807 intel_pmu_lbr_init_snb();
3808
3809 x86_pmu.event_constraints = intel_ivb_event_constraints;
3810 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3811 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3812 x86_pmu.pebs_prec_dist = true;
3813 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
3814 x86_pmu.extra_regs = intel_snbep_extra_regs;
3815 else
3816 x86_pmu.extra_regs = intel_snb_extra_regs;
3817 /* all extra regs are per-cpu when HT is on */
3818 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3819 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3820
3821 x86_pmu.cpu_events = snb_events_attrs;
3822
3823 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3824 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3825 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3826
3827 pr_cont("IvyBridge events, ");
3828 break;
3829
3830
3831 case INTEL_FAM6_HASWELL_CORE:
3832 case INTEL_FAM6_HASWELL_X:
3833 case INTEL_FAM6_HASWELL_ULT:
3834 case INTEL_FAM6_HASWELL_GT3E:
3835 x86_add_quirk(intel_ht_bug);
3836 x86_pmu.late_ack = true;
3837 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3838 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3839
3840 intel_pmu_lbr_init_hsw();
3841
3842 x86_pmu.event_constraints = intel_hsw_event_constraints;
3843 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3844 x86_pmu.extra_regs = intel_snbep_extra_regs;
3845 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3846 x86_pmu.pebs_prec_dist = true;
3847 /* all extra regs are per-cpu when HT is on */
3848 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3849 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3850
3851 x86_pmu.hw_config = hsw_hw_config;
3852 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3853 x86_pmu.cpu_events = hsw_events_attrs;
3854 x86_pmu.lbr_double_abort = true;
3855 pr_cont("Haswell events, ");
3856 break;
3857
3858 case INTEL_FAM6_BROADWELL_CORE:
3859 case INTEL_FAM6_BROADWELL_XEON_D:
3860 case INTEL_FAM6_BROADWELL_GT3E:
3861 case INTEL_FAM6_BROADWELL_X:
3862 x86_pmu.late_ack = true;
3863 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3864 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3865
3866 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3867 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3868 BDW_L3_MISS|HSW_SNOOP_DRAM;
3869 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3870 HSW_SNOOP_DRAM;
3871 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3872 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3873 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3874 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3875
3876 intel_pmu_lbr_init_hsw();
3877
3878 x86_pmu.event_constraints = intel_bdw_event_constraints;
3879 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
3880 x86_pmu.extra_regs = intel_snbep_extra_regs;
3881 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3882 x86_pmu.pebs_prec_dist = true;
3883 /* all extra regs are per-cpu when HT is on */
3884 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3885 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3886
3887 x86_pmu.hw_config = hsw_hw_config;
3888 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3889 x86_pmu.cpu_events = hsw_events_attrs;
3890 x86_pmu.limit_period = bdw_limit_period;
3891 pr_cont("Broadwell events, ");
3892 break;
3893
3894 case INTEL_FAM6_XEON_PHI_KNL:
3895 memcpy(hw_cache_event_ids,
3896 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3897 memcpy(hw_cache_extra_regs,
3898 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3899 intel_pmu_lbr_init_knl();
3900
3901 x86_pmu.event_constraints = intel_slm_event_constraints;
3902 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3903 x86_pmu.extra_regs = intel_knl_extra_regs;
3904
3905 /* all extra regs are per-cpu when HT is on */
3906 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3907 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3908
3909 pr_cont("Knights Landing events, ");
3910 break;
3911
3912 case INTEL_FAM6_SKYLAKE_MOBILE:
3913 case INTEL_FAM6_SKYLAKE_DESKTOP:
3914 case INTEL_FAM6_SKYLAKE_X:
3915 case INTEL_FAM6_KABYLAKE_MOBILE:
3916 case INTEL_FAM6_KABYLAKE_DESKTOP:
3917 x86_pmu.late_ack = true;
3918 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3919 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3920 intel_pmu_lbr_init_skl();
3921
3922 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
3923 event_attr_td_recovery_bubbles.event_str_noht =
3924 "event=0xd,umask=0x1,cmask=1";
3925 event_attr_td_recovery_bubbles.event_str_ht =
3926 "event=0xd,umask=0x1,cmask=1,any=1";
3927
3928 x86_pmu.event_constraints = intel_skl_event_constraints;
3929 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3930 x86_pmu.extra_regs = intel_skl_extra_regs;
3931 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3932 x86_pmu.pebs_prec_dist = true;
3933 /* all extra regs are per-cpu when HT is on */
3934 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3935 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3936
3937 x86_pmu.hw_config = hsw_hw_config;
3938 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3939 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3940 skl_format_attr);
3941 WARN_ON(!x86_pmu.format_attrs);
3942 x86_pmu.cpu_events = hsw_events_attrs;
3943 pr_cont("Skylake events, ");
3944 break;
3945
3946 default:
3947 switch (x86_pmu.version) {
3948 case 1:
3949 x86_pmu.event_constraints = intel_v1_event_constraints;
3950 pr_cont("generic architected perfmon v1, ");
3951 break;
3952 default:
3953 /*
3954 * default constraints for v2 and up
3955 */
3956 x86_pmu.event_constraints = intel_gen_event_constraints;
3957 pr_cont("generic architected perfmon, ");
3958 break;
3959 }
3960 }
3961
3962 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3963 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3964 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3965 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3966 }
3967 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3968
3969 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3970 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3971 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3972 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3973 }
3974
3975 x86_pmu.intel_ctrl |=
3976 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3977
3978 if (x86_pmu.event_constraints) {
3979 /*
3980 * event on fixed counter2 (REF_CYCLES) only works on this
3981 * counter, so do not extend mask to generic counters
3982 */
3983 for_each_event_constraint(c, x86_pmu.event_constraints) {
3984 if (c->cmask == FIXED_EVENT_FLAGS
3985 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3986 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3987 }
3988 c->idxmsk64 &=
3989 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3990 c->weight = hweight64(c->idxmsk64);
3991 }
3992 }
3993
3994 /*
3995 * Access LBR MSR may cause #GP under certain circumstances.
3996 * E.g. KVM doesn't support LBR MSR
3997 * Check all LBT MSR here.
3998 * Disable LBR access if any LBR MSRs can not be accessed.
3999 */
4000 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
4001 x86_pmu.lbr_nr = 0;
4002 for (i = 0; i < x86_pmu.lbr_nr; i++) {
4003 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
4004 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
4005 x86_pmu.lbr_nr = 0;
4006 }
4007
4008 if (x86_pmu.lbr_nr)
4009 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
4010 /*
4011 * Access extra MSR may cause #GP under certain circumstances.
4012 * E.g. KVM doesn't support offcore event
4013 * Check all extra_regs here.
4014 */
4015 if (x86_pmu.extra_regs) {
4016 for (er = x86_pmu.extra_regs; er->msr; er++) {
4017 er->extra_msr_access = check_msr(er->msr, 0x11UL);
4018 /* Disable LBR select mapping */
4019 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
4020 x86_pmu.lbr_sel_map = NULL;
4021 }
4022 }
4023
4024 /* Support full width counters using alternative MSR range */
4025 if (x86_pmu.intel_cap.full_width_write) {
4026 x86_pmu.max_period = x86_pmu.cntval_mask;
4027 x86_pmu.perfctr = MSR_IA32_PMC0;
4028 pr_cont("full-width counters, ");
4029 }
4030
4031 return 0;
4032 }
4033
4034 /*
4035 * HT bug: phase 2 init
4036 * Called once we have valid topology information to check
4037 * whether or not HT is enabled
4038 * If HT is off, then we disable the workaround
4039 */
4040 static __init int fixup_ht_bug(void)
4041 {
4042 int c;
4043 /*
4044 * problem not present on this CPU model, nothing to do
4045 */
4046 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
4047 return 0;
4048
4049 if (topology_max_smt_threads() > 1) {
4050 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4051 return 0;
4052 }
4053
4054 if (lockup_detector_suspend() != 0) {
4055 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
4056 return 0;
4057 }
4058
4059 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
4060
4061 x86_pmu.start_scheduling = NULL;
4062 x86_pmu.commit_scheduling = NULL;
4063 x86_pmu.stop_scheduling = NULL;
4064
4065 lockup_detector_resume();
4066
4067 get_online_cpus();
4068
4069 for_each_online_cpu(c) {
4070 free_excl_cntrs(c);
4071 }
4072
4073 put_online_cpus();
4074 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4075 return 0;
4076 }
4077 subsys_initcall(fixup_ht_bug)
Linux kernel - Deliverables
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