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regmap: irq: Add support to call client specific pre/post interrupt service
[deliverable/linux.git] / arch / x86 / events / intel / uncore_snbep.c
1 /* SandyBridge-EP/IvyTown uncore support */
2 #include "uncore.h"
3
4 /* SNB-EP Box level control */
5 #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
6 #define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1)
7 #define SNBEP_PMON_BOX_CTL_FRZ (1 << 8)
8 #define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16)
9 #define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
10 SNBEP_PMON_BOX_CTL_RST_CTRS | \
11 SNBEP_PMON_BOX_CTL_FRZ_EN)
12 /* SNB-EP event control */
13 #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
14 #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
15 #define SNBEP_PMON_CTL_RST (1 << 17)
16 #define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
17 #define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21)
18 #define SNBEP_PMON_CTL_EN (1 << 22)
19 #define SNBEP_PMON_CTL_INVERT (1 << 23)
20 #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
21 #define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
22 SNBEP_PMON_CTL_UMASK_MASK | \
23 SNBEP_PMON_CTL_EDGE_DET | \
24 SNBEP_PMON_CTL_INVERT | \
25 SNBEP_PMON_CTL_TRESH_MASK)
26
27 /* SNB-EP Ubox event control */
28 #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
29 #define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \
30 (SNBEP_PMON_CTL_EV_SEL_MASK | \
31 SNBEP_PMON_CTL_UMASK_MASK | \
32 SNBEP_PMON_CTL_EDGE_DET | \
33 SNBEP_PMON_CTL_INVERT | \
34 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
35
36 #define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19)
37 #define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
38 SNBEP_CBO_PMON_CTL_TID_EN)
39
40 /* SNB-EP PCU event control */
41 #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
42 #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
43 #define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30)
44 #define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31)
45 #define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
46 (SNBEP_PMON_CTL_EV_SEL_MASK | \
47 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
48 SNBEP_PMON_CTL_EDGE_DET | \
49 SNBEP_PMON_CTL_INVERT | \
50 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
51 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
52 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
53
54 #define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
55 (SNBEP_PMON_RAW_EVENT_MASK | \
56 SNBEP_PMON_CTL_EV_SEL_EXT)
57
58 /* SNB-EP pci control register */
59 #define SNBEP_PCI_PMON_BOX_CTL 0xf4
60 #define SNBEP_PCI_PMON_CTL0 0xd8
61 /* SNB-EP pci counter register */
62 #define SNBEP_PCI_PMON_CTR0 0xa0
63
64 /* SNB-EP home agent register */
65 #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
66 #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
67 #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
68 /* SNB-EP memory controller register */
69 #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
70 #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
71 /* SNB-EP QPI register */
72 #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
73 #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
74 #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
75 #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
76
77 /* SNB-EP Ubox register */
78 #define SNBEP_U_MSR_PMON_CTR0 0xc16
79 #define SNBEP_U_MSR_PMON_CTL0 0xc10
80
81 #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
82 #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
83
84 /* SNB-EP Cbo register */
85 #define SNBEP_C0_MSR_PMON_CTR0 0xd16
86 #define SNBEP_C0_MSR_PMON_CTL0 0xd10
87 #define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
88 #define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
89 #define SNBEP_CBO_MSR_OFFSET 0x20
90
91 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f
92 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00
93 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000
94 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000
95
96 #define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \
97 .event = (e), \
98 .msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \
99 .config_mask = (m), \
100 .idx = (i) \
101 }
102
103 /* SNB-EP PCU register */
104 #define SNBEP_PCU_MSR_PMON_CTR0 0xc36
105 #define SNBEP_PCU_MSR_PMON_CTL0 0xc30
106 #define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
107 #define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
108 #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff
109 #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
110 #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
111
112 /* IVBEP event control */
113 #define IVBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
114 SNBEP_PMON_BOX_CTL_RST_CTRS)
115 #define IVBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
116 SNBEP_PMON_CTL_UMASK_MASK | \
117 SNBEP_PMON_CTL_EDGE_DET | \
118 SNBEP_PMON_CTL_TRESH_MASK)
119 /* IVBEP Ubox */
120 #define IVBEP_U_MSR_PMON_GLOBAL_CTL 0xc00
121 #define IVBEP_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
122 #define IVBEP_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29)
123
124 #define IVBEP_U_MSR_PMON_RAW_EVENT_MASK \
125 (SNBEP_PMON_CTL_EV_SEL_MASK | \
126 SNBEP_PMON_CTL_UMASK_MASK | \
127 SNBEP_PMON_CTL_EDGE_DET | \
128 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
129 /* IVBEP Cbo */
130 #define IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK (IVBEP_PMON_RAW_EVENT_MASK | \
131 SNBEP_CBO_PMON_CTL_TID_EN)
132
133 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0)
134 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5)
135 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17)
136 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
137 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
138 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
139 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
140 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
141
142 /* IVBEP home agent */
143 #define IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16)
144 #define IVBEP_HA_PCI_PMON_RAW_EVENT_MASK \
145 (IVBEP_PMON_RAW_EVENT_MASK | \
146 IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST)
147 /* IVBEP PCU */
148 #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
149 (SNBEP_PMON_CTL_EV_SEL_MASK | \
150 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
151 SNBEP_PMON_CTL_EDGE_DET | \
152 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
153 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
154 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
155 /* IVBEP QPI */
156 #define IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
157 (IVBEP_PMON_RAW_EVENT_MASK | \
158 SNBEP_PMON_CTL_EV_SEL_EXT)
159
160 #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
161 ((1ULL << (n)) - 1)))
162
163 /* Haswell-EP Ubox */
164 #define HSWEP_U_MSR_PMON_CTR0 0x709
165 #define HSWEP_U_MSR_PMON_CTL0 0x705
166 #define HSWEP_U_MSR_PMON_FILTER 0x707
167
168 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703
169 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704
170
171 #define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0)
172 #define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1)
173 #define HSWEP_U_MSR_PMON_BOX_FILTER_MASK \
174 (HSWEP_U_MSR_PMON_BOX_FILTER_TID | \
175 HSWEP_U_MSR_PMON_BOX_FILTER_CID)
176
177 /* Haswell-EP CBo */
178 #define HSWEP_C0_MSR_PMON_CTR0 0xe08
179 #define HSWEP_C0_MSR_PMON_CTL0 0xe01
180 #define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00
181 #define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05
182 #define HSWEP_CBO_MSR_OFFSET 0x10
183
184
185 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0)
186 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6)
187 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17)
188 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
189 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
190 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
191 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
192 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
193
194
195 /* Haswell-EP Sbox */
196 #define HSWEP_S0_MSR_PMON_CTR0 0x726
197 #define HSWEP_S0_MSR_PMON_CTL0 0x721
198 #define HSWEP_S0_MSR_PMON_BOX_CTL 0x720
199 #define HSWEP_SBOX_MSR_OFFSET 0xa
200 #define HSWEP_S_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
201 SNBEP_CBO_PMON_CTL_TID_EN)
202
203 /* Haswell-EP PCU */
204 #define HSWEP_PCU_MSR_PMON_CTR0 0x717
205 #define HSWEP_PCU_MSR_PMON_CTL0 0x711
206 #define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710
207 #define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715
208
209 /* KNL Ubox */
210 #define KNL_U_MSR_PMON_RAW_EVENT_MASK \
211 (SNBEP_U_MSR_PMON_RAW_EVENT_MASK | \
212 SNBEP_CBO_PMON_CTL_TID_EN)
213 /* KNL CHA */
214 #define KNL_CHA_MSR_OFFSET 0xc
215 #define KNL_CHA_MSR_PMON_CTL_QOR (1 << 16)
216 #define KNL_CHA_MSR_PMON_RAW_EVENT_MASK \
217 (SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK | \
218 KNL_CHA_MSR_PMON_CTL_QOR)
219 #define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff
220 #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE (7 << 18)
221 #define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32)
222 #define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE (0x1ULL << 32)
223 #define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE (0x1ULL << 33)
224 #define KNL_CHA_MSR_PMON_BOX_FILTER_NNC (0x1ULL << 37)
225
226 /* KNL EDC/MC UCLK */
227 #define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400
228 #define KNL_UCLK_MSR_PMON_CTL0 0x420
229 #define KNL_UCLK_MSR_PMON_BOX_CTL 0x430
230 #define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c
231 #define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454
232 #define KNL_PMON_FIXED_CTL_EN 0x1
233
234 /* KNL EDC */
235 #define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00
236 #define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20
237 #define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30
238 #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c
239 #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44
240
241 /* KNL MC */
242 #define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00
243 #define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20
244 #define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30
245 #define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c
246 #define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44
247
248 /* KNL IRP */
249 #define KNL_IRP_PCI_PMON_BOX_CTL 0xf0
250 #define KNL_IRP_PCI_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
251 KNL_CHA_MSR_PMON_CTL_QOR)
252 /* KNL PCU */
253 #define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f
254 #define KNL_PCU_PMON_CTL_USE_OCC_CTR (1 << 7)
255 #define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000
256 #define KNL_PCU_MSR_PMON_RAW_EVENT_MASK \
257 (KNL_PCU_PMON_CTL_EV_SEL_MASK | \
258 KNL_PCU_PMON_CTL_USE_OCC_CTR | \
259 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
260 SNBEP_PMON_CTL_EDGE_DET | \
261 SNBEP_CBO_PMON_CTL_TID_EN | \
262 SNBEP_PMON_CTL_INVERT | \
263 KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \
264 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
265 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
266
267 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
268 DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
269 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
270 DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7");
271 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
272 DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");
273 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
274 DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
275 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
276 DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
277 DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29");
278 DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
279 DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
280 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
281 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
282 DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31");
283 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
284 DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0");
285 DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5");
286 DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8");
287 DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5");
288 DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
289 DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8");
290 DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12");
291 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
292 DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
293 DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
294 DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
295 DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23");
296 DEFINE_UNCORE_FORMAT_ATTR(filter_state4, filter_state, "config1:18-20");
297 DEFINE_UNCORE_FORMAT_ATTR(filter_local, filter_local, "config1:33");
298 DEFINE_UNCORE_FORMAT_ATTR(filter_all_op, filter_all_op, "config1:35");
299 DEFINE_UNCORE_FORMAT_ATTR(filter_nnm, filter_nnm, "config1:37");
300 DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
301 DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
302 DEFINE_UNCORE_FORMAT_ATTR(filter_opc3, filter_opc, "config1:41-60");
303 DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62");
304 DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61");
305 DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63");
306 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
307 DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
308 DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
309 DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
310 DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51");
311 DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35");
312 DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31");
313 DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17");
314 DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12");
315 DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8");
316 DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4");
317 DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31");
318 DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63");
319 DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51");
320 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35");
321 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31");
322 DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17");
323 DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12");
324 DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8");
325 DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4");
326 DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");
327 DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63");
328
329 static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
330 {
331 struct pci_dev *pdev = box->pci_dev;
332 int box_ctl = uncore_pci_box_ctl(box);
333 u32 config = 0;
334
335 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
336 config |= SNBEP_PMON_BOX_CTL_FRZ;
337 pci_write_config_dword(pdev, box_ctl, config);
338 }
339 }
340
341 static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
342 {
343 struct pci_dev *pdev = box->pci_dev;
344 int box_ctl = uncore_pci_box_ctl(box);
345 u32 config = 0;
346
347 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
348 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
349 pci_write_config_dword(pdev, box_ctl, config);
350 }
351 }
352
353 static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
354 {
355 struct pci_dev *pdev = box->pci_dev;
356 struct hw_perf_event *hwc = &event->hw;
357
358 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
359 }
360
361 static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
362 {
363 struct pci_dev *pdev = box->pci_dev;
364 struct hw_perf_event *hwc = &event->hw;
365
366 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
367 }
368
369 static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
370 {
371 struct pci_dev *pdev = box->pci_dev;
372 struct hw_perf_event *hwc = &event->hw;
373 u64 count = 0;
374
375 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
376 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
377
378 return count;
379 }
380
381 static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
382 {
383 struct pci_dev *pdev = box->pci_dev;
384 int box_ctl = uncore_pci_box_ctl(box);
385
386 pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT);
387 }
388
389 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
390 {
391 u64 config;
392 unsigned msr;
393
394 msr = uncore_msr_box_ctl(box);
395 if (msr) {
396 rdmsrl(msr, config);
397 config |= SNBEP_PMON_BOX_CTL_FRZ;
398 wrmsrl(msr, config);
399 }
400 }
401
402 static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
403 {
404 u64 config;
405 unsigned msr;
406
407 msr = uncore_msr_box_ctl(box);
408 if (msr) {
409 rdmsrl(msr, config);
410 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
411 wrmsrl(msr, config);
412 }
413 }
414
415 static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
416 {
417 struct hw_perf_event *hwc = &event->hw;
418 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
419
420 if (reg1->idx != EXTRA_REG_NONE)
421 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
422
423 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
424 }
425
426 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
427 struct perf_event *event)
428 {
429 struct hw_perf_event *hwc = &event->hw;
430
431 wrmsrl(hwc->config_base, hwc->config);
432 }
433
434 static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
435 {
436 unsigned msr = uncore_msr_box_ctl(box);
437
438 if (msr)
439 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
440 }
441
442 static struct attribute *snbep_uncore_formats_attr[] = {
443 &format_attr_event.attr,
444 &format_attr_umask.attr,
445 &format_attr_edge.attr,
446 &format_attr_inv.attr,
447 &format_attr_thresh8.attr,
448 NULL,
449 };
450
451 static struct attribute *snbep_uncore_ubox_formats_attr[] = {
452 &format_attr_event.attr,
453 &format_attr_umask.attr,
454 &format_attr_edge.attr,
455 &format_attr_inv.attr,
456 &format_attr_thresh5.attr,
457 NULL,
458 };
459
460 static struct attribute *snbep_uncore_cbox_formats_attr[] = {
461 &format_attr_event.attr,
462 &format_attr_umask.attr,
463 &format_attr_edge.attr,
464 &format_attr_tid_en.attr,
465 &format_attr_inv.attr,
466 &format_attr_thresh8.attr,
467 &format_attr_filter_tid.attr,
468 &format_attr_filter_nid.attr,
469 &format_attr_filter_state.attr,
470 &format_attr_filter_opc.attr,
471 NULL,
472 };
473
474 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
475 &format_attr_event.attr,
476 &format_attr_occ_sel.attr,
477 &format_attr_edge.attr,
478 &format_attr_inv.attr,
479 &format_attr_thresh5.attr,
480 &format_attr_occ_invert.attr,
481 &format_attr_occ_edge.attr,
482 &format_attr_filter_band0.attr,
483 &format_attr_filter_band1.attr,
484 &format_attr_filter_band2.attr,
485 &format_attr_filter_band3.attr,
486 NULL,
487 };
488
489 static struct attribute *snbep_uncore_qpi_formats_attr[] = {
490 &format_attr_event_ext.attr,
491 &format_attr_umask.attr,
492 &format_attr_edge.attr,
493 &format_attr_inv.attr,
494 &format_attr_thresh8.attr,
495 &format_attr_match_rds.attr,
496 &format_attr_match_rnid30.attr,
497 &format_attr_match_rnid4.attr,
498 &format_attr_match_dnid.attr,
499 &format_attr_match_mc.attr,
500 &format_attr_match_opc.attr,
501 &format_attr_match_vnw.attr,
502 &format_attr_match0.attr,
503 &format_attr_match1.attr,
504 &format_attr_mask_rds.attr,
505 &format_attr_mask_rnid30.attr,
506 &format_attr_mask_rnid4.attr,
507 &format_attr_mask_dnid.attr,
508 &format_attr_mask_mc.attr,
509 &format_attr_mask_opc.attr,
510 &format_attr_mask_vnw.attr,
511 &format_attr_mask0.attr,
512 &format_attr_mask1.attr,
513 NULL,
514 };
515
516 static struct uncore_event_desc snbep_uncore_imc_events[] = {
517 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
518 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
519 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
520 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
521 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
522 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
523 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
524 { /* end: all zeroes */ },
525 };
526
527 static struct uncore_event_desc snbep_uncore_qpi_events[] = {
528 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"),
529 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
530 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"),
531 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"),
532 { /* end: all zeroes */ },
533 };
534
535 static struct attribute_group snbep_uncore_format_group = {
536 .name = "format",
537 .attrs = snbep_uncore_formats_attr,
538 };
539
540 static struct attribute_group snbep_uncore_ubox_format_group = {
541 .name = "format",
542 .attrs = snbep_uncore_ubox_formats_attr,
543 };
544
545 static struct attribute_group snbep_uncore_cbox_format_group = {
546 .name = "format",
547 .attrs = snbep_uncore_cbox_formats_attr,
548 };
549
550 static struct attribute_group snbep_uncore_pcu_format_group = {
551 .name = "format",
552 .attrs = snbep_uncore_pcu_formats_attr,
553 };
554
555 static struct attribute_group snbep_uncore_qpi_format_group = {
556 .name = "format",
557 .attrs = snbep_uncore_qpi_formats_attr,
558 };
559
560 #define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
561 .disable_box = snbep_uncore_msr_disable_box, \
562 .enable_box = snbep_uncore_msr_enable_box, \
563 .disable_event = snbep_uncore_msr_disable_event, \
564 .enable_event = snbep_uncore_msr_enable_event, \
565 .read_counter = uncore_msr_read_counter
566
567 #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
568 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \
569 .init_box = snbep_uncore_msr_init_box \
570
571 static struct intel_uncore_ops snbep_uncore_msr_ops = {
572 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
573 };
574
575 #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \
576 .init_box = snbep_uncore_pci_init_box, \
577 .disable_box = snbep_uncore_pci_disable_box, \
578 .enable_box = snbep_uncore_pci_enable_box, \
579 .disable_event = snbep_uncore_pci_disable_event, \
580 .read_counter = snbep_uncore_pci_read_counter
581
582 static struct intel_uncore_ops snbep_uncore_pci_ops = {
583 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
584 .enable_event = snbep_uncore_pci_enable_event, \
585 };
586
587 static struct event_constraint snbep_uncore_cbox_constraints[] = {
588 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
589 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
590 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
591 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
592 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
593 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
594 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
595 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
596 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
597 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
598 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
599 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
600 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
601 EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
602 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
603 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
604 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
605 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
606 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
607 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
608 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
609 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
610 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
611 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
612 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
613 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
614 EVENT_CONSTRAINT_END
615 };
616
617 static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
618 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
619 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
620 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
621 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
622 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
623 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
624 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
625 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
626 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
627 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
628 EVENT_CONSTRAINT_END
629 };
630
631 static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
632 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
633 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
634 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
635 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
636 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
637 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
638 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
639 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
640 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
641 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
642 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
643 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
644 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
645 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
646 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
647 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
648 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
649 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
650 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
651 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
652 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
653 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
654 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
655 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
656 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
657 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
658 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
659 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
660 EVENT_CONSTRAINT_END
661 };
662
663 static struct intel_uncore_type snbep_uncore_ubox = {
664 .name = "ubox",
665 .num_counters = 2,
666 .num_boxes = 1,
667 .perf_ctr_bits = 44,
668 .fixed_ctr_bits = 48,
669 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
670 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
671 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
672 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
673 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
674 .ops = &snbep_uncore_msr_ops,
675 .format_group = &snbep_uncore_ubox_format_group,
676 };
677
678 static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
679 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
680 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
681 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
682 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
683 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
684 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
685 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
686 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
687 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
688 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
689 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
690 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa),
691 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa),
692 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
693 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
694 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
695 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
696 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
697 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
698 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa),
699 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa),
700 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
701 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
702 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
703 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
704 EVENT_EXTRA_END
705 };
706
707 static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
708 {
709 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
710 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
711 int i;
712
713 if (uncore_box_is_fake(box))
714 return;
715
716 for (i = 0; i < 5; i++) {
717 if (reg1->alloc & (0x1 << i))
718 atomic_sub(1 << (i * 6), &er->ref);
719 }
720 reg1->alloc = 0;
721 }
722
723 static struct event_constraint *
724 __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event,
725 u64 (*cbox_filter_mask)(int fields))
726 {
727 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
728 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
729 int i, alloc = 0;
730 unsigned long flags;
731 u64 mask;
732
733 if (reg1->idx == EXTRA_REG_NONE)
734 return NULL;
735
736 raw_spin_lock_irqsave(&er->lock, flags);
737 for (i = 0; i < 5; i++) {
738 if (!(reg1->idx & (0x1 << i)))
739 continue;
740 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
741 continue;
742
743 mask = cbox_filter_mask(0x1 << i);
744 if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) ||
745 !((reg1->config ^ er->config) & mask)) {
746 atomic_add(1 << (i * 6), &er->ref);
747 er->config &= ~mask;
748 er->config |= reg1->config & mask;
749 alloc |= (0x1 << i);
750 } else {
751 break;
752 }
753 }
754 raw_spin_unlock_irqrestore(&er->lock, flags);
755 if (i < 5)
756 goto fail;
757
758 if (!uncore_box_is_fake(box))
759 reg1->alloc |= alloc;
760
761 return NULL;
762 fail:
763 for (; i >= 0; i--) {
764 if (alloc & (0x1 << i))
765 atomic_sub(1 << (i * 6), &er->ref);
766 }
767 return &uncore_constraint_empty;
768 }
769
770 static u64 snbep_cbox_filter_mask(int fields)
771 {
772 u64 mask = 0;
773
774 if (fields & 0x1)
775 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID;
776 if (fields & 0x2)
777 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID;
778 if (fields & 0x4)
779 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
780 if (fields & 0x8)
781 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
782
783 return mask;
784 }
785
786 static struct event_constraint *
787 snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
788 {
789 return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask);
790 }
791
792 static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
793 {
794 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
795 struct extra_reg *er;
796 int idx = 0;
797
798 for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) {
799 if (er->event != (event->hw.config & er->config_mask))
800 continue;
801 idx |= er->idx;
802 }
803
804 if (idx) {
805 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
806 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
807 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx);
808 reg1->idx = idx;
809 }
810 return 0;
811 }
812
813 static struct intel_uncore_ops snbep_uncore_cbox_ops = {
814 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
815 .hw_config = snbep_cbox_hw_config,
816 .get_constraint = snbep_cbox_get_constraint,
817 .put_constraint = snbep_cbox_put_constraint,
818 };
819
820 static struct intel_uncore_type snbep_uncore_cbox = {
821 .name = "cbox",
822 .num_counters = 4,
823 .num_boxes = 8,
824 .perf_ctr_bits = 44,
825 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
826 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
827 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
828 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
829 .msr_offset = SNBEP_CBO_MSR_OFFSET,
830 .num_shared_regs = 1,
831 .constraints = snbep_uncore_cbox_constraints,
832 .ops = &snbep_uncore_cbox_ops,
833 .format_group = &snbep_uncore_cbox_format_group,
834 };
835
836 static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify)
837 {
838 struct hw_perf_event *hwc = &event->hw;
839 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
840 u64 config = reg1->config;
841
842 if (new_idx > reg1->idx)
843 config <<= 8 * (new_idx - reg1->idx);
844 else
845 config >>= 8 * (reg1->idx - new_idx);
846
847 if (modify) {
848 hwc->config += new_idx - reg1->idx;
849 reg1->config = config;
850 reg1->idx = new_idx;
851 }
852 return config;
853 }
854
855 static struct event_constraint *
856 snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
857 {
858 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
859 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
860 unsigned long flags;
861 int idx = reg1->idx;
862 u64 mask, config1 = reg1->config;
863 bool ok = false;
864
865 if (reg1->idx == EXTRA_REG_NONE ||
866 (!uncore_box_is_fake(box) && reg1->alloc))
867 return NULL;
868 again:
869 mask = 0xffULL << (idx * 8);
870 raw_spin_lock_irqsave(&er->lock, flags);
871 if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
872 !((config1 ^ er->config) & mask)) {
873 atomic_add(1 << (idx * 8), &er->ref);
874 er->config &= ~mask;
875 er->config |= config1 & mask;
876 ok = true;
877 }
878 raw_spin_unlock_irqrestore(&er->lock, flags);
879
880 if (!ok) {
881 idx = (idx + 1) % 4;
882 if (idx != reg1->idx) {
883 config1 = snbep_pcu_alter_er(event, idx, false);
884 goto again;
885 }
886 return &uncore_constraint_empty;
887 }
888
889 if (!uncore_box_is_fake(box)) {
890 if (idx != reg1->idx)
891 snbep_pcu_alter_er(event, idx, true);
892 reg1->alloc = 1;
893 }
894 return NULL;
895 }
896
897 static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
898 {
899 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
900 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
901
902 if (uncore_box_is_fake(box) || !reg1->alloc)
903 return;
904
905 atomic_sub(1 << (reg1->idx * 8), &er->ref);
906 reg1->alloc = 0;
907 }
908
909 static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
910 {
911 struct hw_perf_event *hwc = &event->hw;
912 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
913 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
914
915 if (ev_sel >= 0xb && ev_sel <= 0xe) {
916 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
917 reg1->idx = ev_sel - 0xb;
918 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8));
919 }
920 return 0;
921 }
922
923 static struct intel_uncore_ops snbep_uncore_pcu_ops = {
924 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
925 .hw_config = snbep_pcu_hw_config,
926 .get_constraint = snbep_pcu_get_constraint,
927 .put_constraint = snbep_pcu_put_constraint,
928 };
929
930 static struct intel_uncore_type snbep_uncore_pcu = {
931 .name = "pcu",
932 .num_counters = 4,
933 .num_boxes = 1,
934 .perf_ctr_bits = 48,
935 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
936 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
937 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
938 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
939 .num_shared_regs = 1,
940 .ops = &snbep_uncore_pcu_ops,
941 .format_group = &snbep_uncore_pcu_format_group,
942 };
943
944 static struct intel_uncore_type *snbep_msr_uncores[] = {
945 &snbep_uncore_ubox,
946 &snbep_uncore_cbox,
947 &snbep_uncore_pcu,
948 NULL,
949 };
950
951 void snbep_uncore_cpu_init(void)
952 {
953 if (snbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
954 snbep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
955 uncore_msr_uncores = snbep_msr_uncores;
956 }
957
958 enum {
959 SNBEP_PCI_QPI_PORT0_FILTER,
960 SNBEP_PCI_QPI_PORT1_FILTER,
961 HSWEP_PCI_PCU_3,
962 };
963
964 static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event)
965 {
966 struct hw_perf_event *hwc = &event->hw;
967 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
968 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
969
970 if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) {
971 reg1->idx = 0;
972 reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0;
973 reg1->config = event->attr.config1;
974 reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0;
975 reg2->config = event->attr.config2;
976 }
977 return 0;
978 }
979
980 static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event)
981 {
982 struct pci_dev *pdev = box->pci_dev;
983 struct hw_perf_event *hwc = &event->hw;
984 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
985 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
986
987 if (reg1->idx != EXTRA_REG_NONE) {
988 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER;
989 int pkg = topology_phys_to_logical_pkg(box->pci_phys_id);
990 struct pci_dev *filter_pdev = uncore_extra_pci_dev[pkg].dev[idx];
991
992 if (filter_pdev) {
993 pci_write_config_dword(filter_pdev, reg1->reg,
994 (u32)reg1->config);
995 pci_write_config_dword(filter_pdev, reg1->reg + 4,
996 (u32)(reg1->config >> 32));
997 pci_write_config_dword(filter_pdev, reg2->reg,
998 (u32)reg2->config);
999 pci_write_config_dword(filter_pdev, reg2->reg + 4,
1000 (u32)(reg2->config >> 32));
1001 }
1002 }
1003
1004 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1005 }
1006
1007 static struct intel_uncore_ops snbep_uncore_qpi_ops = {
1008 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
1009 .enable_event = snbep_qpi_enable_event,
1010 .hw_config = snbep_qpi_hw_config,
1011 .get_constraint = uncore_get_constraint,
1012 .put_constraint = uncore_put_constraint,
1013 };
1014
1015 #define SNBEP_UNCORE_PCI_COMMON_INIT() \
1016 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1017 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1018 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
1019 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1020 .ops = &snbep_uncore_pci_ops, \
1021 .format_group = &snbep_uncore_format_group
1022
1023 static struct intel_uncore_type snbep_uncore_ha = {
1024 .name = "ha",
1025 .num_counters = 4,
1026 .num_boxes = 1,
1027 .perf_ctr_bits = 48,
1028 SNBEP_UNCORE_PCI_COMMON_INIT(),
1029 };
1030
1031 static struct intel_uncore_type snbep_uncore_imc = {
1032 .name = "imc",
1033 .num_counters = 4,
1034 .num_boxes = 4,
1035 .perf_ctr_bits = 48,
1036 .fixed_ctr_bits = 48,
1037 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1038 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1039 .event_descs = snbep_uncore_imc_events,
1040 SNBEP_UNCORE_PCI_COMMON_INIT(),
1041 };
1042
1043 static struct intel_uncore_type snbep_uncore_qpi = {
1044 .name = "qpi",
1045 .num_counters = 4,
1046 .num_boxes = 2,
1047 .perf_ctr_bits = 48,
1048 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1049 .event_ctl = SNBEP_PCI_PMON_CTL0,
1050 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
1051 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1052 .num_shared_regs = 1,
1053 .ops = &snbep_uncore_qpi_ops,
1054 .event_descs = snbep_uncore_qpi_events,
1055 .format_group = &snbep_uncore_qpi_format_group,
1056 };
1057
1058
1059 static struct intel_uncore_type snbep_uncore_r2pcie = {
1060 .name = "r2pcie",
1061 .num_counters = 4,
1062 .num_boxes = 1,
1063 .perf_ctr_bits = 44,
1064 .constraints = snbep_uncore_r2pcie_constraints,
1065 SNBEP_UNCORE_PCI_COMMON_INIT(),
1066 };
1067
1068 static struct intel_uncore_type snbep_uncore_r3qpi = {
1069 .name = "r3qpi",
1070 .num_counters = 3,
1071 .num_boxes = 2,
1072 .perf_ctr_bits = 44,
1073 .constraints = snbep_uncore_r3qpi_constraints,
1074 SNBEP_UNCORE_PCI_COMMON_INIT(),
1075 };
1076
1077 enum {
1078 SNBEP_PCI_UNCORE_HA,
1079 SNBEP_PCI_UNCORE_IMC,
1080 SNBEP_PCI_UNCORE_QPI,
1081 SNBEP_PCI_UNCORE_R2PCIE,
1082 SNBEP_PCI_UNCORE_R3QPI,
1083 };
1084
1085 static struct intel_uncore_type *snbep_pci_uncores[] = {
1086 [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha,
1087 [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc,
1088 [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi,
1089 [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie,
1090 [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi,
1091 NULL,
1092 };
1093
1094 static const struct pci_device_id snbep_uncore_pci_ids[] = {
1095 { /* Home Agent */
1096 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
1097 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0),
1098 },
1099 { /* MC Channel 0 */
1100 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
1101 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0),
1102 },
1103 { /* MC Channel 1 */
1104 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
1105 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1),
1106 },
1107 { /* MC Channel 2 */
1108 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
1109 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2),
1110 },
1111 { /* MC Channel 3 */
1112 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
1113 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3),
1114 },
1115 { /* QPI Port 0 */
1116 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
1117 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0),
1118 },
1119 { /* QPI Port 1 */
1120 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
1121 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1),
1122 },
1123 { /* R2PCIe */
1124 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
1125 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0),
1126 },
1127 { /* R3QPI Link 0 */
1128 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
1129 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0),
1130 },
1131 { /* R3QPI Link 1 */
1132 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
1133 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1),
1134 },
1135 { /* QPI Port 0 filter */
1136 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86),
1137 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1138 SNBEP_PCI_QPI_PORT0_FILTER),
1139 },
1140 { /* QPI Port 0 filter */
1141 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96),
1142 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1143 SNBEP_PCI_QPI_PORT1_FILTER),
1144 },
1145 { /* end: all zeroes */ }
1146 };
1147
1148 static struct pci_driver snbep_uncore_pci_driver = {
1149 .name = "snbep_uncore",
1150 .id_table = snbep_uncore_pci_ids,
1151 };
1152
1153 /*
1154 * build pci bus to socket mapping
1155 */
1156 static int snbep_pci2phy_map_init(int devid)
1157 {
1158 struct pci_dev *ubox_dev = NULL;
1159 int i, bus, nodeid, segment;
1160 struct pci2phy_map *map;
1161 int err = 0;
1162 u32 config = 0;
1163
1164 while (1) {
1165 /* find the UBOX device */
1166 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
1167 if (!ubox_dev)
1168 break;
1169 bus = ubox_dev->bus->number;
1170 /* get the Node ID of the local register */
1171 err = pci_read_config_dword(ubox_dev, 0x40, &config);
1172 if (err)
1173 break;
1174 nodeid = config;
1175 /* get the Node ID mapping */
1176 err = pci_read_config_dword(ubox_dev, 0x54, &config);
1177 if (err)
1178 break;
1179
1180 segment = pci_domain_nr(ubox_dev->bus);
1181 raw_spin_lock(&pci2phy_map_lock);
1182 map = __find_pci2phy_map(segment);
1183 if (!map) {
1184 raw_spin_unlock(&pci2phy_map_lock);
1185 err = -ENOMEM;
1186 break;
1187 }
1188
1189 /*
1190 * every three bits in the Node ID mapping register maps
1191 * to a particular node.
1192 */
1193 for (i = 0; i < 8; i++) {
1194 if (nodeid == ((config >> (3 * i)) & 0x7)) {
1195 map->pbus_to_physid[bus] = i;
1196 break;
1197 }
1198 }
1199 raw_spin_unlock(&pci2phy_map_lock);
1200 }
1201
1202 if (!err) {
1203 /*
1204 * For PCI bus with no UBOX device, find the next bus
1205 * that has UBOX device and use its mapping.
1206 */
1207 raw_spin_lock(&pci2phy_map_lock);
1208 list_for_each_entry(map, &pci2phy_map_head, list) {
1209 i = -1;
1210 for (bus = 255; bus >= 0; bus--) {
1211 if (map->pbus_to_physid[bus] >= 0)
1212 i = map->pbus_to_physid[bus];
1213 else
1214 map->pbus_to_physid[bus] = i;
1215 }
1216 }
1217 raw_spin_unlock(&pci2phy_map_lock);
1218 }
1219
1220 pci_dev_put(ubox_dev);
1221
1222 return err ? pcibios_err_to_errno(err) : 0;
1223 }
1224
1225 int snbep_uncore_pci_init(void)
1226 {
1227 int ret = snbep_pci2phy_map_init(0x3ce0);
1228 if (ret)
1229 return ret;
1230 uncore_pci_uncores = snbep_pci_uncores;
1231 uncore_pci_driver = &snbep_uncore_pci_driver;
1232 return 0;
1233 }
1234 /* end of Sandy Bridge-EP uncore support */
1235
1236 /* IvyTown uncore support */
1237 static void ivbep_uncore_msr_init_box(struct intel_uncore_box *box)
1238 {
1239 unsigned msr = uncore_msr_box_ctl(box);
1240 if (msr)
1241 wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT);
1242 }
1243
1244 static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box)
1245 {
1246 struct pci_dev *pdev = box->pci_dev;
1247
1248 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT);
1249 }
1250
1251 #define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() \
1252 .init_box = ivbep_uncore_msr_init_box, \
1253 .disable_box = snbep_uncore_msr_disable_box, \
1254 .enable_box = snbep_uncore_msr_enable_box, \
1255 .disable_event = snbep_uncore_msr_disable_event, \
1256 .enable_event = snbep_uncore_msr_enable_event, \
1257 .read_counter = uncore_msr_read_counter
1258
1259 static struct intel_uncore_ops ivbep_uncore_msr_ops = {
1260 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1261 };
1262
1263 static struct intel_uncore_ops ivbep_uncore_pci_ops = {
1264 .init_box = ivbep_uncore_pci_init_box,
1265 .disable_box = snbep_uncore_pci_disable_box,
1266 .enable_box = snbep_uncore_pci_enable_box,
1267 .disable_event = snbep_uncore_pci_disable_event,
1268 .enable_event = snbep_uncore_pci_enable_event,
1269 .read_counter = snbep_uncore_pci_read_counter,
1270 };
1271
1272 #define IVBEP_UNCORE_PCI_COMMON_INIT() \
1273 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1274 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1275 .event_mask = IVBEP_PMON_RAW_EVENT_MASK, \
1276 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1277 .ops = &ivbep_uncore_pci_ops, \
1278 .format_group = &ivbep_uncore_format_group
1279
1280 static struct attribute *ivbep_uncore_formats_attr[] = {
1281 &format_attr_event.attr,
1282 &format_attr_umask.attr,
1283 &format_attr_edge.attr,
1284 &format_attr_inv.attr,
1285 &format_attr_thresh8.attr,
1286 NULL,
1287 };
1288
1289 static struct attribute *ivbep_uncore_ubox_formats_attr[] = {
1290 &format_attr_event.attr,
1291 &format_attr_umask.attr,
1292 &format_attr_edge.attr,
1293 &format_attr_inv.attr,
1294 &format_attr_thresh5.attr,
1295 NULL,
1296 };
1297
1298 static struct attribute *ivbep_uncore_cbox_formats_attr[] = {
1299 &format_attr_event.attr,
1300 &format_attr_umask.attr,
1301 &format_attr_edge.attr,
1302 &format_attr_tid_en.attr,
1303 &format_attr_thresh8.attr,
1304 &format_attr_filter_tid.attr,
1305 &format_attr_filter_link.attr,
1306 &format_attr_filter_state2.attr,
1307 &format_attr_filter_nid2.attr,
1308 &format_attr_filter_opc2.attr,
1309 &format_attr_filter_nc.attr,
1310 &format_attr_filter_c6.attr,
1311 &format_attr_filter_isoc.attr,
1312 NULL,
1313 };
1314
1315 static struct attribute *ivbep_uncore_pcu_formats_attr[] = {
1316 &format_attr_event.attr,
1317 &format_attr_occ_sel.attr,
1318 &format_attr_edge.attr,
1319 &format_attr_thresh5.attr,
1320 &format_attr_occ_invert.attr,
1321 &format_attr_occ_edge.attr,
1322 &format_attr_filter_band0.attr,
1323 &format_attr_filter_band1.attr,
1324 &format_attr_filter_band2.attr,
1325 &format_attr_filter_band3.attr,
1326 NULL,
1327 };
1328
1329 static struct attribute *ivbep_uncore_qpi_formats_attr[] = {
1330 &format_attr_event_ext.attr,
1331 &format_attr_umask.attr,
1332 &format_attr_edge.attr,
1333 &format_attr_thresh8.attr,
1334 &format_attr_match_rds.attr,
1335 &format_attr_match_rnid30.attr,
1336 &format_attr_match_rnid4.attr,
1337 &format_attr_match_dnid.attr,
1338 &format_attr_match_mc.attr,
1339 &format_attr_match_opc.attr,
1340 &format_attr_match_vnw.attr,
1341 &format_attr_match0.attr,
1342 &format_attr_match1.attr,
1343 &format_attr_mask_rds.attr,
1344 &format_attr_mask_rnid30.attr,
1345 &format_attr_mask_rnid4.attr,
1346 &format_attr_mask_dnid.attr,
1347 &format_attr_mask_mc.attr,
1348 &format_attr_mask_opc.attr,
1349 &format_attr_mask_vnw.attr,
1350 &format_attr_mask0.attr,
1351 &format_attr_mask1.attr,
1352 NULL,
1353 };
1354
1355 static struct attribute_group ivbep_uncore_format_group = {
1356 .name = "format",
1357 .attrs = ivbep_uncore_formats_attr,
1358 };
1359
1360 static struct attribute_group ivbep_uncore_ubox_format_group = {
1361 .name = "format",
1362 .attrs = ivbep_uncore_ubox_formats_attr,
1363 };
1364
1365 static struct attribute_group ivbep_uncore_cbox_format_group = {
1366 .name = "format",
1367 .attrs = ivbep_uncore_cbox_formats_attr,
1368 };
1369
1370 static struct attribute_group ivbep_uncore_pcu_format_group = {
1371 .name = "format",
1372 .attrs = ivbep_uncore_pcu_formats_attr,
1373 };
1374
1375 static struct attribute_group ivbep_uncore_qpi_format_group = {
1376 .name = "format",
1377 .attrs = ivbep_uncore_qpi_formats_attr,
1378 };
1379
1380 static struct intel_uncore_type ivbep_uncore_ubox = {
1381 .name = "ubox",
1382 .num_counters = 2,
1383 .num_boxes = 1,
1384 .perf_ctr_bits = 44,
1385 .fixed_ctr_bits = 48,
1386 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
1387 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
1388 .event_mask = IVBEP_U_MSR_PMON_RAW_EVENT_MASK,
1389 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
1390 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
1391 .ops = &ivbep_uncore_msr_ops,
1392 .format_group = &ivbep_uncore_ubox_format_group,
1393 };
1394
1395 static struct extra_reg ivbep_uncore_cbox_extra_regs[] = {
1396 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1397 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1398 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1399 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
1400 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1401 SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
1402 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1403 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
1404 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1405 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
1406 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1407 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
1408 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1409 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1410 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1411 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1412 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1413 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1414 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1415 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1416 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1417 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1418 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1419 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1420 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1421 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1422 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
1423 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1424 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1425 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1426 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1427 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1428 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1429 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1430 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1431 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1432 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1433 EVENT_EXTRA_END
1434 };
1435
1436 static u64 ivbep_cbox_filter_mask(int fields)
1437 {
1438 u64 mask = 0;
1439
1440 if (fields & 0x1)
1441 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_TID;
1442 if (fields & 0x2)
1443 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK;
1444 if (fields & 0x4)
1445 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
1446 if (fields & 0x8)
1447 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NID;
1448 if (fields & 0x10) {
1449 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
1450 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NC;
1451 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_C6;
1452 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC;
1453 }
1454
1455 return mask;
1456 }
1457
1458 static struct event_constraint *
1459 ivbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1460 {
1461 return __snbep_cbox_get_constraint(box, event, ivbep_cbox_filter_mask);
1462 }
1463
1464 static int ivbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1465 {
1466 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1467 struct extra_reg *er;
1468 int idx = 0;
1469
1470 for (er = ivbep_uncore_cbox_extra_regs; er->msr; er++) {
1471 if (er->event != (event->hw.config & er->config_mask))
1472 continue;
1473 idx |= er->idx;
1474 }
1475
1476 if (idx) {
1477 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
1478 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1479 reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx);
1480 reg1->idx = idx;
1481 }
1482 return 0;
1483 }
1484
1485 static void ivbep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1486 {
1487 struct hw_perf_event *hwc = &event->hw;
1488 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1489
1490 if (reg1->idx != EXTRA_REG_NONE) {
1491 u64 filter = uncore_shared_reg_config(box, 0);
1492 wrmsrl(reg1->reg, filter & 0xffffffff);
1493 wrmsrl(reg1->reg + 6, filter >> 32);
1494 }
1495
1496 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1497 }
1498
1499 static struct intel_uncore_ops ivbep_uncore_cbox_ops = {
1500 .init_box = ivbep_uncore_msr_init_box,
1501 .disable_box = snbep_uncore_msr_disable_box,
1502 .enable_box = snbep_uncore_msr_enable_box,
1503 .disable_event = snbep_uncore_msr_disable_event,
1504 .enable_event = ivbep_cbox_enable_event,
1505 .read_counter = uncore_msr_read_counter,
1506 .hw_config = ivbep_cbox_hw_config,
1507 .get_constraint = ivbep_cbox_get_constraint,
1508 .put_constraint = snbep_cbox_put_constraint,
1509 };
1510
1511 static struct intel_uncore_type ivbep_uncore_cbox = {
1512 .name = "cbox",
1513 .num_counters = 4,
1514 .num_boxes = 15,
1515 .perf_ctr_bits = 44,
1516 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
1517 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
1518 .event_mask = IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
1519 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
1520 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1521 .num_shared_regs = 1,
1522 .constraints = snbep_uncore_cbox_constraints,
1523 .ops = &ivbep_uncore_cbox_ops,
1524 .format_group = &ivbep_uncore_cbox_format_group,
1525 };
1526
1527 static struct intel_uncore_ops ivbep_uncore_pcu_ops = {
1528 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1529 .hw_config = snbep_pcu_hw_config,
1530 .get_constraint = snbep_pcu_get_constraint,
1531 .put_constraint = snbep_pcu_put_constraint,
1532 };
1533
1534 static struct intel_uncore_type ivbep_uncore_pcu = {
1535 .name = "pcu",
1536 .num_counters = 4,
1537 .num_boxes = 1,
1538 .perf_ctr_bits = 48,
1539 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
1540 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
1541 .event_mask = IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
1542 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
1543 .num_shared_regs = 1,
1544 .ops = &ivbep_uncore_pcu_ops,
1545 .format_group = &ivbep_uncore_pcu_format_group,
1546 };
1547
1548 static struct intel_uncore_type *ivbep_msr_uncores[] = {
1549 &ivbep_uncore_ubox,
1550 &ivbep_uncore_cbox,
1551 &ivbep_uncore_pcu,
1552 NULL,
1553 };
1554
1555 void ivbep_uncore_cpu_init(void)
1556 {
1557 if (ivbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
1558 ivbep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
1559 uncore_msr_uncores = ivbep_msr_uncores;
1560 }
1561
1562 static struct intel_uncore_type ivbep_uncore_ha = {
1563 .name = "ha",
1564 .num_counters = 4,
1565 .num_boxes = 2,
1566 .perf_ctr_bits = 48,
1567 IVBEP_UNCORE_PCI_COMMON_INIT(),
1568 };
1569
1570 static struct intel_uncore_type ivbep_uncore_imc = {
1571 .name = "imc",
1572 .num_counters = 4,
1573 .num_boxes = 8,
1574 .perf_ctr_bits = 48,
1575 .fixed_ctr_bits = 48,
1576 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1577 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1578 .event_descs = snbep_uncore_imc_events,
1579 IVBEP_UNCORE_PCI_COMMON_INIT(),
1580 };
1581
1582 /* registers in IRP boxes are not properly aligned */
1583 static unsigned ivbep_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4};
1584 static unsigned ivbep_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0};
1585
1586 static void ivbep_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1587 {
1588 struct pci_dev *pdev = box->pci_dev;
1589 struct hw_perf_event *hwc = &event->hw;
1590
1591 pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx],
1592 hwc->config | SNBEP_PMON_CTL_EN);
1593 }
1594
1595 static void ivbep_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1596 {
1597 struct pci_dev *pdev = box->pci_dev;
1598 struct hw_perf_event *hwc = &event->hw;
1599
1600 pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], hwc->config);
1601 }
1602
1603 static u64 ivbep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
1604 {
1605 struct pci_dev *pdev = box->pci_dev;
1606 struct hw_perf_event *hwc = &event->hw;
1607 u64 count = 0;
1608
1609 pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
1610 pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
1611
1612 return count;
1613 }
1614
1615 static struct intel_uncore_ops ivbep_uncore_irp_ops = {
1616 .init_box = ivbep_uncore_pci_init_box,
1617 .disable_box = snbep_uncore_pci_disable_box,
1618 .enable_box = snbep_uncore_pci_enable_box,
1619 .disable_event = ivbep_uncore_irp_disable_event,
1620 .enable_event = ivbep_uncore_irp_enable_event,
1621 .read_counter = ivbep_uncore_irp_read_counter,
1622 };
1623
1624 static struct intel_uncore_type ivbep_uncore_irp = {
1625 .name = "irp",
1626 .num_counters = 4,
1627 .num_boxes = 1,
1628 .perf_ctr_bits = 48,
1629 .event_mask = IVBEP_PMON_RAW_EVENT_MASK,
1630 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1631 .ops = &ivbep_uncore_irp_ops,
1632 .format_group = &ivbep_uncore_format_group,
1633 };
1634
1635 static struct intel_uncore_ops ivbep_uncore_qpi_ops = {
1636 .init_box = ivbep_uncore_pci_init_box,
1637 .disable_box = snbep_uncore_pci_disable_box,
1638 .enable_box = snbep_uncore_pci_enable_box,
1639 .disable_event = snbep_uncore_pci_disable_event,
1640 .enable_event = snbep_qpi_enable_event,
1641 .read_counter = snbep_uncore_pci_read_counter,
1642 .hw_config = snbep_qpi_hw_config,
1643 .get_constraint = uncore_get_constraint,
1644 .put_constraint = uncore_put_constraint,
1645 };
1646
1647 static struct intel_uncore_type ivbep_uncore_qpi = {
1648 .name = "qpi",
1649 .num_counters = 4,
1650 .num_boxes = 3,
1651 .perf_ctr_bits = 48,
1652 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1653 .event_ctl = SNBEP_PCI_PMON_CTL0,
1654 .event_mask = IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
1655 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1656 .num_shared_regs = 1,
1657 .ops = &ivbep_uncore_qpi_ops,
1658 .format_group = &ivbep_uncore_qpi_format_group,
1659 };
1660
1661 static struct intel_uncore_type ivbep_uncore_r2pcie = {
1662 .name = "r2pcie",
1663 .num_counters = 4,
1664 .num_boxes = 1,
1665 .perf_ctr_bits = 44,
1666 .constraints = snbep_uncore_r2pcie_constraints,
1667 IVBEP_UNCORE_PCI_COMMON_INIT(),
1668 };
1669
1670 static struct intel_uncore_type ivbep_uncore_r3qpi = {
1671 .name = "r3qpi",
1672 .num_counters = 3,
1673 .num_boxes = 2,
1674 .perf_ctr_bits = 44,
1675 .constraints = snbep_uncore_r3qpi_constraints,
1676 IVBEP_UNCORE_PCI_COMMON_INIT(),
1677 };
1678
1679 enum {
1680 IVBEP_PCI_UNCORE_HA,
1681 IVBEP_PCI_UNCORE_IMC,
1682 IVBEP_PCI_UNCORE_IRP,
1683 IVBEP_PCI_UNCORE_QPI,
1684 IVBEP_PCI_UNCORE_R2PCIE,
1685 IVBEP_PCI_UNCORE_R3QPI,
1686 };
1687
1688 static struct intel_uncore_type *ivbep_pci_uncores[] = {
1689 [IVBEP_PCI_UNCORE_HA] = &ivbep_uncore_ha,
1690 [IVBEP_PCI_UNCORE_IMC] = &ivbep_uncore_imc,
1691 [IVBEP_PCI_UNCORE_IRP] = &ivbep_uncore_irp,
1692 [IVBEP_PCI_UNCORE_QPI] = &ivbep_uncore_qpi,
1693 [IVBEP_PCI_UNCORE_R2PCIE] = &ivbep_uncore_r2pcie,
1694 [IVBEP_PCI_UNCORE_R3QPI] = &ivbep_uncore_r3qpi,
1695 NULL,
1696 };
1697
1698 static const struct pci_device_id ivbep_uncore_pci_ids[] = {
1699 { /* Home Agent 0 */
1700 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
1701 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 0),
1702 },
1703 { /* Home Agent 1 */
1704 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
1705 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 1),
1706 },
1707 { /* MC0 Channel 0 */
1708 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
1709 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 0),
1710 },
1711 { /* MC0 Channel 1 */
1712 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
1713 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 1),
1714 },
1715 { /* MC0 Channel 3 */
1716 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
1717 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 2),
1718 },
1719 { /* MC0 Channel 4 */
1720 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
1721 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 3),
1722 },
1723 { /* MC1 Channel 0 */
1724 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
1725 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 4),
1726 },
1727 { /* MC1 Channel 1 */
1728 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
1729 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 5),
1730 },
1731 { /* MC1 Channel 3 */
1732 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
1733 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 6),
1734 },
1735 { /* MC1 Channel 4 */
1736 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
1737 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 7),
1738 },
1739 { /* IRP */
1740 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39),
1741 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IRP, 0),
1742 },
1743 { /* QPI0 Port 0 */
1744 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
1745 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 0),
1746 },
1747 { /* QPI0 Port 1 */
1748 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
1749 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 1),
1750 },
1751 { /* QPI1 Port 2 */
1752 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
1753 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 2),
1754 },
1755 { /* R2PCIe */
1756 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
1757 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R2PCIE, 0),
1758 },
1759 { /* R3QPI0 Link 0 */
1760 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
1761 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 0),
1762 },
1763 { /* R3QPI0 Link 1 */
1764 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
1765 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 1),
1766 },
1767 { /* R3QPI1 Link 2 */
1768 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
1769 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 2),
1770 },
1771 { /* QPI Port 0 filter */
1772 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86),
1773 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1774 SNBEP_PCI_QPI_PORT0_FILTER),
1775 },
1776 { /* QPI Port 0 filter */
1777 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96),
1778 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1779 SNBEP_PCI_QPI_PORT1_FILTER),
1780 },
1781 { /* end: all zeroes */ }
1782 };
1783
1784 static struct pci_driver ivbep_uncore_pci_driver = {
1785 .name = "ivbep_uncore",
1786 .id_table = ivbep_uncore_pci_ids,
1787 };
1788
1789 int ivbep_uncore_pci_init(void)
1790 {
1791 int ret = snbep_pci2phy_map_init(0x0e1e);
1792 if (ret)
1793 return ret;
1794 uncore_pci_uncores = ivbep_pci_uncores;
1795 uncore_pci_driver = &ivbep_uncore_pci_driver;
1796 return 0;
1797 }
1798 /* end of IvyTown uncore support */
1799
1800 /* KNL uncore support */
1801 static struct attribute *knl_uncore_ubox_formats_attr[] = {
1802 &format_attr_event.attr,
1803 &format_attr_umask.attr,
1804 &format_attr_edge.attr,
1805 &format_attr_tid_en.attr,
1806 &format_attr_inv.attr,
1807 &format_attr_thresh5.attr,
1808 NULL,
1809 };
1810
1811 static struct attribute_group knl_uncore_ubox_format_group = {
1812 .name = "format",
1813 .attrs = knl_uncore_ubox_formats_attr,
1814 };
1815
1816 static struct intel_uncore_type knl_uncore_ubox = {
1817 .name = "ubox",
1818 .num_counters = 2,
1819 .num_boxes = 1,
1820 .perf_ctr_bits = 48,
1821 .fixed_ctr_bits = 48,
1822 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
1823 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
1824 .event_mask = KNL_U_MSR_PMON_RAW_EVENT_MASK,
1825 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
1826 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
1827 .ops = &snbep_uncore_msr_ops,
1828 .format_group = &knl_uncore_ubox_format_group,
1829 };
1830
1831 static struct attribute *knl_uncore_cha_formats_attr[] = {
1832 &format_attr_event.attr,
1833 &format_attr_umask.attr,
1834 &format_attr_qor.attr,
1835 &format_attr_edge.attr,
1836 &format_attr_tid_en.attr,
1837 &format_attr_inv.attr,
1838 &format_attr_thresh8.attr,
1839 &format_attr_filter_tid4.attr,
1840 &format_attr_filter_link3.attr,
1841 &format_attr_filter_state4.attr,
1842 &format_attr_filter_local.attr,
1843 &format_attr_filter_all_op.attr,
1844 &format_attr_filter_nnm.attr,
1845 &format_attr_filter_opc3.attr,
1846 &format_attr_filter_nc.attr,
1847 &format_attr_filter_isoc.attr,
1848 NULL,
1849 };
1850
1851 static struct attribute_group knl_uncore_cha_format_group = {
1852 .name = "format",
1853 .attrs = knl_uncore_cha_formats_attr,
1854 };
1855
1856 static struct event_constraint knl_uncore_cha_constraints[] = {
1857 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
1858 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
1859 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
1860 EVENT_CONSTRAINT_END
1861 };
1862
1863 static struct extra_reg knl_uncore_cha_extra_regs[] = {
1864 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1865 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1866 SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2),
1867 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4),
1868 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4),
1869 EVENT_EXTRA_END
1870 };
1871
1872 static u64 knl_cha_filter_mask(int fields)
1873 {
1874 u64 mask = 0;
1875
1876 if (fields & 0x1)
1877 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID;
1878 if (fields & 0x2)
1879 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE;
1880 if (fields & 0x4)
1881 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP;
1882 return mask;
1883 }
1884
1885 static struct event_constraint *
1886 knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1887 {
1888 return __snbep_cbox_get_constraint(box, event, knl_cha_filter_mask);
1889 }
1890
1891 static int knl_cha_hw_config(struct intel_uncore_box *box,
1892 struct perf_event *event)
1893 {
1894 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1895 struct extra_reg *er;
1896 int idx = 0;
1897
1898 for (er = knl_uncore_cha_extra_regs; er->msr; er++) {
1899 if (er->event != (event->hw.config & er->config_mask))
1900 continue;
1901 idx |= er->idx;
1902 }
1903
1904 if (idx) {
1905 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
1906 KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
1907 reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
1908
1909 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE;
1910 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE;
1911 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC;
1912 reg1->idx = idx;
1913 }
1914 return 0;
1915 }
1916
1917 static void hswep_cbox_enable_event(struct intel_uncore_box *box,
1918 struct perf_event *event);
1919
1920 static struct intel_uncore_ops knl_uncore_cha_ops = {
1921 .init_box = snbep_uncore_msr_init_box,
1922 .disable_box = snbep_uncore_msr_disable_box,
1923 .enable_box = snbep_uncore_msr_enable_box,
1924 .disable_event = snbep_uncore_msr_disable_event,
1925 .enable_event = hswep_cbox_enable_event,
1926 .read_counter = uncore_msr_read_counter,
1927 .hw_config = knl_cha_hw_config,
1928 .get_constraint = knl_cha_get_constraint,
1929 .put_constraint = snbep_cbox_put_constraint,
1930 };
1931
1932 static struct intel_uncore_type knl_uncore_cha = {
1933 .name = "cha",
1934 .num_counters = 4,
1935 .num_boxes = 38,
1936 .perf_ctr_bits = 48,
1937 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
1938 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
1939 .event_mask = KNL_CHA_MSR_PMON_RAW_EVENT_MASK,
1940 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
1941 .msr_offset = KNL_CHA_MSR_OFFSET,
1942 .num_shared_regs = 1,
1943 .constraints = knl_uncore_cha_constraints,
1944 .ops = &knl_uncore_cha_ops,
1945 .format_group = &knl_uncore_cha_format_group,
1946 };
1947
1948 static struct attribute *knl_uncore_pcu_formats_attr[] = {
1949 &format_attr_event2.attr,
1950 &format_attr_use_occ_ctr.attr,
1951 &format_attr_occ_sel.attr,
1952 &format_attr_edge.attr,
1953 &format_attr_tid_en.attr,
1954 &format_attr_inv.attr,
1955 &format_attr_thresh6.attr,
1956 &format_attr_occ_invert.attr,
1957 &format_attr_occ_edge_det.attr,
1958 NULL,
1959 };
1960
1961 static struct attribute_group knl_uncore_pcu_format_group = {
1962 .name = "format",
1963 .attrs = knl_uncore_pcu_formats_attr,
1964 };
1965
1966 static struct intel_uncore_type knl_uncore_pcu = {
1967 .name = "pcu",
1968 .num_counters = 4,
1969 .num_boxes = 1,
1970 .perf_ctr_bits = 48,
1971 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
1972 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
1973 .event_mask = KNL_PCU_MSR_PMON_RAW_EVENT_MASK,
1974 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
1975 .ops = &snbep_uncore_msr_ops,
1976 .format_group = &knl_uncore_pcu_format_group,
1977 };
1978
1979 static struct intel_uncore_type *knl_msr_uncores[] = {
1980 &knl_uncore_ubox,
1981 &knl_uncore_cha,
1982 &knl_uncore_pcu,
1983 NULL,
1984 };
1985
1986 void knl_uncore_cpu_init(void)
1987 {
1988 uncore_msr_uncores = knl_msr_uncores;
1989 }
1990
1991 static void knl_uncore_imc_enable_box(struct intel_uncore_box *box)
1992 {
1993 struct pci_dev *pdev = box->pci_dev;
1994 int box_ctl = uncore_pci_box_ctl(box);
1995
1996 pci_write_config_dword(pdev, box_ctl, 0);
1997 }
1998
1999 static void knl_uncore_imc_enable_event(struct intel_uncore_box *box,
2000 struct perf_event *event)
2001 {
2002 struct pci_dev *pdev = box->pci_dev;
2003 struct hw_perf_event *hwc = &event->hw;
2004
2005 if ((event->attr.config & SNBEP_PMON_CTL_EV_SEL_MASK)
2006 == UNCORE_FIXED_EVENT)
2007 pci_write_config_dword(pdev, hwc->config_base,
2008 hwc->config | KNL_PMON_FIXED_CTL_EN);
2009 else
2010 pci_write_config_dword(pdev, hwc->config_base,
2011 hwc->config | SNBEP_PMON_CTL_EN);
2012 }
2013
2014 static struct intel_uncore_ops knl_uncore_imc_ops = {
2015 .init_box = snbep_uncore_pci_init_box,
2016 .disable_box = snbep_uncore_pci_disable_box,
2017 .enable_box = knl_uncore_imc_enable_box,
2018 .read_counter = snbep_uncore_pci_read_counter,
2019 .enable_event = knl_uncore_imc_enable_event,
2020 .disable_event = snbep_uncore_pci_disable_event,
2021 };
2022
2023 static struct intel_uncore_type knl_uncore_imc_uclk = {
2024 .name = "imc_uclk",
2025 .num_counters = 4,
2026 .num_boxes = 2,
2027 .perf_ctr_bits = 48,
2028 .fixed_ctr_bits = 48,
2029 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW,
2030 .event_ctl = KNL_UCLK_MSR_PMON_CTL0,
2031 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2032 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW,
2033 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL,
2034 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL,
2035 .ops = &knl_uncore_imc_ops,
2036 .format_group = &snbep_uncore_format_group,
2037 };
2038
2039 static struct intel_uncore_type knl_uncore_imc_dclk = {
2040 .name = "imc",
2041 .num_counters = 4,
2042 .num_boxes = 6,
2043 .perf_ctr_bits = 48,
2044 .fixed_ctr_bits = 48,
2045 .perf_ctr = KNL_MC0_CH0_MSR_PMON_CTR0_LOW,
2046 .event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0,
2047 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2048 .fixed_ctr = KNL_MC0_CH0_MSR_PMON_FIXED_LOW,
2049 .fixed_ctl = KNL_MC0_CH0_MSR_PMON_FIXED_CTL,
2050 .box_ctl = KNL_MC0_CH0_MSR_PMON_BOX_CTL,
2051 .ops = &knl_uncore_imc_ops,
2052 .format_group = &snbep_uncore_format_group,
2053 };
2054
2055 static struct intel_uncore_type knl_uncore_edc_uclk = {
2056 .name = "edc_uclk",
2057 .num_counters = 4,
2058 .num_boxes = 8,
2059 .perf_ctr_bits = 48,
2060 .fixed_ctr_bits = 48,
2061 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW,
2062 .event_ctl = KNL_UCLK_MSR_PMON_CTL0,
2063 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2064 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW,
2065 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL,
2066 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL,
2067 .ops = &knl_uncore_imc_ops,
2068 .format_group = &snbep_uncore_format_group,
2069 };
2070
2071 static struct intel_uncore_type knl_uncore_edc_eclk = {
2072 .name = "edc_eclk",
2073 .num_counters = 4,
2074 .num_boxes = 8,
2075 .perf_ctr_bits = 48,
2076 .fixed_ctr_bits = 48,
2077 .perf_ctr = KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW,
2078 .event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0,
2079 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2080 .fixed_ctr = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW,
2081 .fixed_ctl = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL,
2082 .box_ctl = KNL_EDC0_ECLK_MSR_PMON_BOX_CTL,
2083 .ops = &knl_uncore_imc_ops,
2084 .format_group = &snbep_uncore_format_group,
2085 };
2086
2087 static struct event_constraint knl_uncore_m2pcie_constraints[] = {
2088 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2089 EVENT_CONSTRAINT_END
2090 };
2091
2092 static struct intel_uncore_type knl_uncore_m2pcie = {
2093 .name = "m2pcie",
2094 .num_counters = 4,
2095 .num_boxes = 1,
2096 .perf_ctr_bits = 48,
2097 .constraints = knl_uncore_m2pcie_constraints,
2098 SNBEP_UNCORE_PCI_COMMON_INIT(),
2099 };
2100
2101 static struct attribute *knl_uncore_irp_formats_attr[] = {
2102 &format_attr_event.attr,
2103 &format_attr_umask.attr,
2104 &format_attr_qor.attr,
2105 &format_attr_edge.attr,
2106 &format_attr_inv.attr,
2107 &format_attr_thresh8.attr,
2108 NULL,
2109 };
2110
2111 static struct attribute_group knl_uncore_irp_format_group = {
2112 .name = "format",
2113 .attrs = knl_uncore_irp_formats_attr,
2114 };
2115
2116 static struct intel_uncore_type knl_uncore_irp = {
2117 .name = "irp",
2118 .num_counters = 2,
2119 .num_boxes = 1,
2120 .perf_ctr_bits = 48,
2121 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2122 .event_ctl = SNBEP_PCI_PMON_CTL0,
2123 .event_mask = KNL_IRP_PCI_PMON_RAW_EVENT_MASK,
2124 .box_ctl = KNL_IRP_PCI_PMON_BOX_CTL,
2125 .ops = &snbep_uncore_pci_ops,
2126 .format_group = &knl_uncore_irp_format_group,
2127 };
2128
2129 enum {
2130 KNL_PCI_UNCORE_MC_UCLK,
2131 KNL_PCI_UNCORE_MC_DCLK,
2132 KNL_PCI_UNCORE_EDC_UCLK,
2133 KNL_PCI_UNCORE_EDC_ECLK,
2134 KNL_PCI_UNCORE_M2PCIE,
2135 KNL_PCI_UNCORE_IRP,
2136 };
2137
2138 static struct intel_uncore_type *knl_pci_uncores[] = {
2139 [KNL_PCI_UNCORE_MC_UCLK] = &knl_uncore_imc_uclk,
2140 [KNL_PCI_UNCORE_MC_DCLK] = &knl_uncore_imc_dclk,
2141 [KNL_PCI_UNCORE_EDC_UCLK] = &knl_uncore_edc_uclk,
2142 [KNL_PCI_UNCORE_EDC_ECLK] = &knl_uncore_edc_eclk,
2143 [KNL_PCI_UNCORE_M2PCIE] = &knl_uncore_m2pcie,
2144 [KNL_PCI_UNCORE_IRP] = &knl_uncore_irp,
2145 NULL,
2146 };
2147
2148 /*
2149 * KNL uses a common PCI device ID for multiple instances of an Uncore PMU
2150 * device type. prior to KNL, each instance of a PMU device type had a unique
2151 * device ID.
2152 *
2153 * PCI Device ID Uncore PMU Devices
2154 * ----------------------------------
2155 * 0x7841 MC0 UClk, MC1 UClk
2156 * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2,
2157 * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2
2158 * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk,
2159 * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk
2160 * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk,
2161 * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk
2162 * 0x7817 M2PCIe
2163 * 0x7814 IRP
2164 */
2165
2166 static const struct pci_device_id knl_uncore_pci_ids[] = {
2167 { /* MC UClk */
2168 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841),
2169 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_MC_UCLK, 0),
2170 },
2171 { /* MC DClk Channel */
2172 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2173 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_MC_DCLK, 0),
2174 },
2175 { /* EDC UClk */
2176 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2177 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_EDC_UCLK, 0),
2178 },
2179 { /* EDC EClk */
2180 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2181 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_EDC_ECLK, 0),
2182 },
2183 { /* M2PCIe */
2184 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817),
2185 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0),
2186 },
2187 { /* IRP */
2188 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814),
2189 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0),
2190 },
2191 { /* end: all zeroes */ }
2192 };
2193
2194 static struct pci_driver knl_uncore_pci_driver = {
2195 .name = "knl_uncore",
2196 .id_table = knl_uncore_pci_ids,
2197 };
2198
2199 int knl_uncore_pci_init(void)
2200 {
2201 int ret;
2202
2203 /* All KNL PCI based PMON units are on the same PCI bus except IRP */
2204 ret = snb_pci2phy_map_init(0x7814); /* IRP */
2205 if (ret)
2206 return ret;
2207 ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */
2208 if (ret)
2209 return ret;
2210 uncore_pci_uncores = knl_pci_uncores;
2211 uncore_pci_driver = &knl_uncore_pci_driver;
2212 return 0;
2213 }
2214
2215 /* end of KNL uncore support */
2216
2217 /* Haswell-EP uncore support */
2218 static struct attribute *hswep_uncore_ubox_formats_attr[] = {
2219 &format_attr_event.attr,
2220 &format_attr_umask.attr,
2221 &format_attr_edge.attr,
2222 &format_attr_inv.attr,
2223 &format_attr_thresh5.attr,
2224 &format_attr_filter_tid2.attr,
2225 &format_attr_filter_cid.attr,
2226 NULL,
2227 };
2228
2229 static struct attribute_group hswep_uncore_ubox_format_group = {
2230 .name = "format",
2231 .attrs = hswep_uncore_ubox_formats_attr,
2232 };
2233
2234 static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2235 {
2236 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2237 reg1->reg = HSWEP_U_MSR_PMON_FILTER;
2238 reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK;
2239 reg1->idx = 0;
2240 return 0;
2241 }
2242
2243 static struct intel_uncore_ops hswep_uncore_ubox_ops = {
2244 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
2245 .hw_config = hswep_ubox_hw_config,
2246 .get_constraint = uncore_get_constraint,
2247 .put_constraint = uncore_put_constraint,
2248 };
2249
2250 static struct intel_uncore_type hswep_uncore_ubox = {
2251 .name = "ubox",
2252 .num_counters = 2,
2253 .num_boxes = 1,
2254 .perf_ctr_bits = 44,
2255 .fixed_ctr_bits = 48,
2256 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
2257 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
2258 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
2259 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
2260 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
2261 .num_shared_regs = 1,
2262 .ops = &hswep_uncore_ubox_ops,
2263 .format_group = &hswep_uncore_ubox_format_group,
2264 };
2265
2266 static struct attribute *hswep_uncore_cbox_formats_attr[] = {
2267 &format_attr_event.attr,
2268 &format_attr_umask.attr,
2269 &format_attr_edge.attr,
2270 &format_attr_tid_en.attr,
2271 &format_attr_thresh8.attr,
2272 &format_attr_filter_tid3.attr,
2273 &format_attr_filter_link2.attr,
2274 &format_attr_filter_state3.attr,
2275 &format_attr_filter_nid2.attr,
2276 &format_attr_filter_opc2.attr,
2277 &format_attr_filter_nc.attr,
2278 &format_attr_filter_c6.attr,
2279 &format_attr_filter_isoc.attr,
2280 NULL,
2281 };
2282
2283 static struct attribute_group hswep_uncore_cbox_format_group = {
2284 .name = "format",
2285 .attrs = hswep_uncore_cbox_formats_attr,
2286 };
2287
2288 static struct event_constraint hswep_uncore_cbox_constraints[] = {
2289 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
2290 UNCORE_EVENT_CONSTRAINT(0x09, 0x1),
2291 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2292 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
2293 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
2294 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
2295 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
2296 EVENT_CONSTRAINT_END
2297 };
2298
2299 static struct extra_reg hswep_uncore_cbox_extra_regs[] = {
2300 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
2301 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
2302 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
2303 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
2304 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
2305 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
2306 SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4),
2307 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4),
2308 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
2309 SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8),
2310 SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8),
2311 SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8),
2312 SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8),
2313 SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8),
2314 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12),
2315 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
2316 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
2317 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
2318 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
2319 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
2320 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
2321 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
2322 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
2323 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
2324 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
2325 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
2326 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
2327 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
2328 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
2329 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
2330 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
2331 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
2332 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
2333 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
2334 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
2335 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
2336 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
2337 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
2338 EVENT_EXTRA_END
2339 };
2340
2341 static u64 hswep_cbox_filter_mask(int fields)
2342 {
2343 u64 mask = 0;
2344 if (fields & 0x1)
2345 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID;
2346 if (fields & 0x2)
2347 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK;
2348 if (fields & 0x4)
2349 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE;
2350 if (fields & 0x8)
2351 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID;
2352 if (fields & 0x10) {
2353 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC;
2354 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC;
2355 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6;
2356 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC;
2357 }
2358 return mask;
2359 }
2360
2361 static struct event_constraint *
2362 hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2363 {
2364 return __snbep_cbox_get_constraint(box, event, hswep_cbox_filter_mask);
2365 }
2366
2367 static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2368 {
2369 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2370 struct extra_reg *er;
2371 int idx = 0;
2372
2373 for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) {
2374 if (er->event != (event->hw.config & er->config_mask))
2375 continue;
2376 idx |= er->idx;
2377 }
2378
2379 if (idx) {
2380 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
2381 HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
2382 reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx);
2383 reg1->idx = idx;
2384 }
2385 return 0;
2386 }
2387
2388 static void hswep_cbox_enable_event(struct intel_uncore_box *box,
2389 struct perf_event *event)
2390 {
2391 struct hw_perf_event *hwc = &event->hw;
2392 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2393
2394 if (reg1->idx != EXTRA_REG_NONE) {
2395 u64 filter = uncore_shared_reg_config(box, 0);
2396 wrmsrl(reg1->reg, filter & 0xffffffff);
2397 wrmsrl(reg1->reg + 1, filter >> 32);
2398 }
2399
2400 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
2401 }
2402
2403 static struct intel_uncore_ops hswep_uncore_cbox_ops = {
2404 .init_box = snbep_uncore_msr_init_box,
2405 .disable_box = snbep_uncore_msr_disable_box,
2406 .enable_box = snbep_uncore_msr_enable_box,
2407 .disable_event = snbep_uncore_msr_disable_event,
2408 .enable_event = hswep_cbox_enable_event,
2409 .read_counter = uncore_msr_read_counter,
2410 .hw_config = hswep_cbox_hw_config,
2411 .get_constraint = hswep_cbox_get_constraint,
2412 .put_constraint = snbep_cbox_put_constraint,
2413 };
2414
2415 static struct intel_uncore_type hswep_uncore_cbox = {
2416 .name = "cbox",
2417 .num_counters = 4,
2418 .num_boxes = 18,
2419 .perf_ctr_bits = 48,
2420 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
2421 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
2422 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
2423 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
2424 .msr_offset = HSWEP_CBO_MSR_OFFSET,
2425 .num_shared_regs = 1,
2426 .constraints = hswep_uncore_cbox_constraints,
2427 .ops = &hswep_uncore_cbox_ops,
2428 .format_group = &hswep_uncore_cbox_format_group,
2429 };
2430
2431 /*
2432 * Write SBOX Initialization register bit by bit to avoid spurious #GPs
2433 */
2434 static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box)
2435 {
2436 unsigned msr = uncore_msr_box_ctl(box);
2437
2438 if (msr) {
2439 u64 init = SNBEP_PMON_BOX_CTL_INT;
2440 u64 flags = 0;
2441 int i;
2442
2443 for_each_set_bit(i, (unsigned long *)&init, 64) {
2444 flags |= (1ULL << i);
2445 wrmsrl(msr, flags);
2446 }
2447 }
2448 }
2449
2450 static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = {
2451 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
2452 .init_box = hswep_uncore_sbox_msr_init_box
2453 };
2454
2455 static struct attribute *hswep_uncore_sbox_formats_attr[] = {
2456 &format_attr_event.attr,
2457 &format_attr_umask.attr,
2458 &format_attr_edge.attr,
2459 &format_attr_tid_en.attr,
2460 &format_attr_inv.attr,
2461 &format_attr_thresh8.attr,
2462 NULL,
2463 };
2464
2465 static struct attribute_group hswep_uncore_sbox_format_group = {
2466 .name = "format",
2467 .attrs = hswep_uncore_sbox_formats_attr,
2468 };
2469
2470 static struct intel_uncore_type hswep_uncore_sbox = {
2471 .name = "sbox",
2472 .num_counters = 4,
2473 .num_boxes = 4,
2474 .perf_ctr_bits = 44,
2475 .event_ctl = HSWEP_S0_MSR_PMON_CTL0,
2476 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
2477 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
2478 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
2479 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
2480 .ops = &hswep_uncore_sbox_msr_ops,
2481 .format_group = &hswep_uncore_sbox_format_group,
2482 };
2483
2484 static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2485 {
2486 struct hw_perf_event *hwc = &event->hw;
2487 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2488 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
2489
2490 if (ev_sel >= 0xb && ev_sel <= 0xe) {
2491 reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER;
2492 reg1->idx = ev_sel - 0xb;
2493 reg1->config = event->attr.config1 & (0xff << reg1->idx);
2494 }
2495 return 0;
2496 }
2497
2498 static struct intel_uncore_ops hswep_uncore_pcu_ops = {
2499 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
2500 .hw_config = hswep_pcu_hw_config,
2501 .get_constraint = snbep_pcu_get_constraint,
2502 .put_constraint = snbep_pcu_put_constraint,
2503 };
2504
2505 static struct intel_uncore_type hswep_uncore_pcu = {
2506 .name = "pcu",
2507 .num_counters = 4,
2508 .num_boxes = 1,
2509 .perf_ctr_bits = 48,
2510 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
2511 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
2512 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
2513 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
2514 .num_shared_regs = 1,
2515 .ops = &hswep_uncore_pcu_ops,
2516 .format_group = &snbep_uncore_pcu_format_group,
2517 };
2518
2519 static struct intel_uncore_type *hswep_msr_uncores[] = {
2520 &hswep_uncore_ubox,
2521 &hswep_uncore_cbox,
2522 &hswep_uncore_sbox,
2523 &hswep_uncore_pcu,
2524 NULL,
2525 };
2526
2527 void hswep_uncore_cpu_init(void)
2528 {
2529 int pkg = topology_phys_to_logical_pkg(0);
2530
2531 if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
2532 hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
2533
2534 /* Detect 6-8 core systems with only two SBOXes */
2535 if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) {
2536 u32 capid4;
2537
2538 pci_read_config_dword(uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3],
2539 0x94, &capid4);
2540 if (((capid4 >> 6) & 0x3) == 0)
2541 hswep_uncore_sbox.num_boxes = 2;
2542 }
2543
2544 uncore_msr_uncores = hswep_msr_uncores;
2545 }
2546
2547 static struct intel_uncore_type hswep_uncore_ha = {
2548 .name = "ha",
2549 .num_counters = 5,
2550 .num_boxes = 2,
2551 .perf_ctr_bits = 48,
2552 SNBEP_UNCORE_PCI_COMMON_INIT(),
2553 };
2554
2555 static struct uncore_event_desc hswep_uncore_imc_events[] = {
2556 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"),
2557 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
2558 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
2559 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
2560 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
2561 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
2562 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
2563 { /* end: all zeroes */ },
2564 };
2565
2566 static struct intel_uncore_type hswep_uncore_imc = {
2567 .name = "imc",
2568 .num_counters = 5,
2569 .num_boxes = 8,
2570 .perf_ctr_bits = 48,
2571 .fixed_ctr_bits = 48,
2572 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
2573 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
2574 .event_descs = hswep_uncore_imc_events,
2575 SNBEP_UNCORE_PCI_COMMON_INIT(),
2576 };
2577
2578 static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8};
2579
2580 static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
2581 {
2582 struct pci_dev *pdev = box->pci_dev;
2583 struct hw_perf_event *hwc = &event->hw;
2584 u64 count = 0;
2585
2586 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
2587 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
2588
2589 return count;
2590 }
2591
2592 static struct intel_uncore_ops hswep_uncore_irp_ops = {
2593 .init_box = snbep_uncore_pci_init_box,
2594 .disable_box = snbep_uncore_pci_disable_box,
2595 .enable_box = snbep_uncore_pci_enable_box,
2596 .disable_event = ivbep_uncore_irp_disable_event,
2597 .enable_event = ivbep_uncore_irp_enable_event,
2598 .read_counter = hswep_uncore_irp_read_counter,
2599 };
2600
2601 static struct intel_uncore_type hswep_uncore_irp = {
2602 .name = "irp",
2603 .num_counters = 4,
2604 .num_boxes = 1,
2605 .perf_ctr_bits = 48,
2606 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2607 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2608 .ops = &hswep_uncore_irp_ops,
2609 .format_group = &snbep_uncore_format_group,
2610 };
2611
2612 static struct intel_uncore_type hswep_uncore_qpi = {
2613 .name = "qpi",
2614 .num_counters = 5,
2615 .num_boxes = 3,
2616 .perf_ctr_bits = 48,
2617 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2618 .event_ctl = SNBEP_PCI_PMON_CTL0,
2619 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
2620 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2621 .num_shared_regs = 1,
2622 .ops = &snbep_uncore_qpi_ops,
2623 .format_group = &snbep_uncore_qpi_format_group,
2624 };
2625
2626 static struct event_constraint hswep_uncore_r2pcie_constraints[] = {
2627 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2628 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2629 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2630 UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
2631 UNCORE_EVENT_CONSTRAINT(0x24, 0x1),
2632 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
2633 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2634 UNCORE_EVENT_CONSTRAINT(0x27, 0x1),
2635 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
2636 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
2637 UNCORE_EVENT_CONSTRAINT(0x2a, 0x1),
2638 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
2639 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
2640 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2641 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
2642 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
2643 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
2644 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
2645 EVENT_CONSTRAINT_END
2646 };
2647
2648 static struct intel_uncore_type hswep_uncore_r2pcie = {
2649 .name = "r2pcie",
2650 .num_counters = 4,
2651 .num_boxes = 1,
2652 .perf_ctr_bits = 48,
2653 .constraints = hswep_uncore_r2pcie_constraints,
2654 SNBEP_UNCORE_PCI_COMMON_INIT(),
2655 };
2656
2657 static struct event_constraint hswep_uncore_r3qpi_constraints[] = {
2658 UNCORE_EVENT_CONSTRAINT(0x01, 0x3),
2659 UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
2660 UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
2661 UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
2662 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
2663 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
2664 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2665 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2666 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
2667 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2668 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
2669 UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
2670 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
2671 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
2672 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
2673 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
2674 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2675 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
2676 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2677 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
2678 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
2679 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
2680 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2681 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
2682 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
2683 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
2684 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
2685 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
2686 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
2687 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
2688 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
2689 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
2690 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
2691 EVENT_CONSTRAINT_END
2692 };
2693
2694 static struct intel_uncore_type hswep_uncore_r3qpi = {
2695 .name = "r3qpi",
2696 .num_counters = 4,
2697 .num_boxes = 3,
2698 .perf_ctr_bits = 44,
2699 .constraints = hswep_uncore_r3qpi_constraints,
2700 SNBEP_UNCORE_PCI_COMMON_INIT(),
2701 };
2702
2703 enum {
2704 HSWEP_PCI_UNCORE_HA,
2705 HSWEP_PCI_UNCORE_IMC,
2706 HSWEP_PCI_UNCORE_IRP,
2707 HSWEP_PCI_UNCORE_QPI,
2708 HSWEP_PCI_UNCORE_R2PCIE,
2709 HSWEP_PCI_UNCORE_R3QPI,
2710 };
2711
2712 static struct intel_uncore_type *hswep_pci_uncores[] = {
2713 [HSWEP_PCI_UNCORE_HA] = &hswep_uncore_ha,
2714 [HSWEP_PCI_UNCORE_IMC] = &hswep_uncore_imc,
2715 [HSWEP_PCI_UNCORE_IRP] = &hswep_uncore_irp,
2716 [HSWEP_PCI_UNCORE_QPI] = &hswep_uncore_qpi,
2717 [HSWEP_PCI_UNCORE_R2PCIE] = &hswep_uncore_r2pcie,
2718 [HSWEP_PCI_UNCORE_R3QPI] = &hswep_uncore_r3qpi,
2719 NULL,
2720 };
2721
2722 static const struct pci_device_id hswep_uncore_pci_ids[] = {
2723 { /* Home Agent 0 */
2724 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30),
2725 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0),
2726 },
2727 { /* Home Agent 1 */
2728 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38),
2729 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 1),
2730 },
2731 { /* MC0 Channel 0 */
2732 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0),
2733 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0),
2734 },
2735 { /* MC0 Channel 1 */
2736 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1),
2737 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1),
2738 },
2739 { /* MC0 Channel 2 */
2740 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4),
2741 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2),
2742 },
2743 { /* MC0 Channel 3 */
2744 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5),
2745 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3),
2746 },
2747 { /* MC1 Channel 0 */
2748 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0),
2749 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4),
2750 },
2751 { /* MC1 Channel 1 */
2752 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1),
2753 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5),
2754 },
2755 { /* MC1 Channel 2 */
2756 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4),
2757 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6),
2758 },
2759 { /* MC1 Channel 3 */
2760 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5),
2761 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7),
2762 },
2763 { /* IRP */
2764 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39),
2765 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0),
2766 },
2767 { /* QPI0 Port 0 */
2768 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32),
2769 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0),
2770 },
2771 { /* QPI0 Port 1 */
2772 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33),
2773 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 1),
2774 },
2775 { /* QPI1 Port 2 */
2776 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a),
2777 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 2),
2778 },
2779 { /* R2PCIe */
2780 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34),
2781 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0),
2782 },
2783 { /* R3QPI0 Link 0 */
2784 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36),
2785 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0),
2786 },
2787 { /* R3QPI0 Link 1 */
2788 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37),
2789 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 1),
2790 },
2791 { /* R3QPI1 Link 2 */
2792 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e),
2793 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 2),
2794 },
2795 { /* QPI Port 0 filter */
2796 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86),
2797 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2798 SNBEP_PCI_QPI_PORT0_FILTER),
2799 },
2800 { /* QPI Port 1 filter */
2801 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96),
2802 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2803 SNBEP_PCI_QPI_PORT1_FILTER),
2804 },
2805 { /* PCU.3 (for Capability registers) */
2806 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fc0),
2807 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2808 HSWEP_PCI_PCU_3),
2809 },
2810 { /* end: all zeroes */ }
2811 };
2812
2813 static struct pci_driver hswep_uncore_pci_driver = {
2814 .name = "hswep_uncore",
2815 .id_table = hswep_uncore_pci_ids,
2816 };
2817
2818 int hswep_uncore_pci_init(void)
2819 {
2820 int ret = snbep_pci2phy_map_init(0x2f1e);
2821 if (ret)
2822 return ret;
2823 uncore_pci_uncores = hswep_pci_uncores;
2824 uncore_pci_driver = &hswep_uncore_pci_driver;
2825 return 0;
2826 }
2827 /* end of Haswell-EP uncore support */
2828
2829 /* BDX uncore support */
2830
2831 static struct intel_uncore_type bdx_uncore_ubox = {
2832 .name = "ubox",
2833 .num_counters = 2,
2834 .num_boxes = 1,
2835 .perf_ctr_bits = 48,
2836 .fixed_ctr_bits = 48,
2837 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
2838 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
2839 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
2840 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
2841 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
2842 .num_shared_regs = 1,
2843 .ops = &ivbep_uncore_msr_ops,
2844 .format_group = &ivbep_uncore_ubox_format_group,
2845 };
2846
2847 static struct event_constraint bdx_uncore_cbox_constraints[] = {
2848 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
2849 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2850 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
2851 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
2852 EVENT_CONSTRAINT_END
2853 };
2854
2855 static struct intel_uncore_type bdx_uncore_cbox = {
2856 .name = "cbox",
2857 .num_counters = 4,
2858 .num_boxes = 24,
2859 .perf_ctr_bits = 48,
2860 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
2861 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
2862 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
2863 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
2864 .msr_offset = HSWEP_CBO_MSR_OFFSET,
2865 .num_shared_regs = 1,
2866 .constraints = bdx_uncore_cbox_constraints,
2867 .ops = &hswep_uncore_cbox_ops,
2868 .format_group = &hswep_uncore_cbox_format_group,
2869 };
2870
2871 static struct intel_uncore_type bdx_uncore_sbox = {
2872 .name = "sbox",
2873 .num_counters = 4,
2874 .num_boxes = 4,
2875 .perf_ctr_bits = 48,
2876 .event_ctl = HSWEP_S0_MSR_PMON_CTL0,
2877 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
2878 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
2879 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
2880 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
2881 .ops = &hswep_uncore_sbox_msr_ops,
2882 .format_group = &hswep_uncore_sbox_format_group,
2883 };
2884
2885 #define BDX_MSR_UNCORE_SBOX 3
2886
2887 static struct intel_uncore_type *bdx_msr_uncores[] = {
2888 &bdx_uncore_ubox,
2889 &bdx_uncore_cbox,
2890 &hswep_uncore_pcu,
2891 &bdx_uncore_sbox,
2892 NULL,
2893 };
2894
2895 void bdx_uncore_cpu_init(void)
2896 {
2897 if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
2898 bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
2899 uncore_msr_uncores = bdx_msr_uncores;
2900
2901 /* BDX-DE doesn't have SBOX */
2902 if (boot_cpu_data.x86_model == 86)
2903 uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
2904 }
2905
2906 static struct intel_uncore_type bdx_uncore_ha = {
2907 .name = "ha",
2908 .num_counters = 4,
2909 .num_boxes = 2,
2910 .perf_ctr_bits = 48,
2911 SNBEP_UNCORE_PCI_COMMON_INIT(),
2912 };
2913
2914 static struct intel_uncore_type bdx_uncore_imc = {
2915 .name = "imc",
2916 .num_counters = 5,
2917 .num_boxes = 8,
2918 .perf_ctr_bits = 48,
2919 .fixed_ctr_bits = 48,
2920 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
2921 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
2922 .event_descs = hswep_uncore_imc_events,
2923 SNBEP_UNCORE_PCI_COMMON_INIT(),
2924 };
2925
2926 static struct intel_uncore_type bdx_uncore_irp = {
2927 .name = "irp",
2928 .num_counters = 4,
2929 .num_boxes = 1,
2930 .perf_ctr_bits = 48,
2931 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2932 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2933 .ops = &hswep_uncore_irp_ops,
2934 .format_group = &snbep_uncore_format_group,
2935 };
2936
2937 static struct intel_uncore_type bdx_uncore_qpi = {
2938 .name = "qpi",
2939 .num_counters = 4,
2940 .num_boxes = 3,
2941 .perf_ctr_bits = 48,
2942 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2943 .event_ctl = SNBEP_PCI_PMON_CTL0,
2944 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
2945 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2946 .num_shared_regs = 1,
2947 .ops = &snbep_uncore_qpi_ops,
2948 .format_group = &snbep_uncore_qpi_format_group,
2949 };
2950
2951 static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
2952 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2953 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2954 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2955 UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
2956 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
2957 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2958 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
2959 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
2960 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2961 EVENT_CONSTRAINT_END
2962 };
2963
2964 static struct intel_uncore_type bdx_uncore_r2pcie = {
2965 .name = "r2pcie",
2966 .num_counters = 4,
2967 .num_boxes = 1,
2968 .perf_ctr_bits = 48,
2969 .constraints = bdx_uncore_r2pcie_constraints,
2970 SNBEP_UNCORE_PCI_COMMON_INIT(),
2971 };
2972
2973 static struct event_constraint bdx_uncore_r3qpi_constraints[] = {
2974 UNCORE_EVENT_CONSTRAINT(0x01, 0x7),
2975 UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
2976 UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
2977 UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
2978 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
2979 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
2980 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2981 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2982 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2983 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
2984 UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
2985 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
2986 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
2987 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
2988 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
2989 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2990 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
2991 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2992 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
2993 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
2994 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
2995 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2996 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
2997 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
2998 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
2999 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3000 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
3001 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
3002 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
3003 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
3004 EVENT_CONSTRAINT_END
3005 };
3006
3007 static struct intel_uncore_type bdx_uncore_r3qpi = {
3008 .name = "r3qpi",
3009 .num_counters = 3,
3010 .num_boxes = 3,
3011 .perf_ctr_bits = 48,
3012 .constraints = bdx_uncore_r3qpi_constraints,
3013 SNBEP_UNCORE_PCI_COMMON_INIT(),
3014 };
3015
3016 enum {
3017 BDX_PCI_UNCORE_HA,
3018 BDX_PCI_UNCORE_IMC,
3019 BDX_PCI_UNCORE_IRP,
3020 BDX_PCI_UNCORE_QPI,
3021 BDX_PCI_UNCORE_R2PCIE,
3022 BDX_PCI_UNCORE_R3QPI,
3023 };
3024
3025 static struct intel_uncore_type *bdx_pci_uncores[] = {
3026 [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
3027 [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
3028 [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
3029 [BDX_PCI_UNCORE_QPI] = &bdx_uncore_qpi,
3030 [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
3031 [BDX_PCI_UNCORE_R3QPI] = &bdx_uncore_r3qpi,
3032 NULL,
3033 };
3034
3035 static const struct pci_device_id bdx_uncore_pci_ids[] = {
3036 { /* Home Agent 0 */
3037 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
3038 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
3039 },
3040 { /* Home Agent 1 */
3041 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38),
3042 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 1),
3043 },
3044 { /* MC0 Channel 0 */
3045 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
3046 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
3047 },
3048 { /* MC0 Channel 1 */
3049 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
3050 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
3051 },
3052 { /* MC0 Channel 2 */
3053 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4),
3054 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 2),
3055 },
3056 { /* MC0 Channel 3 */
3057 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5),
3058 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 3),
3059 },
3060 { /* MC1 Channel 0 */
3061 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0),
3062 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 4),
3063 },
3064 { /* MC1 Channel 1 */
3065 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1),
3066 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 5),
3067 },
3068 { /* MC1 Channel 2 */
3069 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4),
3070 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 6),
3071 },
3072 { /* MC1 Channel 3 */
3073 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5),
3074 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 7),
3075 },
3076 { /* IRP */
3077 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
3078 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
3079 },
3080 { /* QPI0 Port 0 */
3081 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32),
3082 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0),
3083 },
3084 { /* QPI0 Port 1 */
3085 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33),
3086 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 1),
3087 },
3088 { /* QPI1 Port 2 */
3089 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a),
3090 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 2),
3091 },
3092 { /* R2PCIe */
3093 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
3094 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
3095 },
3096 { /* R3QPI0 Link 0 */
3097 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36),
3098 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0),
3099 },
3100 { /* R3QPI0 Link 1 */
3101 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37),
3102 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 1),
3103 },
3104 { /* R3QPI1 Link 2 */
3105 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e),
3106 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 2),
3107 },
3108 { /* QPI Port 0 filter */
3109 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86),
3110 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 0),
3111 },
3112 { /* QPI Port 1 filter */
3113 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96),
3114 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1),
3115 },
3116 { /* QPI Port 2 filter */
3117 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
3118 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2),
3119 },
3120 { /* end: all zeroes */ }
3121 };
3122
3123 static struct pci_driver bdx_uncore_pci_driver = {
3124 .name = "bdx_uncore",
3125 .id_table = bdx_uncore_pci_ids,
3126 };
3127
3128 int bdx_uncore_pci_init(void)
3129 {
3130 int ret = snbep_pci2phy_map_init(0x6f1e);
3131
3132 if (ret)
3133 return ret;
3134 uncore_pci_uncores = bdx_pci_uncores;
3135 uncore_pci_driver = &bdx_uncore_pci_driver;
3136 return 0;
3137 }
3138
3139 /* end of BDX uncore support */
Linux kernel - Deliverables
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