2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_FPU_INTERNAL_H
11 #define _ASM_X86_FPU_INTERNAL_H
13 #include <linux/compat.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
18 #include <asm/fpu/api.h>
19 #include <asm/fpu/xstate.h>
22 * High level FPU state handling functions:
24 extern void fpu__activate_curr(struct fpu
*fpu
);
25 extern void fpu__activate_fpstate_read(struct fpu
*fpu
);
26 extern void fpu__activate_fpstate_write(struct fpu
*fpu
);
27 extern void fpu__save(struct fpu
*fpu
);
28 extern void fpu__restore(struct fpu
*fpu
);
29 extern int fpu__restore_sig(void __user
*buf
, int ia32_frame
);
30 extern void fpu__drop(struct fpu
*fpu
);
31 extern int fpu__copy(struct fpu
*dst_fpu
, struct fpu
*src_fpu
);
32 extern void fpu__clear(struct fpu
*fpu
);
33 extern int fpu__exception_code(struct fpu
*fpu
, int trap_nr
);
34 extern int dump_fpu(struct pt_regs
*ptregs
, struct user_i387_struct
*fpstate
);
37 * Boot time FPU initialization functions:
39 extern void fpu__init_cpu(void);
40 extern void fpu__init_system_xstate(void);
41 extern void fpu__init_cpu_xstate(void);
42 extern void fpu__init_system(struct cpuinfo_x86
*c
);
43 extern void fpu__init_check_bugs(void);
44 extern void fpu__resume_cpu(void);
49 #ifdef CONFIG_X86_DEBUG_FPU
50 # define WARN_ON_FPU(x) WARN_ON_ONCE(x)
52 # define WARN_ON_FPU(x) ({ 0; })
56 * FPU related CPU feature flag helper routines:
58 static __always_inline __pure
bool use_eager_fpu(void)
60 return static_cpu_has_safe(X86_FEATURE_EAGER_FPU
);
63 static __always_inline __pure
bool use_xsaveopt(void)
65 return static_cpu_has_safe(X86_FEATURE_XSAVEOPT
);
68 static __always_inline __pure
bool use_xsave(void)
70 return static_cpu_has_safe(X86_FEATURE_XSAVE
);
73 static __always_inline __pure
bool use_fxsr(void)
75 return static_cpu_has_safe(X86_FEATURE_FXSR
);
79 * fpstate handling functions:
82 extern union fpregs_state init_fpstate
;
84 extern void fpstate_init(union fpregs_state
*state
);
85 #ifdef CONFIG_MATH_EMULATION
86 extern void fpstate_init_soft(struct swregs_state
*soft
);
88 static inline void fpstate_init_soft(struct swregs_state
*soft
) {}
90 static inline void fpstate_init_fxstate(struct fxregs_state
*fx
)
93 fx
->mxcsr
= MXCSR_DEFAULT
;
95 extern void fpstate_sanitize_xstate(struct fpu
*fpu
);
97 #define user_insn(insn, output, input...) \
100 asm volatile(ASM_STAC "\n" \
102 "2: " ASM_CLAC "\n" \
103 ".section .fixup,\"ax\"\n" \
104 "3: movl $-1,%[err]\n" \
107 _ASM_EXTABLE(1b, 3b) \
108 : [err] "=r" (err), output \
113 #define check_insn(insn, output, input...) \
116 asm volatile("1:" #insn "\n\t" \
118 ".section .fixup,\"ax\"\n" \
119 "3: movl $-1,%[err]\n" \
122 _ASM_EXTABLE(1b, 3b) \
123 : [err] "=r" (err), output \
128 static inline int copy_fregs_to_user(struct fregs_state __user
*fx
)
130 return user_insn(fnsave
%[fx
]; fwait
, [fx
] "=m" (*fx
), "m" (*fx
));
133 static inline int copy_fxregs_to_user(struct fxregs_state __user
*fx
)
135 if (config_enabled(CONFIG_X86_32
))
136 return user_insn(fxsave
%[fx
], [fx
] "=m" (*fx
), "m" (*fx
));
137 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
138 return user_insn(fxsaveq
%[fx
], [fx
] "=m" (*fx
), "m" (*fx
));
140 /* See comment in copy_fxregs_to_kernel() below. */
141 return user_insn(rex64
/fxsave (%[fx
]), "=m" (*fx
), [fx
] "R" (fx
));
144 static inline void copy_kernel_to_fxregs(struct fxregs_state
*fx
)
148 if (config_enabled(CONFIG_X86_32
)) {
149 err
= check_insn(fxrstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
151 if (config_enabled(CONFIG_AS_FXSAVEQ
)) {
152 err
= check_insn(fxrstorq
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
154 /* See comment in copy_fxregs_to_kernel() below. */
155 err
= check_insn(rex64
/fxrstor (%[fx
]), "=m" (*fx
), [fx
] "R" (fx
), "m" (*fx
));
158 /* Copying from a kernel buffer to FPU registers should never fail: */
162 static inline int copy_user_to_fxregs(struct fxregs_state __user
*fx
)
164 if (config_enabled(CONFIG_X86_32
))
165 return user_insn(fxrstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
166 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
167 return user_insn(fxrstorq
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
169 /* See comment in copy_fxregs_to_kernel() below. */
170 return user_insn(rex64
/fxrstor (%[fx
]), "=m" (*fx
), [fx
] "R" (fx
),
174 static inline void copy_kernel_to_fregs(struct fregs_state
*fx
)
176 int err
= check_insn(frstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
181 static inline int copy_user_to_fregs(struct fregs_state __user
*fx
)
183 return user_insn(frstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
186 static inline void copy_fxregs_to_kernel(struct fpu
*fpu
)
188 if (config_enabled(CONFIG_X86_32
))
189 asm volatile( "fxsave %[fx]" : [fx
] "=m" (fpu
->state
.fxsave
));
190 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
191 asm volatile("fxsaveq %[fx]" : [fx
] "=m" (fpu
->state
.fxsave
));
193 /* Using "rex64; fxsave %0" is broken because, if the memory
194 * operand uses any extended registers for addressing, a second
195 * REX prefix will be generated (to the assembler, rex64
196 * followed by semicolon is a separate instruction), and hence
197 * the 64-bitness is lost.
199 * Using "fxsaveq %0" would be the ideal choice, but is only
200 * supported starting with gas 2.16.
202 * Using, as a workaround, the properly prefixed form below
203 * isn't accepted by any binutils version so far released,
204 * complaining that the same type of prefix is used twice if
205 * an extended register is needed for addressing (fix submitted
206 * to mainline 2005-11-21).
208 * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave));
210 * This, however, we can work around by forcing the compiler to
211 * select an addressing mode that doesn't require extended
214 asm volatile( "rex64/fxsave (%[fx])"
215 : "=m" (fpu
->state
.fxsave
)
216 : [fx
] "R" (&fpu
->state
.fxsave
));
220 /* These macros all use (%edi)/(%rdi) as the single memory argument. */
221 #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
222 #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
223 #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
224 #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
225 #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
227 /* xstate instruction fault handler: */
228 #define xstate_fault(__err) \
230 ".section .fixup,\"ax\"\n" \
232 "3: movl $-2,%[_err]\n" \
237 _ASM_EXTABLE(1b, 3b) \
238 : [_err] "=r" (__err)
241 * This function is called only during boot time when x86 caps are not set
242 * up and alternative can not be used yet.
244 static inline void copy_xregs_to_kernel_booting(struct xregs_state
*xstate
)
248 u32 hmask
= mask
>> 32;
251 WARN_ON(system_state
!= SYSTEM_BOOTING
);
253 if (boot_cpu_has(X86_FEATURE_XSAVES
))
254 asm volatile("1:"XSAVES
"\n\t"
257 : "D" (xstate
), "m" (*xstate
), "a" (lmask
), "d" (hmask
), "0" (err
)
260 asm volatile("1:"XSAVE
"\n\t"
263 : "D" (xstate
), "m" (*xstate
), "a" (lmask
), "d" (hmask
), "0" (err
)
266 /* We should never fault when copying to a kernel buffer: */
271 * This function is called only during boot time when x86 caps are not set
272 * up and alternative can not be used yet.
274 static inline void copy_kernel_to_xregs_booting(struct xregs_state
*xstate
)
278 u32 hmask
= mask
>> 32;
281 WARN_ON(system_state
!= SYSTEM_BOOTING
);
283 if (boot_cpu_has(X86_FEATURE_XSAVES
))
284 asm volatile("1:"XRSTORS
"\n\t"
287 : "D" (xstate
), "m" (*xstate
), "a" (lmask
), "d" (hmask
), "0" (err
)
290 asm volatile("1:"XRSTOR
"\n\t"
293 : "D" (xstate
), "m" (*xstate
), "a" (lmask
), "d" (hmask
), "0" (err
)
296 /* We should never fault when copying from a kernel buffer: */
301 * Save processor xstate to xsave area.
303 static inline void copy_xregs_to_kernel(struct xregs_state
*xstate
)
307 u32 hmask
= mask
>> 32;
310 WARN_ON(!alternatives_patched
);
313 * If xsaves is enabled, xsaves replaces xsaveopt because
314 * it supports compact format and supervisor states in addition to
315 * modified optimization in xsaveopt.
317 * Otherwise, if xsaveopt is enabled, xsaveopt replaces xsave
318 * because xsaveopt supports modified optimization which is not
319 * supported by xsave.
321 * If none of xsaves and xsaveopt is enabled, use xsave.
326 X86_FEATURE_XSAVEOPT
,
329 [xstate
] "D" (xstate
), "a" (lmask
), "d" (hmask
) :
331 asm volatile("2:\n\t"
336 /* We should never fault when copying to a kernel buffer: */
341 * Restore processor xstate from xsave area.
343 static inline void copy_kernel_to_xregs(struct xregs_state
*xstate
, u64 mask
)
346 u32 hmask
= mask
>> 32;
350 * Use xrstors to restore context if it is enabled. xrstors supports
351 * compacted format of xsave area which is not supported by xrstor.
357 "D" (xstate
), "m" (*xstate
), "a" (lmask
), "d" (hmask
)
365 /* We should never fault when copying from a kernel buffer: */
370 * Save xstate to user space xsave area.
372 * We don't use modified optimization because xrstor/xrstors might track
373 * a different application.
375 * We don't use compacted format xsave area for
376 * backward compatibility for old applications which don't understand
377 * compacted format of xsave area.
379 static inline int copy_xregs_to_user(struct xregs_state __user
*buf
)
384 * Clear the xsave header first, so that reserved fields are
385 * initialized to zero.
387 err
= __clear_user(&buf
->header
, sizeof(buf
->header
));
391 __asm__
__volatile__(ASM_STAC
"\n"
395 : "D" (buf
), "a" (-1), "d" (-1), "0" (err
)
401 * Restore xstate from user space xsave area.
403 static inline int copy_user_to_xregs(struct xregs_state __user
*buf
, u64 mask
)
405 struct xregs_state
*xstate
= ((__force
struct xregs_state
*)buf
);
407 u32 hmask
= mask
>> 32;
410 __asm__
__volatile__(ASM_STAC
"\n"
414 : "D" (xstate
), "a" (lmask
), "d" (hmask
), "0" (err
)
415 : "memory"); /* memory required? */
420 * These must be called with preempt disabled. Returns
421 * 'true' if the FPU state is still intact and we can
422 * keep registers active.
424 * The legacy FNSAVE instruction cleared all FPU state
425 * unconditionally, so registers are essentially destroyed.
426 * Modern FPU state can be kept in registers, if there are
427 * no pending FP exceptions.
429 static inline int copy_fpregs_to_fpstate(struct fpu
*fpu
)
431 if (likely(use_xsave())) {
432 copy_xregs_to_kernel(&fpu
->state
.xsave
);
436 if (likely(use_fxsr())) {
437 copy_fxregs_to_kernel(fpu
);
442 * Legacy FPU register saving, FNSAVE always clears FPU registers,
443 * so we have to mark them inactive:
445 asm volatile("fnsave %[fp]; fwait" : [fp
] "=m" (fpu
->state
.fsave
));
450 static inline void __copy_kernel_to_fpregs(union fpregs_state
*fpstate
)
453 copy_kernel_to_xregs(&fpstate
->xsave
, -1);
456 copy_kernel_to_fxregs(&fpstate
->fxsave
);
458 copy_kernel_to_fregs(&fpstate
->fsave
);
462 static inline void copy_kernel_to_fpregs(union fpregs_state
*fpstate
)
465 * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
466 * pending. Clear the x87 state here by setting it to fixed values.
467 * "m" is a random variable that should be in L1.
469 if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK
))) {
473 "fildl %P[addr]" /* set F?P to defined value */
474 : : [addr
] "m" (fpstate
));
477 __copy_kernel_to_fpregs(fpstate
);
480 extern int copy_fpstate_to_sigframe(void __user
*buf
, void __user
*fp
, int size
);
483 * FPU context switch related helper methods:
486 DECLARE_PER_CPU(struct fpu
*, fpu_fpregs_owner_ctx
);
489 * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
492 * This will disable any lazy FPU state restore of the current FPU state,
493 * but if the current thread owns the FPU, it will still be saved by.
495 static inline void __cpu_disable_lazy_restore(unsigned int cpu
)
497 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
500 static inline int fpu_want_lazy_restore(struct fpu
*fpu
, unsigned int cpu
)
502 return fpu
== this_cpu_read_stable(fpu_fpregs_owner_ctx
) && cpu
== fpu
->last_cpu
;
507 * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation'
508 * idiom, which is then paired with the sw-flag (fpregs_active) later on:
511 static inline void __fpregs_activate_hw(void)
513 if (!use_eager_fpu())
517 static inline void __fpregs_deactivate_hw(void)
519 if (!use_eager_fpu())
523 /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */
524 static inline void __fpregs_deactivate(struct fpu
*fpu
)
526 WARN_ON_FPU(!fpu
->fpregs_active
);
528 fpu
->fpregs_active
= 0;
529 this_cpu_write(fpu_fpregs_owner_ctx
, NULL
);
532 /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */
533 static inline void __fpregs_activate(struct fpu
*fpu
)
535 WARN_ON_FPU(fpu
->fpregs_active
);
537 fpu
->fpregs_active
= 1;
538 this_cpu_write(fpu_fpregs_owner_ctx
, fpu
);
542 * The question "does this thread have fpu access?"
543 * is slightly racy, since preemption could come in
544 * and revoke it immediately after the test.
546 * However, even in that very unlikely scenario,
547 * we can just assume we have FPU access - typically
548 * to save the FP state - we'll just take a #NM
549 * fault and get the FPU access back.
551 static inline int fpregs_active(void)
553 return current
->thread
.fpu
.fpregs_active
;
557 * Encapsulate the CR0.TS handling together with the
560 * These generally need preemption protection to work,
561 * do try to avoid using these on their own.
563 static inline void fpregs_activate(struct fpu
*fpu
)
565 __fpregs_activate_hw();
566 __fpregs_activate(fpu
);
569 static inline void fpregs_deactivate(struct fpu
*fpu
)
571 __fpregs_deactivate(fpu
);
572 __fpregs_deactivate_hw();
576 * FPU state switching for scheduling.
578 * This is a two-stage process:
580 * - switch_fpu_prepare() saves the old state and
581 * sets the new state of the CR0.TS bit. This is
582 * done within the context of the old process.
584 * - switch_fpu_finish() restores the new state as
587 typedef struct { int preload
; } fpu_switch_t
;
589 static inline fpu_switch_t
590 switch_fpu_prepare(struct fpu
*old_fpu
, struct fpu
*new_fpu
, int cpu
)
595 * If the task has used the math, pre-load the FPU on xsave processors
596 * or if the past 5 consecutive context-switches used math.
598 fpu
.preload
= new_fpu
->fpstate_active
&&
599 (use_eager_fpu() || new_fpu
->counter
> 5);
601 if (old_fpu
->fpregs_active
) {
602 if (!copy_fpregs_to_fpstate(old_fpu
))
603 old_fpu
->last_cpu
= -1;
605 old_fpu
->last_cpu
= cpu
;
607 /* But leave fpu_fpregs_owner_ctx! */
608 old_fpu
->fpregs_active
= 0;
610 /* Don't change CR0.TS if we just switch! */
613 __fpregs_activate(new_fpu
);
614 prefetch(&new_fpu
->state
);
616 __fpregs_deactivate_hw();
619 old_fpu
->counter
= 0;
620 old_fpu
->last_cpu
= -1;
623 if (fpu_want_lazy_restore(new_fpu
, cpu
))
626 prefetch(&new_fpu
->state
);
627 fpregs_activate(new_fpu
);
634 * Misc helper functions:
638 * By the time this gets called, we've already cleared CR0.TS and
639 * given the process the FPU if we are going to preload the FPU
640 * state - all we need to do is to conditionally restore the register
643 static inline void switch_fpu_finish(struct fpu
*new_fpu
, fpu_switch_t fpu_switch
)
645 if (fpu_switch
.preload
)
646 copy_kernel_to_fpregs(&new_fpu
->state
);
650 * Needs to be preemption-safe.
652 * NOTE! user_fpu_begin() must be used only immediately before restoring
653 * the save state. It does not do any saving/restoring on its own. In
654 * lazy FPU mode, it is just an optimization to avoid a #NM exception,
655 * the task can lose the FPU right after preempt_enable().
657 static inline void user_fpu_begin(void)
659 struct fpu
*fpu
= ¤t
->thread
.fpu
;
662 if (!fpregs_active())
663 fpregs_activate(fpu
);
668 * MXCSR and XCR definitions:
671 extern unsigned int mxcsr_feature_mask
;
673 #define XCR_XFEATURE_ENABLED_MASK 0x00000000
675 static inline u64
xgetbv(u32 index
)
679 asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
680 : "=a" (eax
), "=d" (edx
)
682 return eax
+ ((u64
)edx
<< 32);
685 static inline void xsetbv(u32 index
, u64 value
)
688 u32 edx
= value
>> 32;
690 asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
691 : : "a" (eax
), "d" (edx
), "c" (index
));
694 #endif /* _ASM_X86_FPU_INTERNAL_H */