2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_FPU_INTERNAL_H
11 #define _ASM_X86_FPU_INTERNAL_H
13 #include <linux/regset.h>
14 #include <linux/compat.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
19 #include <asm/fpu/api.h>
20 #include <asm/fpu/xstate.h>
23 # include <asm/sigcontext32.h>
24 # include <asm/user32.h>
26 int ia32_setup_rt_frame(int sig
, struct ksignal
*ksig
,
27 compat_sigset_t
*set
, struct pt_regs
*regs
);
28 int ia32_setup_frame(int sig
, struct ksignal
*ksig
,
29 compat_sigset_t
*set
, struct pt_regs
*regs
);
31 # define user_i387_ia32_struct user_i387_struct
32 # define user32_fxsr_struct user_fxsr_struct
33 # define ia32_setup_frame __setup_frame
34 # define ia32_setup_rt_frame __setup_rt_frame
37 #define MXCSR_DEFAULT 0x1f80
39 extern unsigned int mxcsr_feature_mask
;
41 extern void fpu__init_cpu(void);
42 extern void fpu__init_system_xstate(void);
43 extern void fpu__init_cpu_xstate(void);
44 extern void fpu__init_system(struct cpuinfo_x86
*c
);
46 extern void fpu__activate_curr(struct fpu
*fpu
);
47 extern void fpstate_init(struct fpu
*fpu
);
49 extern int dump_fpu(struct pt_regs
*, struct user_i387_struct
*);
52 * High level FPU state handling functions:
54 extern void fpu__save(struct fpu
*fpu
);
55 extern void fpu__restore(void);
56 extern int fpu__restore_sig(void __user
*buf
, int ia32_frame
);
57 extern void fpu__drop(struct fpu
*fpu
);
58 extern int fpu__copy(struct fpu
*dst_fpu
, struct fpu
*src_fpu
);
59 extern void fpu__clear(struct fpu
*fpu
);
61 extern void fpu__init_check_bugs(void);
62 extern void fpu__resume_cpu(void);
64 DECLARE_PER_CPU(struct fpu
*, fpu_fpregs_owner_ctx
);
66 extern void convert_from_fxsr(struct user_i387_ia32_struct
*env
,
67 struct task_struct
*tsk
);
68 extern void convert_to_fxsr(struct task_struct
*tsk
,
69 const struct user_i387_ia32_struct
*env
);
71 extern user_regset_active_fn regset_fpregs_active
, regset_xregset_fpregs_active
;
72 extern user_regset_get_fn fpregs_get
, xfpregs_get
, fpregs_soft_get
,
74 extern user_regset_set_fn fpregs_set
, xfpregs_set
, fpregs_soft_set
,
78 * xstateregs_active == regset_fpregs_active. Please refer to the comment
79 * at the definition of regset_fpregs_active.
81 #define xstateregs_active regset_fpregs_active
83 #ifdef CONFIG_MATH_EMULATION
84 extern void finit_soft_fpu(struct i387_soft_struct
*soft
);
86 static inline void finit_soft_fpu(struct i387_soft_struct
*soft
) {}
90 * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
93 * This will disable any lazy FPU state restore of the current FPU state,
94 * but if the current thread owns the FPU, it will still be saved by.
96 static inline void __cpu_disable_lazy_restore(unsigned int cpu
)
98 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
101 static inline int fpu_want_lazy_restore(struct fpu
*fpu
, unsigned int cpu
)
103 return fpu
== this_cpu_read_stable(fpu_fpregs_owner_ctx
) && cpu
== fpu
->last_cpu
;
106 #define X87_FSW_ES (1 << 7) /* Exception Summary */
108 static __always_inline __pure
bool use_eager_fpu(void)
110 return static_cpu_has_safe(X86_FEATURE_EAGER_FPU
);
113 static __always_inline __pure
bool use_xsaveopt(void)
115 return static_cpu_has_safe(X86_FEATURE_XSAVEOPT
);
118 static __always_inline __pure
bool use_xsave(void)
120 return static_cpu_has_safe(X86_FEATURE_XSAVE
);
123 static __always_inline __pure
bool use_fxsr(void)
125 return static_cpu_has_safe(X86_FEATURE_FXSR
);
128 static inline void fx_finit(struct i387_fxsave_struct
*fx
)
131 fx
->mxcsr
= MXCSR_DEFAULT
;
134 extern void fpstate_sanitize_xstate(struct fpu
*fpu
);
136 #define user_insn(insn, output, input...) \
139 asm volatile(ASM_STAC "\n" \
141 "2: " ASM_CLAC "\n" \
142 ".section .fixup,\"ax\"\n" \
143 "3: movl $-1,%[err]\n" \
146 _ASM_EXTABLE(1b, 3b) \
147 : [err] "=r" (err), output \
152 #define check_insn(insn, output, input...) \
155 asm volatile("1:" #insn "\n\t" \
157 ".section .fixup,\"ax\"\n" \
158 "3: movl $-1,%[err]\n" \
161 _ASM_EXTABLE(1b, 3b) \
162 : [err] "=r" (err), output \
167 static inline int fsave_user(struct i387_fsave_struct __user
*fx
)
169 return user_insn(fnsave
%[fx
]; fwait
, [fx
] "=m" (*fx
), "m" (*fx
));
172 static inline int fxsave_user(struct i387_fxsave_struct __user
*fx
)
174 if (config_enabled(CONFIG_X86_32
))
175 return user_insn(fxsave
%[fx
], [fx
] "=m" (*fx
), "m" (*fx
));
176 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
177 return user_insn(fxsaveq
%[fx
], [fx
] "=m" (*fx
), "m" (*fx
));
179 /* See comment in fpu_fxsave() below. */
180 return user_insn(rex64
/fxsave (%[fx
]), "=m" (*fx
), [fx
] "R" (fx
));
183 static inline int fxrstor_checking(struct i387_fxsave_struct
*fx
)
185 if (config_enabled(CONFIG_X86_32
))
186 return check_insn(fxrstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
187 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
188 return check_insn(fxrstorq
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
190 /* See comment in fpu_fxsave() below. */
191 return check_insn(rex64
/fxrstor (%[fx
]), "=m" (*fx
), [fx
] "R" (fx
),
195 static inline int fxrstor_user(struct i387_fxsave_struct __user
*fx
)
197 if (config_enabled(CONFIG_X86_32
))
198 return user_insn(fxrstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
199 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
200 return user_insn(fxrstorq
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
202 /* See comment in fpu_fxsave() below. */
203 return user_insn(rex64
/fxrstor (%[fx
]), "=m" (*fx
), [fx
] "R" (fx
),
207 static inline int frstor_checking(struct i387_fsave_struct
*fx
)
209 return check_insn(frstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
212 static inline int frstor_user(struct i387_fsave_struct __user
*fx
)
214 return user_insn(frstor
%[fx
], "=m" (*fx
), [fx
] "m" (*fx
));
217 static inline void fpu_fxsave(struct fpu
*fpu
)
219 if (config_enabled(CONFIG_X86_32
))
220 asm volatile( "fxsave %[fx]" : [fx
] "=m" (fpu
->state
.fxsave
));
221 else if (config_enabled(CONFIG_AS_FXSAVEQ
))
222 asm volatile("fxsaveq %[fx]" : [fx
] "=m" (fpu
->state
.fxsave
));
224 /* Using "rex64; fxsave %0" is broken because, if the memory
225 * operand uses any extended registers for addressing, a second
226 * REX prefix will be generated (to the assembler, rex64
227 * followed by semicolon is a separate instruction), and hence
228 * the 64-bitness is lost.
230 * Using "fxsaveq %0" would be the ideal choice, but is only
231 * supported starting with gas 2.16.
233 * Using, as a workaround, the properly prefixed form below
234 * isn't accepted by any binutils version so far released,
235 * complaining that the same type of prefix is used twice if
236 * an extended register is needed for addressing (fix submitted
237 * to mainline 2005-11-21).
239 * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave));
241 * This, however, we can work around by forcing the compiler to
242 * select an addressing mode that doesn't require extended
245 asm volatile( "rex64/fxsave (%[fx])"
246 : "=m" (fpu
->state
.fxsave
)
247 : [fx
] "R" (&fpu
->state
.fxsave
));
252 * These must be called with preempt disabled. Returns
253 * 'true' if the FPU state is still intact and we can
254 * keep registers active.
256 * The legacy FNSAVE instruction cleared all FPU state
257 * unconditionally, so registers are essentially destroyed.
258 * Modern FPU state can be kept in registers, if there are
259 * no pending FP exceptions.
261 static inline int copy_fpregs_to_fpstate(struct fpu
*fpu
)
263 if (likely(use_xsave())) {
264 xsave_state(&fpu
->state
.xsave
);
268 if (likely(use_fxsr())) {
274 * Legacy FPU register saving, FNSAVE always clears FPU registers,
275 * so we have to mark them inactive:
277 asm volatile("fnsave %[fx]; fwait" : [fx
] "=m" (fpu
->state
.fsave
));
282 static inline int __copy_fpstate_to_fpregs(struct fpu
*fpu
)
285 return fpu_xrstor_checking(&fpu
->state
.xsave
);
287 return fxrstor_checking(&fpu
->state
.fxsave
);
289 return frstor_checking(&fpu
->state
.fsave
);
292 static inline int copy_fpstate_to_fpregs(struct fpu
*fpu
)
295 * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
296 * pending. Clear the x87 state here by setting it to fixed values.
297 * "m" is a random variable that should be in L1.
299 if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK
))) {
303 "fildl %P[addr]" /* set F?P to defined value */
304 : : [addr
] "m" (fpu
->fpregs_active
));
307 return __copy_fpstate_to_fpregs(fpu
);
311 * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation'
312 * idiom, which is then paired with the sw-flag (fpregs_active) later on:
315 static inline void __fpregs_activate_hw(void)
317 if (!use_eager_fpu())
321 static inline void __fpregs_deactivate_hw(void)
323 if (!use_eager_fpu())
327 /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */
328 static inline void __fpregs_deactivate(struct fpu
*fpu
)
330 fpu
->fpregs_active
= 0;
331 this_cpu_write(fpu_fpregs_owner_ctx
, NULL
);
334 /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */
335 static inline void __fpregs_activate(struct fpu
*fpu
)
337 fpu
->fpregs_active
= 1;
338 this_cpu_write(fpu_fpregs_owner_ctx
, fpu
);
342 * The question "does this thread have fpu access?"
343 * is slightly racy, since preemption could come in
344 * and revoke it immediately after the test.
346 * However, even in that very unlikely scenario,
347 * we can just assume we have FPU access - typically
348 * to save the FP state - we'll just take a #NM
349 * fault and get the FPU access back.
351 static inline int fpregs_active(void)
353 return current
->thread
.fpu
.fpregs_active
;
357 * Encapsulate the CR0.TS handling together with the
360 * These generally need preemption protection to work,
361 * do try to avoid using these on their own.
363 static inline void fpregs_activate(struct fpu
*fpu
)
365 __fpregs_activate_hw();
366 __fpregs_activate(fpu
);
369 static inline void fpregs_deactivate(struct fpu
*fpu
)
371 __fpregs_deactivate(fpu
);
372 __fpregs_deactivate_hw();
375 static inline void restore_init_xstate(void)
378 xrstor_state(&init_xstate_ctx
, -1);
380 fxrstor_checking(&init_xstate_ctx
.i387
);
384 * Definitions for the eXtended Control Register instructions
387 #define XCR_XFEATURE_ENABLED_MASK 0x00000000
389 static inline u64
xgetbv(u32 index
)
393 asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
394 : "=a" (eax
), "=d" (edx
)
396 return eax
+ ((u64
)edx
<< 32);
399 static inline void xsetbv(u32 index
, u64 value
)
402 u32 edx
= value
>> 32;
404 asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
405 : : "a" (eax
), "d" (edx
), "c" (index
));
409 * FPU state switching for scheduling.
411 * This is a two-stage process:
413 * - switch_fpu_prepare() saves the old state and
414 * sets the new state of the CR0.TS bit. This is
415 * done within the context of the old process.
417 * - switch_fpu_finish() restores the new state as
420 typedef struct { int preload
; } fpu_switch_t
;
422 static inline fpu_switch_t
423 switch_fpu_prepare(struct fpu
*old_fpu
, struct fpu
*new_fpu
, int cpu
)
428 * If the task has used the math, pre-load the FPU on xsave processors
429 * or if the past 5 consecutive context-switches used math.
431 fpu
.preload
= new_fpu
->fpstate_active
&&
432 (use_eager_fpu() || new_fpu
->counter
> 5);
434 if (old_fpu
->fpregs_active
) {
435 if (!copy_fpregs_to_fpstate(old_fpu
))
436 old_fpu
->last_cpu
= -1;
438 old_fpu
->last_cpu
= cpu
;
440 /* But leave fpu_fpregs_owner_ctx! */
441 old_fpu
->fpregs_active
= 0;
443 /* Don't change CR0.TS if we just switch! */
446 __fpregs_activate(new_fpu
);
447 prefetch(&new_fpu
->state
);
449 __fpregs_deactivate_hw();
452 old_fpu
->counter
= 0;
453 old_fpu
->last_cpu
= -1;
456 if (fpu_want_lazy_restore(new_fpu
, cpu
))
459 prefetch(&new_fpu
->state
);
460 fpregs_activate(new_fpu
);
467 * By the time this gets called, we've already cleared CR0.TS and
468 * given the process the FPU if we are going to preload the FPU
469 * state - all we need to do is to conditionally restore the register
472 static inline void switch_fpu_finish(struct fpu
*new_fpu
, fpu_switch_t fpu_switch
)
474 if (fpu_switch
.preload
) {
475 if (unlikely(copy_fpstate_to_fpregs(new_fpu
)))
481 * Signal frame handlers...
483 extern int copy_fpstate_to_sigframe(void __user
*buf
, void __user
*fx
, int size
);
486 * Needs to be preemption-safe.
488 * NOTE! user_fpu_begin() must be used only immediately before restoring
489 * the save state. It does not do any saving/restoring on its own. In
490 * lazy FPU mode, it is just an optimization to avoid a #NM exception,
491 * the task can lose the FPU right after preempt_enable().
493 static inline void user_fpu_begin(void)
495 struct fpu
*fpu
= ¤t
->thread
.fpu
;
498 if (!fpregs_active())
499 fpregs_activate(fpu
);
504 * i387 state interaction
506 static inline unsigned short get_fpu_cwd(struct task_struct
*tsk
)
509 return tsk
->thread
.fpu
.state
.fxsave
.cwd
;
511 return (unsigned short)tsk
->thread
.fpu
.state
.fsave
.cwd
;
515 static inline unsigned short get_fpu_swd(struct task_struct
*tsk
)
518 return tsk
->thread
.fpu
.state
.fxsave
.swd
;
520 return (unsigned short)tsk
->thread
.fpu
.state
.fsave
.swd
;
524 static inline unsigned short get_fpu_mxcsr(struct task_struct
*tsk
)
527 return tsk
->thread
.fpu
.state
.fxsave
.mxcsr
;
529 return MXCSR_DEFAULT
;
534 fpu__alloc_mathframe(unsigned long sp
, int ia32_frame
,
535 unsigned long *buf_fx
, unsigned long *size
);
537 #endif /* _ASM_X86_FPU_INTERNAL_H */