arch/x86/include/asm/i387.h

   1 /*
   2  * Copyright (C) 1994 Linus Torvalds
   3  *
   4  * Pentium III FXSR, SSE support
   5  * General FPU state handling cleanups
   6  *      Gareth Hughes <gareth@valinux.com>, May 2000
   7  * x86-64 work by Andi Kleen 2002
   8  */
   9
  10 #ifndef _ASM_X86_I387_H
  11 #define _ASM_X86_I387_H
  12
  13 #ifndef __ASSEMBLY__
  14
  15 #include <linux/sched.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/regset.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/slab.h>
  20 #include <asm/asm.h>
  21 #include <asm/cpufeature.h>
  22 #include <asm/processor.h>
  23 #include <asm/sigcontext.h>
  24 #include <asm/user.h>
  25 #include <asm/uaccess.h>
  26 #include <asm/xsave.h>
  27
  28 extern unsigned int sig_xstate_size;
  29 extern void fpu_init(void);
  30 extern void mxcsr_feature_mask_init(void);
  31 extern int init_fpu(struct task_struct *child);
  32 extern asmlinkage void math_state_restore(void);
  33 extern void __math_state_restore(void);
  34 extern void init_thread_xstate(void);
  35 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
  36
  37 extern user_regset_active_fn fpregs_active, xfpregs_active;
  38 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
  39                                 xstateregs_get;
  40 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
  41                                  xstateregs_set;
  42
  43 /*
  44  * xstateregs_active == fpregs_active. Please refer to the comment
  45  * at the definition of fpregs_active.
  46  */
  47 #define xstateregs_active       fpregs_active
  48
  49 extern struct _fpx_sw_bytes fx_sw_reserved;
  50 #ifdef CONFIG_IA32_EMULATION
  51 extern unsigned int sig_xstate_ia32_size;
  52 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
  53 struct _fpstate_ia32;
  54 struct _xstate_ia32;
  55 extern int save_i387_xstate_ia32(void __user *buf);
  56 extern int restore_i387_xstate_ia32(void __user *buf);
  57 #endif
  58
  59 #define X87_FSW_ES (1 << 7)     /* Exception Summary */
  60
  61 static __always_inline __pure bool use_xsave(void)
  62 {
  63         return static_cpu_has(X86_FEATURE_XSAVE);
  64 }
  65
  66 #ifdef CONFIG_X86_64
  67
  68 /* Ignore delayed exceptions from user space */
  69 static inline void tolerant_fwait(void)
  70 {
  71         asm volatile("1: fwait\n"
  72                      "2:\n"
  73                      _ASM_EXTABLE(1b, 2b));
  74 }
  75
  76 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  77 {
  78         int err;
  79
  80         asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
  81                      "2:\n"
  82                      ".section .fixup,\"ax\"\n"
  83                      "3:  movl $-1,%[err]\n"
  84                      "    jmp  2b\n"
  85                      ".previous\n"
  86                      _ASM_EXTABLE(1b, 3b)
  87                      : [err] "=r" (err)
  88 #if 0 /* See comment in fxsave() below. */
  89                      : [fx] "r" (fx), "m" (*fx), "0" (0));
  90 #else
  91                      : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
  92 #endif
  93         return err;
  94 }
  95
  96 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
  97    is pending. Clear the x87 state here by setting it to fixed
  98    values. The kernel data segment can be sometimes 0 and sometimes
  99    new user value. Both should be ok.
 100    Use the PDA as safe address because it should be already in L1. */
 101 static inline void fpu_clear(struct fpu *fpu)
 102 {
 103         struct xsave_struct *xstate = &fpu->state->xsave;
 104         struct i387_fxsave_struct *fx = &fpu->state->fxsave;
 105
 106         /*
 107          * xsave header may indicate the init state of the FP.
 108          */
 109         if (use_xsave() &&
 110             !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
 111                 return;
 112
 113         if (unlikely(fx->swd & X87_FSW_ES))
 114                 asm volatile("fnclex");
 115         alternative_input(ASM_NOP8 ASM_NOP2,
 116                           "    emms\n"          /* clear stack tags */
 117                           "    fildl %%gs:0",   /* load to clear state */
 118                           X86_FEATURE_FXSAVE_LEAK);
 119 }
 120
 121 static inline void clear_fpu_state(struct task_struct *tsk)
 122 {
 123         fpu_clear(&tsk->thread.fpu);
 124 }
 125
 126 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
 127 {
 128         int err;
 129
 130         /*
 131          * Clear the bytes not touched by the fxsave and reserved
 132          * for the SW usage.
 133          */
 134         err = __clear_user(&fx->sw_reserved,
 135                            sizeof(struct _fpx_sw_bytes));
 136         if (unlikely(err))
 137                 return -EFAULT;
 138
 139         asm volatile("1:  rex64/fxsave (%[fx])\n\t"
 140                      "2:\n"
 141                      ".section .fixup,\"ax\"\n"
 142                      "3:  movl $-1,%[err]\n"
 143                      "    jmp  2b\n"
 144                      ".previous\n"
 145                      _ASM_EXTABLE(1b, 3b)
 146                      : [err] "=r" (err), "=m" (*fx)
 147 #if 0 /* See comment in fxsave() below. */
 148                      : [fx] "r" (fx), "0" (0));
 149 #else
 150                      : [fx] "cdaSDb" (fx), "0" (0));
 151 #endif
 152         if (unlikely(err) &&
 153             __clear_user(fx, sizeof(struct i387_fxsave_struct)))
 154                 err = -EFAULT;
 155         /* No need to clear here because the caller clears USED_MATH */
 156         return err;
 157 }
 158
 159 static inline void fpu_fxsave(struct fpu *fpu)
 160 {
 161         /* Using "rex64; fxsave %0" is broken because, if the memory operand
 162            uses any extended registers for addressing, a second REX prefix
 163            will be generated (to the assembler, rex64 followed by semicolon
 164            is a separate instruction), and hence the 64-bitness is lost. */
 165 #if 0
 166         /* Using "fxsaveq %0" would be the ideal choice, but is only supported
 167            starting with gas 2.16. */
 168         __asm__ __volatile__("fxsaveq %0"
 169                              : "=m" (fpu->state->fxsave));
 170 #elif 0
 171         /* Using, as a workaround, the properly prefixed form below isn't
 172            accepted by any binutils version so far released, complaining that
 173            the same type of prefix is used twice if an extended register is
 174            needed for addressing (fix submitted to mainline 2005-11-21). */
 175         __asm__ __volatile__("rex64/fxsave %0"
 176                              : "=m" (fpu->state->fxsave));
 177 #else
 178         /* This, however, we can work around by forcing the compiler to select
 179            an addressing mode that doesn't require extended registers. */
 180         __asm__ __volatile__("rex64/fxsave (%1)"
 181                              : "=m" (fpu->state->fxsave)
 182                              : "cdaSDb" (&fpu->state->fxsave));
 183 #endif
 184 }
 185
 186 static inline void fpu_save_init(struct fpu *fpu)
 187 {
 188         if (use_xsave())
 189                 fpu_xsave(fpu);
 190         else
 191                 fpu_fxsave(fpu);
 192
 193         fpu_clear(fpu);
 194 }
 195
 196 static inline void __save_init_fpu(struct task_struct *tsk)
 197 {
 198         fpu_save_init(&tsk->thread.fpu);
 199         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 200 }
 201
 202 #else  /* CONFIG_X86_32 */
 203
 204 #ifdef CONFIG_MATH_EMULATION
 205 extern void finit_soft_fpu(struct i387_soft_struct *soft);
 206 #else
 207 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
 208 #endif
 209
 210 static inline void tolerant_fwait(void)
 211 {
 212         asm volatile("fnclex ; fwait");
 213 }
 214
 215 /* perform fxrstor iff the processor has extended states, otherwise frstor */
 216 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
 217 {
 218         /*
 219          * The "nop" is needed to make the instructions the same
 220          * length.
 221          */
 222         alternative_input(
 223                 "nop ; frstor %1",
 224                 "fxrstor %1",
 225                 X86_FEATURE_FXSR,
 226                 "m" (*fx));
 227
 228         return 0;
 229 }
 230
 231 /* We need a safe address that is cheap to find and that is already
 232    in L1 during context switch. The best choices are unfortunately
 233    different for UP and SMP */
 234 #ifdef CONFIG_SMP
 235 #define safe_address (__per_cpu_offset[0])
 236 #else
 237 #define safe_address (kstat_cpu(0).cpustat.user)
 238 #endif
 239
 240 /*
 241  * These must be called with preempt disabled
 242  */
 243 static inline void fpu_save_init(struct fpu *fpu)
 244 {
 245         if (use_xsave()) {
 246                 struct xsave_struct *xstate = &fpu->state->xsave;
 247                 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
 248
 249                 fpu_xsave(fpu);
 250
 251                 /*
 252                  * xsave header may indicate the init state of the FP.
 253                  */
 254                 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
 255                         goto end;
 256
 257                 if (unlikely(fx->swd & X87_FSW_ES))
 258                         asm volatile("fnclex");
 259
 260                 /*
 261                  * we can do a simple return here or be paranoid :)
 262                  */
 263                 goto clear_state;
 264         }
 265
 266         /* Use more nops than strictly needed in case the compiler
 267            varies code */
 268         alternative_input(
 269                 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
 270                 "fxsave %[fx]\n"
 271                 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
 272                 X86_FEATURE_FXSR,
 273                 [fx] "m" (fpu->state->fxsave),
 274                 [fsw] "m" (fpu->state->fxsave.swd) : "memory");
 275 clear_state:
 276         /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
 277            is pending.  Clear the x87 state here by setting it to fixed
 278            values. safe_address is a random variable that should be in L1 */
 279         alternative_input(
 280                 GENERIC_NOP8 GENERIC_NOP2,
 281                 "emms\n\t"              /* clear stack tags */
 282                 "fildl %[addr]",        /* set F?P to defined value */
 283                 X86_FEATURE_FXSAVE_LEAK,
 284                 [addr] "m" (safe_address));
 285 end:
 286         ;
 287 }
 288
 289 static inline void __save_init_fpu(struct task_struct *tsk)
 290 {
 291         fpu_save_init(&tsk->thread.fpu);
 292         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 293 }
 294
 295
 296 #endif  /* CONFIG_X86_64 */
 297
 298 static inline int fpu_fxrstor_checking(struct fpu *fpu)
 299 {
 300         return fxrstor_checking(&fpu->state->fxsave);
 301 }
 302
 303 static inline int fpu_restore_checking(struct fpu *fpu)
 304 {
 305         if (use_xsave())
 306                 return fpu_xrstor_checking(fpu);
 307         else
 308                 return fpu_fxrstor_checking(fpu);
 309 }
 310
 311 static inline int restore_fpu_checking(struct task_struct *tsk)
 312 {
 313         return fpu_restore_checking(&tsk->thread.fpu);
 314 }
 315
 316 /*
 317  * Signal frame handlers...
 318  */
 319 extern int save_i387_xstate(void __user *buf);
 320 extern int restore_i387_xstate(void __user *buf);
 321
 322 static inline void __unlazy_fpu(struct task_struct *tsk)
 323 {
 324         if (task_thread_info(tsk)->status & TS_USEDFPU) {
 325                 __save_init_fpu(tsk);
 326                 stts();
 327         } else
 328                 tsk->fpu_counter = 0;
 329 }
 330
 331 static inline void __clear_fpu(struct task_struct *tsk)
 332 {
 333         if (task_thread_info(tsk)->status & TS_USEDFPU) {
 334                 tolerant_fwait();
 335                 task_thread_info(tsk)->status &= ~TS_USEDFPU;
 336                 stts();
 337         }
 338 }
 339
 340 static inline void kernel_fpu_begin(void)
 341 {
 342         struct thread_info *me = current_thread_info();
 343         preempt_disable();
 344         if (me->status & TS_USEDFPU)
 345                 __save_init_fpu(me->task);
 346         else
 347                 clts();
 348 }
 349
 350 static inline void kernel_fpu_end(void)
 351 {
 352         stts();
 353         preempt_enable();
 354 }
 355
 356 static inline bool irq_fpu_usable(void)
 357 {
 358         struct pt_regs *regs;
 359
 360         return !in_interrupt() || !(regs = get_irq_regs()) || \
 361                 user_mode(regs) || (read_cr0() & X86_CR0_TS);
 362 }
 363
 364 /*
 365  * Some instructions like VIA's padlock instructions generate a spurious
 366  * DNA fault but don't modify SSE registers. And these instructions
 367  * get used from interrupt context as well. To prevent these kernel instructions
 368  * in interrupt context interacting wrongly with other user/kernel fpu usage, we
 369  * should use them only in the context of irq_ts_save/restore()
 370  */
 371 static inline int irq_ts_save(void)
 372 {
 373         /*
 374          * If in process context and not atomic, we can take a spurious DNA fault.
 375          * Otherwise, doing clts() in process context requires disabling preemption
 376          * or some heavy lifting like kernel_fpu_begin()
 377          */
 378         if (!in_atomic())
 379                 return 0;
 380
 381         if (read_cr0() & X86_CR0_TS) {
 382                 clts();
 383                 return 1;
 384         }
 385
 386         return 0;
 387 }
 388
 389 static inline void irq_ts_restore(int TS_state)
 390 {
 391         if (TS_state)
 392                 stts();
 393 }
 394
 395 #ifdef CONFIG_X86_64
 396
 397 static inline void save_init_fpu(struct task_struct *tsk)
 398 {
 399         __save_init_fpu(tsk);
 400         stts();
 401 }
 402
 403 #define unlazy_fpu      __unlazy_fpu
 404 #define clear_fpu       __clear_fpu
 405
 406 #else  /* CONFIG_X86_32 */
 407
 408 /*
 409  * These disable preemption on their own and are safe
 410  */
 411 static inline void save_init_fpu(struct task_struct *tsk)
 412 {
 413         preempt_disable();
 414         __save_init_fpu(tsk);
 415         stts();
 416         preempt_enable();
 417 }
 418
 419 static inline void unlazy_fpu(struct task_struct *tsk)
 420 {
 421         preempt_disable();
 422         __unlazy_fpu(tsk);
 423         preempt_enable();
 424 }
 425
 426 static inline void clear_fpu(struct task_struct *tsk)
 427 {
 428         preempt_disable();
 429         __clear_fpu(tsk);
 430         preempt_enable();
 431 }
 432
 433 #endif  /* CONFIG_X86_64 */
 434
 435 /*
 436  * i387 state interaction
 437  */
 438 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
 439 {
 440         if (cpu_has_fxsr) {
 441                 return tsk->thread.fpu.state->fxsave.cwd;
 442         } else {
 443                 return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
 444         }
 445 }
 446
 447 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
 448 {
 449         if (cpu_has_fxsr) {
 450                 return tsk->thread.fpu.state->fxsave.swd;
 451         } else {
 452                 return (unsigned short)tsk->thread.fpu.state->fsave.swd;
 453         }
 454 }
 455
 456 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
 457 {
 458         if (cpu_has_xmm) {
 459                 return tsk->thread.fpu.state->fxsave.mxcsr;
 460         } else {
 461                 return MXCSR_DEFAULT;
 462         }
 463 }
 464
 465 static bool fpu_allocated(struct fpu *fpu)
 466 {
 467         return fpu->state != NULL;
 468 }
 469
 470 static inline int fpu_alloc(struct fpu *fpu)
 471 {
 472         if (fpu_allocated(fpu))
 473                 return 0;
 474         fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
 475         if (!fpu->state)
 476                 return -ENOMEM;
 477         WARN_ON((unsigned long)fpu->state & 15);
 478         return 0;
 479 }
 480
 481 static inline void fpu_free(struct fpu *fpu)
 482 {
 483         if (fpu->state) {
 484                 kmem_cache_free(task_xstate_cachep, fpu->state);
 485                 fpu->state = NULL;
 486         }
 487 }
 488
 489 static inline void fpu_copy(struct fpu *dst, struct fpu *src)
 490 {
 491         memcpy(dst->state, src->state, xstate_size);
 492 }
 493
 494 #endif /* __ASSEMBLY__ */
 495
 496 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
 497 #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
 498
 499 #endif /* _ASM_X86_I387_H */