arch/x86/include/asm/intel-mid.h

   1 /*
   2  * intel-mid.h: Intel MID specific setup code
   3  *
   4  * (C) Copyright 2009 Intel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; version 2
   9  * of the License.
  10  */
  11 #ifndef _ASM_X86_INTEL_MID_H
  12 #define _ASM_X86_INTEL_MID_H
  13
  14 #include <linux/sfi.h>
  15 #include <linux/pci.h>
  16 #include <linux/platform_device.h>
  17
  18 extern int intel_mid_pci_init(void);
  19 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
  20
  21 #define INTEL_MID_PWR_LSS_OFFSET        4
  22 #define INTEL_MID_PWR_LSS_TYPE          (1 << 7)
  23
  24 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
  25
  26 extern int get_gpio_by_name(const char *name);
  27 extern void intel_scu_device_register(struct platform_device *pdev);
  28 extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
  29 extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
  30 extern int sfi_mrtc_num;
  31 extern struct sfi_rtc_table_entry sfi_mrtc_array[];
  32
  33 /*
  34  * Here defines the array of devices platform data that IAFW would export
  35  * through SFI "DEVS" table, we use name and type to match the device and
  36  * its platform data.
  37  */
  38 struct devs_id {
  39         char name[SFI_NAME_LEN + 1];
  40         u8 type;
  41         u8 delay;
  42         void *(*get_platform_data)(void *info);
  43         /* Custom handler for devices */
  44         void (*device_handler)(struct sfi_device_table_entry *pentry,
  45                                struct devs_id *dev);
  46 };
  47
  48 #define sfi_device(i)                                                           \
  49         static const struct devs_id *const __intel_mid_sfi_##i##_dev __used     \
  50         __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
  51
  52 /**
  53 * struct mid_sd_board_info - template for SD device creation
  54 * @name:                identifies the driver
  55 * @bus_num:             board-specific identifier for a given SD controller
  56 * @max_clk:             the maximum frequency device supports
  57 * @platform_data:       the particular data stored there is driver-specific
  58 */
  59 struct mid_sd_board_info {
  60         char            name[SFI_NAME_LEN];
  61         int             bus_num;
  62         unsigned short  addr;
  63         u32             max_clk;
  64         void            *platform_data;
  65 };
  66
  67 /*
  68  * Medfield is the follow-up of Moorestown, it combines two chip solution into
  69  * one. Other than that it also added always-on and constant tsc and lapic
  70  * timers. Medfield is the platform name, and the chip name is called Penwell
  71  * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
  72  * identified via MSRs.
  73  */
  74 enum intel_mid_cpu_type {
  75         /* 1 was Moorestown */
  76         INTEL_MID_CPU_CHIP_PENWELL = 2,
  77         INTEL_MID_CPU_CHIP_CLOVERVIEW,
  78         INTEL_MID_CPU_CHIP_TANGIER,
  79 };
  80
  81 extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
  82
  83 /**
  84  * struct intel_mid_ops - Interface between intel-mid & sub archs
  85  * @arch_setup: arch_setup function to re-initialize platform
  86  *              structures (x86_init, x86_platform_init)
  87  *
  88  * This structure can be extended if any new interface is required
  89  * between intel-mid & its sub arch files.
  90  */
  91 struct intel_mid_ops {
  92         void (*arch_setup)(void);
  93 };
  94
  95 /* Helper API's for INTEL_MID_OPS_INIT */
  96 #define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid)                              \
  97         [cpuid] = get_##cpuname##_ops
  98
  99 /* Maximum number of CPU ops */
 100 #define MAX_CPU_OPS(a)                  (sizeof(a)/sizeof(void *))
 101
 102 /*
 103  * For every new cpu addition, a weak get_<cpuname>_ops() function needs be
 104  * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
 105  */
 106 #define INTEL_MID_OPS_INIT {                                                    \
 107         DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL),        \
 108         DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW),  \
 109         DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER)         \
 110 };
 111
 112 #ifdef CONFIG_X86_INTEL_MID
 113
 114 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
 115 {
 116         return __intel_mid_cpu_chip;
 117 }
 118
 119 static inline bool intel_mid_has_msic(void)
 120 {
 121         return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
 122 }
 123
 124 #else /* !CONFIG_X86_INTEL_MID */
 125
 126 #define intel_mid_identify_cpu()        0
 127 #define intel_mid_has_msic()            0
 128
 129 #endif /* !CONFIG_X86_INTEL_MID */
 130
 131 enum intel_mid_timer_options {
 132         INTEL_MID_TIMER_DEFAULT,
 133         INTEL_MID_TIMER_APBT_ONLY,
 134         INTEL_MID_TIMER_LAPIC_APBT,
 135 };
 136
 137 extern enum intel_mid_timer_options intel_mid_timer_options;
 138
 139 /*
 140  * Penwell uses spread spectrum clock, so the freq number is not exactly
 141  * the same as reported by MSR based on SDM.
 142  */
 143 #define FSB_FREQ_83SKU                  83200
 144 #define FSB_FREQ_100SKU                 99840
 145 #define FSB_FREQ_133SKU                 133000
 146
 147 #define FSB_FREQ_167SKU                 167000
 148 #define FSB_FREQ_200SKU                 200000
 149 #define FSB_FREQ_267SKU                 267000
 150 #define FSB_FREQ_333SKU                 333000
 151 #define FSB_FREQ_400SKU                 400000
 152
 153 /* Bus Select SoC Fuse value */
 154 #define BSEL_SOC_FUSE_MASK              0x7
 155 /* FSB 133MHz */
 156 #define BSEL_SOC_FUSE_001               0x1
 157 /* FSB 100MHz */
 158 #define BSEL_SOC_FUSE_101               0x5
 159 /* FSB 83MHz */
 160 #define BSEL_SOC_FUSE_111               0x7
 161
 162 #define SFI_MTMR_MAX_NUM                8
 163 #define SFI_MRTC_MAX                    8
 164
 165 extern void intel_scu_devices_create(void);
 166 extern void intel_scu_devices_destroy(void);
 167
 168 /* VRTC timer */
 169 #define MRST_VRTC_MAP_SZ                1024
 170 /* #define MRST_VRTC_PGOFFSET           0xc00 */
 171
 172 extern void intel_mid_rtc_init(void);
 173
 174 /* The offset for the mapping of global gpio pin to irq */
 175 #define INTEL_MID_IRQ_OFFSET            0x100
 176
 177 #endif /* _ASM_X86_INTEL_MID_H */