x86, apic: clean up ->init_apic_ldr()
[deliverable/linux.git] / arch / x86 / include / asm / mach-default / mach_apic.h
1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
3
4 #ifdef CONFIG_X86_LOCAL_APIC
5
6 #include <mach_apicdef.h>
7 #include <asm/smp.h>
8
9 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
10
11 static inline const struct cpumask *default_target_cpus(void)
12 {
13 #ifdef CONFIG_SMP
14 return cpu_online_mask;
15 #else
16 return cpumask_of(0);
17 #endif
18 }
19
20 #ifdef CONFIG_X86_64
21 #include <asm/genapic.h>
22 #define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
23 #define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
24 #define phys_pkg_id (apic->phys_pkg_id)
25 #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
26 #define send_IPI_self (apic->send_IPI_self)
27 #define wakeup_secondary_cpu (apic->wakeup_cpu)
28 extern void setup_apic_routing(void);
29 #else
30 #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
31 /*
32 * Set up the logical destination ID.
33 *
34 * Intel recommends to set DFR, LDR and TPR before enabling
35 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
36 * document number 292116). So here it goes...
37 */
38 static inline void default_init_apic_ldr(void)
39 {
40 unsigned long val;
41
42 apic_write(APIC_DFR, APIC_DFR_VALUE);
43 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
44 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
45 apic_write(APIC_LDR, val);
46 }
47
48 static inline int default_apic_id_registered(void)
49 {
50 return physid_isset(read_apic_id(), phys_cpu_present_map);
51 }
52
53 static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask)
54 {
55 return cpumask_bits(cpumask)[0];
56 }
57
58 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
59 const struct cpumask *andmask)
60 {
61 unsigned long mask1 = cpumask_bits(cpumask)[0];
62 unsigned long mask2 = cpumask_bits(andmask)[0];
63 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
64
65 return (unsigned int)(mask1 & mask2 & mask3);
66 }
67
68 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
69 {
70 return cpuid_apic >> index_msb;
71 }
72
73 static inline void setup_apic_routing(void)
74 {
75 #ifdef CONFIG_X86_IO_APIC
76 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
77 "Flat", nr_ioapics);
78 #endif
79 }
80
81 static inline int apicid_to_node(int logical_apicid)
82 {
83 #ifdef CONFIG_SMP
84 return apicid_2_node[hard_smp_processor_id()];
85 #else
86 return 0;
87 #endif
88 }
89
90 #endif
91
92 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
93 {
94 return physid_isset(apicid, bitmap);
95 }
96
97 static inline unsigned long default_check_apicid_present(int bit)
98 {
99 return physid_isset(bit, phys_cpu_present_map);
100 }
101
102 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
103 {
104 return phys_map;
105 }
106
107 static inline int multi_timer_check(int apic, int irq)
108 {
109 return 0;
110 }
111
112 /* Mapping from cpu number to logical apicid */
113 static inline int cpu_to_logical_apicid(int cpu)
114 {
115 return 1 << cpu;
116 }
117
118 static inline int cpu_present_to_apicid(int mps_cpu)
119 {
120 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
121 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
122 else
123 return BAD_APICID;
124 }
125
126 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
127 {
128 return physid_mask_of_physid(phys_apicid);
129 }
130
131 static inline void setup_portio_remap(void)
132 {
133 }
134
135 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
136 {
137 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
138 }
139
140 static inline void enable_apic_mode(void)
141 {
142 }
143 #endif /* CONFIG_X86_LOCAL_APIC */
144 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */
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