arch/x86/include/asm/mce.h

   1 #ifndef _ASM_X86_MCE_H
   2 #define _ASM_X86_MCE_H
   3
   4 #include <uapi/asm/mce.h>
   5
   6 /*
   7  * Machine Check support for x86
   8  */
   9
  10 /* MCG_CAP register defines */
  11 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  12 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  13 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  14 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  15 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  16 #define MCG_EXT_CNT_SHIFT       16
  17 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  18 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  19 #define MCG_ELOG_P              (1ULL<<26)   /* Extended error log supported */
  20 #define MCG_LMCE_P              (1ULL<<27)   /* Local machine check supported */
  21
  22 /* MCG_STATUS register defines */
  23 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  24 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  25 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  26 #define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
  27
  28 /* MCG_EXT_CTL register defines */
  29 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
  30
  31 /* MCi_STATUS register defines */
  32 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  33 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  34 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  35 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  36 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  37 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  38 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  39 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  40 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  41
  42 /* AMD-specific bits */
  43 #define MCI_STATUS_DEFERRED     (1ULL<<44)  /* declare an uncorrected error */
  44 #define MCI_STATUS_POISON       (1ULL<<43)  /* access poisonous data */
  45
  46 /*
  47  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
  48  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
  49  * errors to indicate that errors are being filtered by hardware.
  50  * We should mask out bit 12 when looking for specific signatures
  51  * of uncorrected errors - so the F bit is deliberately skipped
  52  * in this #define.
  53  */
  54 #define MCACOD            0xefff     /* MCA Error Code */
  55
  56 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  57 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
  58 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
  59 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
  60 #define MCACOD_DATA     0x0134  /* Data Load */
  61 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
  62
  63 /* MCi_MISC register defines */
  64 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  65 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  66 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  67 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  68 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  69 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  70 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  71
  72 /* CTL2 register defines */
  73 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  74 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  75
  76 #define MCJ_CTX_MASK            3
  77 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  78 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  79 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  80 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  81 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  82 #define MCJ_EXCEPTION           0x8  /* raise as exception */
  83 #define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
  84
  85 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
  86
  87 /* Software defined banks */
  88 #define MCE_EXTENDED_BANK       128
  89 #define MCE_THERMAL_BANK        (MCE_EXTENDED_BANK + 0)
  90
  91 #define MCE_LOG_LEN 32
  92 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
  93
  94 /* AMD Scalable MCA */
  95 #define MSR_AMD64_SMCA_MC0_CONFIG       0xc0002004
  96 #define MSR_AMD64_SMCA_MCx_CONFIG(x)    (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
  97
  98 /*
  99  * This structure contains all data related to the MCE log.  Also
 100  * carries a signature to make it easier to find from external
 101  * debugging tools.  Each entry is only valid when its finished flag
 102  * is set.
 103  */
 104 struct mce_log {
 105         char signature[12]; /* "MACHINECHECK" */
 106         unsigned len;       /* = MCE_LOG_LEN */
 107         unsigned next;
 108         unsigned flags;
 109         unsigned recordlen;     /* length of struct mce */
 110         struct mce entry[MCE_LOG_LEN];
 111 };
 112
 113 struct mca_config {
 114         bool dont_log_ce;
 115         bool cmci_disabled;
 116         bool lmce_disabled;
 117         bool ignore_ce;
 118         bool disabled;
 119         bool ser;
 120         bool bios_cmci_threshold;
 121         u8 banks;
 122         s8 bootlog;
 123         int tolerant;
 124         int monarch_timeout;
 125         int panic_timeout;
 126         u32 rip_msr;
 127 };
 128
 129 struct mce_vendor_flags {
 130         /*
 131          * Indicates that overflow conditions are not fatal, when set.
 132          */
 133         __u64 overflow_recov    : 1,
 134
 135         /*
 136          * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
 137          * Recovery. It indicates support for data poisoning in HW and deferred
 138          * error interrupts.
 139          */
 140               succor            : 1,
 141
 142         /*
 143          * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
 144          * the register space for each MCA bank and also increases number of
 145          * banks. Also, to accommodate the new banks and registers, the MCA
 146          * register space is moved to a new MSR range.
 147          */
 148               smca              : 1,
 149
 150               __reserved_0      : 61;
 151 };
 152 extern struct mce_vendor_flags mce_flags;
 153
 154 extern struct mca_config mca_cfg;
 155 extern void mce_register_decode_chain(struct notifier_block *nb);
 156 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 157
 158 #include <linux/percpu.h>
 159 #include <linux/atomic.h>
 160
 161 extern int mce_p5_enabled;
 162
 163 #ifdef CONFIG_X86_MCE
 164 int mcheck_init(void);
 165 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 166 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
 167 void mcheck_vendor_init_severity(void);
 168 #else
 169 static inline int mcheck_init(void) { return 0; }
 170 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 171 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
 172 static inline void mcheck_vendor_init_severity(void) {}
 173 #endif
 174
 175 #ifdef CONFIG_X86_ANCIENT_MCE
 176 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 177 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 178 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 179 #else
 180 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 181 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 182 static inline void enable_p5_mce(void) {}
 183 #endif
 184
 185 void mce_setup(struct mce *m);
 186 void mce_log(struct mce *m);
 187 DECLARE_PER_CPU(struct device *, mce_device);
 188
 189 /*
 190  * Maximum banks number.
 191  * This is the limit of the current register layout on
 192  * Intel CPUs.
 193  */
 194 #define MAX_NR_BANKS 32
 195
 196 #ifdef CONFIG_X86_MCE_INTEL
 197 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 198 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
 199 void cmci_clear(void);
 200 void cmci_reenable(void);
 201 void cmci_rediscover(void);
 202 void cmci_recheck(void);
 203 #else
 204 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 205 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
 206 static inline void cmci_clear(void) {}
 207 static inline void cmci_reenable(void) {}
 208 static inline void cmci_rediscover(void) {}
 209 static inline void cmci_recheck(void) {}
 210 #endif
 211
 212 #ifdef CONFIG_X86_MCE_AMD
 213 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 214 #else
 215 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 216 #endif
 217
 218 int mce_available(struct cpuinfo_x86 *c);
 219
 220 DECLARE_PER_CPU(unsigned, mce_exception_count);
 221 DECLARE_PER_CPU(unsigned, mce_poll_count);
 222
 223 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 224 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 225
 226 enum mcp_flags {
 227         MCP_TIMESTAMP   = BIT(0),       /* log time stamp */
 228         MCP_UC          = BIT(1),       /* log uncorrected errors */
 229         MCP_DONTLOG     = BIT(2),       /* only clear, don't log */
 230 };
 231 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 232
 233 int mce_notify_irq(void);
 234
 235 DECLARE_PER_CPU(struct mce, injectm);
 236
 237 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
 238                                     const char __user *ubuf,
 239                                     size_t usize, loff_t *off));
 240
 241 /* Disable CMCI/polling for MCA bank claimed by firmware */
 242 extern void mce_disable_bank(int bank);
 243
 244 /*
 245  * Exception handler
 246  */
 247
 248 /* Call the installed machine check handler for this CPU setup. */
 249 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 250 void do_machine_check(struct pt_regs *, long);
 251
 252 /*
 253  * Threshold handler
 254  */
 255
 256 extern void (*mce_threshold_vector)(void);
 257 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 258
 259 /* Deferred error interrupt handler */
 260 extern void (*deferred_error_int_vector)(void);
 261
 262 /*
 263  * Thermal handler
 264  */
 265
 266 void intel_init_thermal(struct cpuinfo_x86 *c);
 267
 268 void mce_log_therm_throt_event(__u64 status);
 269
 270 /* Interrupt Handler for core thermal thresholds */
 271 extern int (*platform_thermal_notify)(__u64 msr_val);
 272
 273 /* Interrupt Handler for package thermal thresholds */
 274 extern int (*platform_thermal_package_notify)(__u64 msr_val);
 275
 276 /* Callback support of rate control, return true, if
 277  * callback has rate control */
 278 extern bool (*platform_thermal_package_rate_control)(void);
 279
 280 #ifdef CONFIG_X86_THERMAL_VECTOR
 281 extern void mcheck_intel_therm_init(void);
 282 #else
 283 static inline void mcheck_intel_therm_init(void) { }
 284 #endif
 285
 286 /*
 287  * Used by APEI to report memory error via /dev/mcelog
 288  */
 289
 290 struct cper_sec_mem_err;
 291 extern void apei_mce_report_mem_error(int corrected,
 292                                       struct cper_sec_mem_err *mem_err);
 293
 294 #endif /* _ASM_X86_MCE_H */