arch/x86/include/asm/mce.h

   1 #ifndef _ASM_X86_MCE_H
   2 #define _ASM_X86_MCE_H
   3
   4 #include <linux/types.h>
   5 #include <asm/ioctls.h>
   6
   7 /*
   8  * Machine Check support for x86
   9  */
  10
  11 /* MCG_CAP register defines */
  12 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  13 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  14 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  15 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  16 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  17 #define MCG_EXT_CNT_SHIFT       16
  18 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  19 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  20
  21 /* MCG_STATUS register defines */
  22 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  23 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  24 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  25
  26 /* MCi_STATUS register defines */
  27 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  28 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  29 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  30 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  31 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  32 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  33 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  34 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  35 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  36 #define MCACOD            0xffff     /* MCA Error Code */
  37
  38 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  39 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
  40 #define MCACOD_SCRUBMSK 0xfff0
  41 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
  42 #define MCACOD_DATA     0x0134  /* Data Load */
  43 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
  44
  45 /* MCi_MISC register defines */
  46 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  47 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  48 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  49 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  50 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  51 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  52 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  53
  54 /* CTL2 register defines */
  55 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  56 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  57
  58 #define MCJ_CTX_MASK            3
  59 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  60 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  61 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  62 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  63 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  64 #define MCJ_EXCEPTION           0x8  /* raise as exception */
  65 #define MCJ_IRQ_BRAODCAST       0x10 /* do IRQ broadcasting */
  66
  67 /* Fields are zero when not available */
  68 struct mce {
  69         __u64 status;
  70         __u64 misc;
  71         __u64 addr;
  72         __u64 mcgstatus;
  73         __u64 ip;
  74         __u64 tsc;      /* cpu time stamp counter */
  75         __u64 time;     /* wall time_t when error was detected */
  76         __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
  77         __u8  inject_flags;     /* software inject flags */
  78         __u16  pad;
  79         __u32 cpuid;    /* CPUID 1 EAX */
  80         __u8  cs;               /* code segment */
  81         __u8  bank;     /* machine check bank */
  82         __u8  cpu;      /* cpu number; obsolete; use extcpu now */
  83         __u8  finished;   /* entry is valid */
  84         __u32 extcpu;   /* linux cpu number that detected the error */
  85         __u32 socketid; /* CPU socket ID */
  86         __u32 apicid;   /* CPU initial apic ID */
  87         __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
  88 };
  89
  90 /*
  91  * This structure contains all data related to the MCE log.  Also
  92  * carries a signature to make it easier to find from external
  93  * debugging tools.  Each entry is only valid when its finished flag
  94  * is set.
  95  */
  96
  97 #define MCE_LOG_LEN 32
  98
  99 struct mce_log {
 100         char signature[12]; /* "MACHINECHECK" */
 101         unsigned len;       /* = MCE_LOG_LEN */
 102         unsigned next;
 103         unsigned flags;
 104         unsigned recordlen;     /* length of struct mce */
 105         struct mce entry[MCE_LOG_LEN];
 106 };
 107
 108 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
 109
 110 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
 111
 112 #define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
 113 #define MCE_GET_LOG_LEN      _IOR('M', 2, int)
 114 #define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
 115
 116 /* Software defined banks */
 117 #define MCE_EXTENDED_BANK       128
 118 #define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
 119 #define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)
 120
 121 #ifdef __KERNEL__
 122
 123 struct mca_config {
 124         bool dont_log_ce;
 125         bool cmci_disabled;
 126         bool ignore_ce;
 127         u8 banks;
 128         s8 bootlog;
 129         int tolerant;
 130         int monarch_timeout;
 131         int panic_timeout;
 132         u32 rip_msr;
 133 };
 134
 135 extern struct mca_config mca_cfg;
 136 extern void mce_register_decode_chain(struct notifier_block *nb);
 137 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 138
 139 #include <linux/percpu.h>
 140 #include <linux/init.h>
 141 #include <linux/atomic.h>
 142
 143 extern int mce_disabled;
 144 extern int mce_p5_enabled;
 145
 146 #ifdef CONFIG_X86_MCE
 147 int mcheck_init(void);
 148 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 149 #else
 150 static inline int mcheck_init(void) { return 0; }
 151 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 152 #endif
 153
 154 #ifdef CONFIG_X86_ANCIENT_MCE
 155 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 156 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 157 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 158 #else
 159 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 160 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 161 static inline void enable_p5_mce(void) {}
 162 #endif
 163
 164 void mce_setup(struct mce *m);
 165 void mce_log(struct mce *m);
 166 DECLARE_PER_CPU(struct device *, mce_device);
 167
 168 /*
 169  * Maximum banks number.
 170  * This is the limit of the current register layout on
 171  * Intel CPUs.
 172  */
 173 #define MAX_NR_BANKS 32
 174
 175 #ifdef CONFIG_X86_MCE_INTEL
 176 extern int mce_bios_cmci_threshold;
 177 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 178 void cmci_clear(void);
 179 void cmci_reenable(void);
 180 void cmci_rediscover(int dying);
 181 void cmci_recheck(void);
 182 #else
 183 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 184 static inline void cmci_clear(void) {}
 185 static inline void cmci_reenable(void) {}
 186 static inline void cmci_rediscover(int dying) {}
 187 static inline void cmci_recheck(void) {}
 188 #endif
 189
 190 #ifdef CONFIG_X86_MCE_AMD
 191 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 192 #else
 193 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 194 #endif
 195
 196 int mce_available(struct cpuinfo_x86 *c);
 197
 198 DECLARE_PER_CPU(unsigned, mce_exception_count);
 199 DECLARE_PER_CPU(unsigned, mce_poll_count);
 200
 201 extern atomic_t mce_entry;
 202
 203 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 204 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 205
 206 enum mcp_flags {
 207         MCP_TIMESTAMP = (1 << 0),       /* log time stamp */
 208         MCP_UC = (1 << 1),              /* log uncorrected errors */
 209         MCP_DONTLOG = (1 << 2),         /* only clear, don't log */
 210 };
 211 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 212
 213 int mce_notify_irq(void);
 214 void mce_notify_process(void);
 215
 216 DECLARE_PER_CPU(struct mce, injectm);
 217
 218 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
 219                                     const char __user *ubuf,
 220                                     size_t usize, loff_t *off));
 221
 222 /*
 223  * Exception handler
 224  */
 225
 226 /* Call the installed machine check handler for this CPU setup. */
 227 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 228 void do_machine_check(struct pt_regs *, long);
 229
 230 /*
 231  * Threshold handler
 232  */
 233
 234 extern void (*mce_threshold_vector)(void);
 235 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 236
 237 /*
 238  * Thermal handler
 239  */
 240
 241 void intel_init_thermal(struct cpuinfo_x86 *c);
 242
 243 void mce_log_therm_throt_event(__u64 status);
 244
 245 /* Interrupt Handler for core thermal thresholds */
 246 extern int (*platform_thermal_notify)(__u64 msr_val);
 247
 248 #ifdef CONFIG_X86_THERMAL_VECTOR
 249 extern void mcheck_intel_therm_init(void);
 250 #else
 251 static inline void mcheck_intel_therm_init(void) { }
 252 #endif
 253
 254 /*
 255  * Used by APEI to report memory error via /dev/mcelog
 256  */
 257
 258 struct cper_sec_mem_err;
 259 extern void apei_mce_report_mem_error(int corrected,
 260                                       struct cper_sec_mem_err *mem_err);
 261
 262 #endif /* __KERNEL__ */
 263 #endif /* _ASM_X86_MCE_H */