arch/x86/include/asm/mce.h

   1 #ifndef _ASM_X86_MCE_H
   2 #define _ASM_X86_MCE_H
   3
   4 #include <linux/types.h>
   5 #include <asm/ioctls.h>
   6
   7 /*
   8  * Machine Check support for x86
   9  */
  10
  11 /* MCG_CAP register defines */
  12 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  13 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  14 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  15 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  16 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  17 #define MCG_EXT_CNT_SHIFT       16
  18 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  19 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  20
  21 /* MCG_STATUS register defines */
  22 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  23 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  24 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  25
  26 /* MCi_STATUS register defines */
  27 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  28 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  29 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  30 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  31 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  32 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  33 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  34 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  35 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  36
  37 /* MCi_MISC register defines */
  38 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  39 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  40 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  41 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  42 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  43 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  44 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  45
  46 /* CTL2 register defines */
  47 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  48 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  49
  50 #define MCJ_CTX_MASK            3
  51 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  52 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  53 #define MCJ_CTX_PROCESS         1    /* inject context: process */
  54 #define MCJ_CTX_IRQ             2    /* inject context: IRQ */
  55 #define MCJ_NMI_BROADCAST       4    /* do NMI broadcasting */
  56 #define MCJ_EXCEPTION           8    /* raise as exception */
  57
  58 /* Fields are zero when not available */
  59 struct mce {
  60         __u64 status;
  61         __u64 misc;
  62         __u64 addr;
  63         __u64 mcgstatus;
  64         __u64 ip;
  65         __u64 tsc;      /* cpu time stamp counter */
  66         __u64 time;     /* wall time_t when error was detected */
  67         __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
  68         __u8  inject_flags;     /* software inject flags */
  69         __u16  pad;
  70         __u32 cpuid;    /* CPUID 1 EAX */
  71         __u8  cs;               /* code segment */
  72         __u8  bank;     /* machine check bank */
  73         __u8  cpu;      /* cpu number; obsolete; use extcpu now */
  74         __u8  finished;   /* entry is valid */
  75         __u32 extcpu;   /* linux cpu number that detected the error */
  76         __u32 socketid; /* CPU socket ID */
  77         __u32 apicid;   /* CPU initial apic ID */
  78         __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
  79 };
  80
  81 /*
  82  * This structure contains all data related to the MCE log.  Also
  83  * carries a signature to make it easier to find from external
  84  * debugging tools.  Each entry is only valid when its finished flag
  85  * is set.
  86  */
  87
  88 #define MCE_LOG_LEN 32
  89
  90 struct mce_log {
  91         char signature[12]; /* "MACHINECHECK" */
  92         unsigned len;       /* = MCE_LOG_LEN */
  93         unsigned next;
  94         unsigned flags;
  95         unsigned recordlen;     /* length of struct mce */
  96         struct mce entry[MCE_LOG_LEN];
  97 };
  98
  99 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
 100
 101 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
 102
 103 #define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
 104 #define MCE_GET_LOG_LEN      _IOR('M', 2, int)
 105 #define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
 106
 107 /* Software defined banks */
 108 #define MCE_EXTENDED_BANK       128
 109 #define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
 110
 111 #define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
 112 #define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
 113 #define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
 114 #define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
 115 #define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
 116 #define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
 117 #define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
 118 #define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
 119
 120
 121 #ifdef __KERNEL__
 122
 123 extern void mce_register_decode_chain(struct notifier_block *nb);
 124 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 125
 126 #include <linux/percpu.h>
 127 #include <linux/init.h>
 128 #include <linux/atomic.h>
 129
 130 extern int mce_disabled;
 131 extern int mce_p5_enabled;
 132
 133 #ifdef CONFIG_X86_MCE
 134 int mcheck_init(void);
 135 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 136 #else
 137 static inline int mcheck_init(void) { return 0; }
 138 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 139 #endif
 140
 141 #ifdef CONFIG_X86_ANCIENT_MCE
 142 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 143 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 144 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 145 #else
 146 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 147 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 148 static inline void enable_p5_mce(void) {}
 149 #endif
 150
 151 void mce_setup(struct mce *m);
 152 void mce_log(struct mce *m);
 153 DECLARE_PER_CPU(struct sys_device, mce_sysdev);
 154
 155 /*
 156  * Maximum banks number.
 157  * This is the limit of the current register layout on
 158  * Intel CPUs.
 159  */
 160 #define MAX_NR_BANKS 32
 161
 162 #ifdef CONFIG_X86_MCE_INTEL
 163 extern int mce_cmci_disabled;
 164 extern int mce_ignore_ce;
 165 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 166 void cmci_clear(void);
 167 void cmci_reenable(void);
 168 void cmci_rediscover(int dying);
 169 void cmci_recheck(void);
 170 #else
 171 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 172 static inline void cmci_clear(void) {}
 173 static inline void cmci_reenable(void) {}
 174 static inline void cmci_rediscover(int dying) {}
 175 static inline void cmci_recheck(void) {}
 176 #endif
 177
 178 #ifdef CONFIG_X86_MCE_AMD
 179 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 180 #else
 181 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 182 #endif
 183
 184 int mce_available(struct cpuinfo_x86 *c);
 185
 186 DECLARE_PER_CPU(unsigned, mce_exception_count);
 187 DECLARE_PER_CPU(unsigned, mce_poll_count);
 188
 189 extern atomic_t mce_entry;
 190
 191 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 192 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 193
 194 enum mcp_flags {
 195         MCP_TIMESTAMP = (1 << 0),       /* log time stamp */
 196         MCP_UC = (1 << 1),              /* log uncorrected errors */
 197         MCP_DONTLOG = (1 << 2),         /* only clear, don't log */
 198 };
 199 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 200
 201 int mce_notify_irq(void);
 202 void mce_notify_process(void);
 203
 204 DECLARE_PER_CPU(struct mce, injectm);
 205
 206 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
 207                                     const char __user *ubuf,
 208                                     size_t usize, loff_t *off));
 209
 210 /*
 211  * Exception handler
 212  */
 213
 214 /* Call the installed machine check handler for this CPU setup. */
 215 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 216 void do_machine_check(struct pt_regs *, long);
 217
 218 /*
 219  * Threshold handler
 220  */
 221
 222 extern void (*mce_threshold_vector)(void);
 223 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 224
 225 /*
 226  * Thermal handler
 227  */
 228
 229 void intel_init_thermal(struct cpuinfo_x86 *c);
 230
 231 void mce_log_therm_throt_event(__u64 status);
 232
 233 /* Interrupt Handler for core thermal thresholds */
 234 extern int (*platform_thermal_notify)(__u64 msr_val);
 235
 236 #ifdef CONFIG_X86_THERMAL_VECTOR
 237 extern void mcheck_intel_therm_init(void);
 238 #else
 239 static inline void mcheck_intel_therm_init(void) { }
 240 #endif
 241
 242 /*
 243  * Used by APEI to report memory error via /dev/mcelog
 244  */
 245
 246 struct cper_sec_mem_err;
 247 extern void apei_mce_report_mem_error(int corrected,
 248                                       struct cper_sec_mem_err *mem_err);
 249
 250 #endif /* __KERNEL__ */
 251 #endif /* _ASM_X86_MCE_H */