4 #include <asm/msr-index.h>
7 # include <linux/types.h>
14 #include <asm/errno.h>
16 static inline unsigned long long native_read_tscp(unsigned int *aux
)
18 unsigned long low
, high
;
19 asm volatile(".byte 0x0f,0x01,0xf9"
20 : "=a" (low
), "=d" (high
), "=c" (*aux
));
21 return low
| ((u64
)high
<< 32);
25 * i386 calling convention returns 64-bit value in edx:eax, while
26 * x86_64 returns at rax. Also, the "A" constraint does not really
27 * mean rdx:rax in x86_64, so we need specialized behaviour for each
31 #define DECLARE_ARGS(val, low, high) unsigned low, high
32 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
33 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
34 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
36 #define DECLARE_ARGS(val, low, high) unsigned long long val
37 #define EAX_EDX_VAL(val, low, high) (val)
38 #define EAX_EDX_ARGS(val, low, high) "A" (val)
39 #define EAX_EDX_RET(val, low, high) "=A" (val)
42 static inline unsigned long long native_read_msr(unsigned int msr
)
44 DECLARE_ARGS(val
, low
, high
);
46 asm volatile("rdmsr" : EAX_EDX_RET(val
, low
, high
) : "c" (msr
));
47 return EAX_EDX_VAL(val
, low
, high
);
50 static inline unsigned long long native_read_msr_safe(unsigned int msr
,
53 DECLARE_ARGS(val
, low
, high
);
55 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
57 ".section .fixup,\"ax\"\n\t"
58 "3: mov %[fault],%[err] ; jmp 1b\n\t"
61 : [err
] "=r" (*err
), EAX_EDX_RET(val
, low
, high
)
62 : "c" (msr
), [fault
] "i" (-EFAULT
));
63 return EAX_EDX_VAL(val
, low
, high
);
66 static inline unsigned long long native_read_msr_amd_safe(unsigned int msr
,
69 DECLARE_ARGS(val
, low
, high
);
71 asm volatile("2: rdmsr ; xor %0,%0\n"
73 ".section .fixup,\"ax\"\n\t"
74 "3: mov %3,%0 ; jmp 1b\n\t"
77 : "=r" (*err
), EAX_EDX_RET(val
, low
, high
)
78 : "c" (msr
), "D" (0x9c5a203a), "i" (-EFAULT
));
79 return EAX_EDX_VAL(val
, low
, high
);
82 static inline void native_write_msr(unsigned int msr
,
83 unsigned low
, unsigned high
)
85 asm volatile("wrmsr" : : "c" (msr
), "a"(low
), "d" (high
) : "memory");
88 static inline int native_write_msr_safe(unsigned int msr
,
89 unsigned low
, unsigned high
)
92 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
94 ".section .fixup,\"ax\"\n\t"
95 "3: mov %[fault],%[err] ; jmp 1b\n\t"
99 : "c" (msr
), "0" (low
), "d" (high
),
100 [fault
] "i" (-EFAULT
)
105 extern unsigned long long native_read_tsc(void);
107 static __always_inline
unsigned long long __native_read_tsc(void)
109 DECLARE_ARGS(val
, low
, high
);
111 asm volatile("rdtsc" : EAX_EDX_RET(val
, low
, high
));
113 return EAX_EDX_VAL(val
, low
, high
);
116 static inline unsigned long long native_read_pmc(int counter
)
118 DECLARE_ARGS(val
, low
, high
);
120 asm volatile("rdpmc" : EAX_EDX_RET(val
, low
, high
) : "c" (counter
));
121 return EAX_EDX_VAL(val
, low
, high
);
124 #ifdef CONFIG_PARAVIRT
125 #include <asm/paravirt.h>
127 #include <linux/errno.h>
129 * Access to machine-specific registers (available on 586 and better only)
130 * Note: the rd* operations modify the parameters directly (without using
131 * pointer indirection), this allows gcc to optimize better
134 #define rdmsr(msr, val1, val2) \
136 u64 __val = native_read_msr((msr)); \
137 (val1) = (u32)__val; \
138 (val2) = (u32)(__val >> 32); \
141 static inline void wrmsr(unsigned msr
, unsigned low
, unsigned high
)
143 native_write_msr(msr
, low
, high
);
146 #define rdmsrl(msr, val) \
147 ((val) = native_read_msr((msr)))
149 #define wrmsrl(msr, val) \
150 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
152 /* wrmsr with exception handling */
153 static inline int wrmsr_safe(unsigned msr
, unsigned low
, unsigned high
)
155 return native_write_msr_safe(msr
, low
, high
);
158 /* rdmsr with exception handling */
159 #define rdmsr_safe(msr, p1, p2) \
162 u64 __val = native_read_msr_safe((msr), &__err); \
163 (*p1) = (u32)__val; \
164 (*p2) = (u32)(__val >> 32); \
168 static inline int rdmsrl_safe(unsigned msr
, unsigned long long *p
)
172 *p
= native_read_msr_safe(msr
, &err
);
175 static inline int rdmsrl_amd_safe(unsigned msr
, unsigned long long *p
)
179 *p
= native_read_msr_amd_safe(msr
, &err
);
183 #define rdtscl(low) \
184 ((low) = (u32)native_read_tsc())
186 #define rdtscll(val) \
187 ((val) = native_read_tsc())
189 #define rdpmc(counter, low, high) \
191 u64 _l = native_read_pmc((counter)); \
193 (high) = (u32)(_l >> 32); \
196 #define rdtscp(low, high, aux) \
198 unsigned long long _val = native_read_tscp(&(aux)); \
200 (high) = (u32)(_val >> 32); \
203 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
205 #endif /* !CONFIG_PARAVIRT */
208 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \
211 #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
213 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
216 int rdmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32
*l
, u32
*h
);
217 int wrmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
);
218 int rdmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u32
*l
, u32
*h
);
219 int wrmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
);
220 #else /* CONFIG_SMP */
221 static inline int rdmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32
*l
, u32
*h
)
223 rdmsr(msr_no
, *l
, *h
);
226 static inline int wrmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
)
231 static inline int rdmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
,
234 return rdmsr_safe(msr_no
, l
, h
);
236 static inline int wrmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
)
238 return wrmsr_safe(msr_no
, l
, h
);
240 #endif /* CONFIG_SMP */
241 #endif /* __ASSEMBLY__ */
242 #endif /* __KERNEL__ */
245 #endif /* _ASM_X86_MSR_H */
This page took 0.03565 seconds and 6 git commands to generate.