x86: Move tsc_calibration to x86_init_ops
[deliverable/linux.git] / arch / x86 / include / asm / paravirt.h
1 #ifndef _ASM_X86_PARAVIRT_H
2 #define _ASM_X86_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/pgtable_types.h>
8 #include <asm/asm.h>
9
10 #include <asm/paravirt_types.h>
11
12 #ifndef __ASSEMBLY__
13 #include <linux/types.h>
14 #include <linux/cpumask.h>
15
16 static inline int paravirt_enabled(void)
17 {
18 return pv_info.paravirt_enabled;
19 }
20
21 static inline void load_sp0(struct tss_struct *tss,
22 struct thread_struct *thread)
23 {
24 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
25 }
26
27 static inline unsigned long get_wallclock(void)
28 {
29 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
30 }
31
32 static inline int set_wallclock(unsigned long nowtime)
33 {
34 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
35 }
36
37 /* The paravirtualized CPUID instruction. */
38 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
39 unsigned int *ecx, unsigned int *edx)
40 {
41 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
42 }
43
44 /*
45 * These special macros can be used to get or set a debugging register
46 */
47 static inline unsigned long paravirt_get_debugreg(int reg)
48 {
49 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
50 }
51 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
52 static inline void set_debugreg(unsigned long val, int reg)
53 {
54 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
55 }
56
57 static inline void clts(void)
58 {
59 PVOP_VCALL0(pv_cpu_ops.clts);
60 }
61
62 static inline unsigned long read_cr0(void)
63 {
64 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
65 }
66
67 static inline void write_cr0(unsigned long x)
68 {
69 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
70 }
71
72 static inline unsigned long read_cr2(void)
73 {
74 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
75 }
76
77 static inline void write_cr2(unsigned long x)
78 {
79 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
80 }
81
82 static inline unsigned long read_cr3(void)
83 {
84 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
85 }
86
87 static inline void write_cr3(unsigned long x)
88 {
89 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
90 }
91
92 static inline unsigned long read_cr4(void)
93 {
94 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
95 }
96 static inline unsigned long read_cr4_safe(void)
97 {
98 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
99 }
100
101 static inline void write_cr4(unsigned long x)
102 {
103 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
104 }
105
106 #ifdef CONFIG_X86_64
107 static inline unsigned long read_cr8(void)
108 {
109 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
110 }
111
112 static inline void write_cr8(unsigned long x)
113 {
114 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
115 }
116 #endif
117
118 static inline void raw_safe_halt(void)
119 {
120 PVOP_VCALL0(pv_irq_ops.safe_halt);
121 }
122
123 static inline void halt(void)
124 {
125 PVOP_VCALL0(pv_irq_ops.safe_halt);
126 }
127
128 static inline void wbinvd(void)
129 {
130 PVOP_VCALL0(pv_cpu_ops.wbinvd);
131 }
132
133 #define get_kernel_rpl() (pv_info.kernel_rpl)
134
135 static inline u64 paravirt_read_msr(unsigned msr, int *err)
136 {
137 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
138 }
139 static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
140 {
141 return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
142 }
143 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
144 {
145 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
146 }
147
148 /* These should all do BUG_ON(_err), but our headers are too tangled. */
149 #define rdmsr(msr, val1, val2) \
150 do { \
151 int _err; \
152 u64 _l = paravirt_read_msr(msr, &_err); \
153 val1 = (u32)_l; \
154 val2 = _l >> 32; \
155 } while (0)
156
157 #define wrmsr(msr, val1, val2) \
158 do { \
159 paravirt_write_msr(msr, val1, val2); \
160 } while (0)
161
162 #define rdmsrl(msr, val) \
163 do { \
164 int _err; \
165 val = paravirt_read_msr(msr, &_err); \
166 } while (0)
167
168 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
169 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
170
171 /* rdmsr with exception handling */
172 #define rdmsr_safe(msr, a, b) \
173 ({ \
174 int _err; \
175 u64 _l = paravirt_read_msr(msr, &_err); \
176 (*a) = (u32)_l; \
177 (*b) = _l >> 32; \
178 _err; \
179 })
180
181 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
182 {
183 int err;
184
185 *p = paravirt_read_msr(msr, &err);
186 return err;
187 }
188 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
189 {
190 int err;
191
192 *p = paravirt_read_msr_amd(msr, &err);
193 return err;
194 }
195
196 static inline u64 paravirt_read_tsc(void)
197 {
198 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
199 }
200
201 #define rdtscl(low) \
202 do { \
203 u64 _l = paravirt_read_tsc(); \
204 low = (int)_l; \
205 } while (0)
206
207 #define rdtscll(val) (val = paravirt_read_tsc())
208
209 static inline unsigned long long paravirt_sched_clock(void)
210 {
211 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
212 }
213
214 static inline unsigned long long paravirt_read_pmc(int counter)
215 {
216 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
217 }
218
219 #define rdpmc(counter, low, high) \
220 do { \
221 u64 _l = paravirt_read_pmc(counter); \
222 low = (u32)_l; \
223 high = _l >> 32; \
224 } while (0)
225
226 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
227 {
228 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
229 }
230
231 #define rdtscp(low, high, aux) \
232 do { \
233 int __aux; \
234 unsigned long __val = paravirt_rdtscp(&__aux); \
235 (low) = (u32)__val; \
236 (high) = (u32)(__val >> 32); \
237 (aux) = __aux; \
238 } while (0)
239
240 #define rdtscpll(val, aux) \
241 do { \
242 unsigned long __aux; \
243 val = paravirt_rdtscp(&__aux); \
244 (aux) = __aux; \
245 } while (0)
246
247 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
248 {
249 PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
250 }
251
252 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
253 {
254 PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
255 }
256
257 static inline void load_TR_desc(void)
258 {
259 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
260 }
261 static inline void load_gdt(const struct desc_ptr *dtr)
262 {
263 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
264 }
265 static inline void load_idt(const struct desc_ptr *dtr)
266 {
267 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
268 }
269 static inline void set_ldt(const void *addr, unsigned entries)
270 {
271 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
272 }
273 static inline void store_gdt(struct desc_ptr *dtr)
274 {
275 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
276 }
277 static inline void store_idt(struct desc_ptr *dtr)
278 {
279 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
280 }
281 static inline unsigned long paravirt_store_tr(void)
282 {
283 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
284 }
285 #define store_tr(tr) ((tr) = paravirt_store_tr())
286 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
287 {
288 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
289 }
290
291 #ifdef CONFIG_X86_64
292 static inline void load_gs_index(unsigned int gs)
293 {
294 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
295 }
296 #endif
297
298 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
299 const void *desc)
300 {
301 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
302 }
303
304 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
305 void *desc, int type)
306 {
307 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
308 }
309
310 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
311 {
312 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
313 }
314 static inline void set_iopl_mask(unsigned mask)
315 {
316 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
317 }
318
319 /* The paravirtualized I/O functions */
320 static inline void slow_down_io(void)
321 {
322 pv_cpu_ops.io_delay();
323 #ifdef REALLY_SLOW_IO
324 pv_cpu_ops.io_delay();
325 pv_cpu_ops.io_delay();
326 pv_cpu_ops.io_delay();
327 #endif
328 }
329
330 #ifdef CONFIG_SMP
331 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
332 unsigned long start_esp)
333 {
334 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
335 phys_apicid, start_eip, start_esp);
336 }
337 #endif
338
339 static inline void paravirt_activate_mm(struct mm_struct *prev,
340 struct mm_struct *next)
341 {
342 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
343 }
344
345 static inline void arch_dup_mmap(struct mm_struct *oldmm,
346 struct mm_struct *mm)
347 {
348 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
349 }
350
351 static inline void arch_exit_mmap(struct mm_struct *mm)
352 {
353 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
354 }
355
356 static inline void __flush_tlb(void)
357 {
358 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
359 }
360 static inline void __flush_tlb_global(void)
361 {
362 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
363 }
364 static inline void __flush_tlb_single(unsigned long addr)
365 {
366 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
367 }
368
369 static inline void flush_tlb_others(const struct cpumask *cpumask,
370 struct mm_struct *mm,
371 unsigned long va)
372 {
373 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, cpumask, mm, va);
374 }
375
376 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
377 {
378 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
379 }
380
381 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
382 {
383 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
384 }
385
386 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
387 {
388 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
389 }
390 static inline void paravirt_release_pte(unsigned long pfn)
391 {
392 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
393 }
394
395 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
396 {
397 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
398 }
399
400 static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
401 unsigned long start, unsigned long count)
402 {
403 PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
404 }
405 static inline void paravirt_release_pmd(unsigned long pfn)
406 {
407 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
408 }
409
410 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
411 {
412 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
413 }
414 static inline void paravirt_release_pud(unsigned long pfn)
415 {
416 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
417 }
418
419 #ifdef CONFIG_HIGHPTE
420 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
421 {
422 unsigned long ret;
423 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
424 return (void *)ret;
425 }
426 #endif
427
428 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
429 pte_t *ptep)
430 {
431 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
432 }
433
434 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
435 pte_t *ptep)
436 {
437 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
438 }
439
440 static inline pte_t __pte(pteval_t val)
441 {
442 pteval_t ret;
443
444 if (sizeof(pteval_t) > sizeof(long))
445 ret = PVOP_CALLEE2(pteval_t,
446 pv_mmu_ops.make_pte,
447 val, (u64)val >> 32);
448 else
449 ret = PVOP_CALLEE1(pteval_t,
450 pv_mmu_ops.make_pte,
451 val);
452
453 return (pte_t) { .pte = ret };
454 }
455
456 static inline pteval_t pte_val(pte_t pte)
457 {
458 pteval_t ret;
459
460 if (sizeof(pteval_t) > sizeof(long))
461 ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val,
462 pte.pte, (u64)pte.pte >> 32);
463 else
464 ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val,
465 pte.pte);
466
467 return ret;
468 }
469
470 static inline pgd_t __pgd(pgdval_t val)
471 {
472 pgdval_t ret;
473
474 if (sizeof(pgdval_t) > sizeof(long))
475 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd,
476 val, (u64)val >> 32);
477 else
478 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd,
479 val);
480
481 return (pgd_t) { ret };
482 }
483
484 static inline pgdval_t pgd_val(pgd_t pgd)
485 {
486 pgdval_t ret;
487
488 if (sizeof(pgdval_t) > sizeof(long))
489 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val,
490 pgd.pgd, (u64)pgd.pgd >> 32);
491 else
492 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val,
493 pgd.pgd);
494
495 return ret;
496 }
497
498 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
499 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
500 pte_t *ptep)
501 {
502 pteval_t ret;
503
504 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
505 mm, addr, ptep);
506
507 return (pte_t) { .pte = ret };
508 }
509
510 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
511 pte_t *ptep, pte_t pte)
512 {
513 if (sizeof(pteval_t) > sizeof(long))
514 /* 5 arg words */
515 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
516 else
517 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
518 mm, addr, ptep, pte.pte);
519 }
520
521 static inline void set_pte(pte_t *ptep, pte_t pte)
522 {
523 if (sizeof(pteval_t) > sizeof(long))
524 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
525 pte.pte, (u64)pte.pte >> 32);
526 else
527 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
528 pte.pte);
529 }
530
531 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
532 pte_t *ptep, pte_t pte)
533 {
534 if (sizeof(pteval_t) > sizeof(long))
535 /* 5 arg words */
536 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
537 else
538 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
539 }
540
541 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
542 {
543 pmdval_t val = native_pmd_val(pmd);
544
545 if (sizeof(pmdval_t) > sizeof(long))
546 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
547 else
548 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
549 }
550
551 #if PAGETABLE_LEVELS >= 3
552 static inline pmd_t __pmd(pmdval_t val)
553 {
554 pmdval_t ret;
555
556 if (sizeof(pmdval_t) > sizeof(long))
557 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd,
558 val, (u64)val >> 32);
559 else
560 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd,
561 val);
562
563 return (pmd_t) { ret };
564 }
565
566 static inline pmdval_t pmd_val(pmd_t pmd)
567 {
568 pmdval_t ret;
569
570 if (sizeof(pmdval_t) > sizeof(long))
571 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val,
572 pmd.pmd, (u64)pmd.pmd >> 32);
573 else
574 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val,
575 pmd.pmd);
576
577 return ret;
578 }
579
580 static inline void set_pud(pud_t *pudp, pud_t pud)
581 {
582 pudval_t val = native_pud_val(pud);
583
584 if (sizeof(pudval_t) > sizeof(long))
585 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
586 val, (u64)val >> 32);
587 else
588 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
589 val);
590 }
591 #if PAGETABLE_LEVELS == 4
592 static inline pud_t __pud(pudval_t val)
593 {
594 pudval_t ret;
595
596 if (sizeof(pudval_t) > sizeof(long))
597 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud,
598 val, (u64)val >> 32);
599 else
600 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud,
601 val);
602
603 return (pud_t) { ret };
604 }
605
606 static inline pudval_t pud_val(pud_t pud)
607 {
608 pudval_t ret;
609
610 if (sizeof(pudval_t) > sizeof(long))
611 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val,
612 pud.pud, (u64)pud.pud >> 32);
613 else
614 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val,
615 pud.pud);
616
617 return ret;
618 }
619
620 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
621 {
622 pgdval_t val = native_pgd_val(pgd);
623
624 if (sizeof(pgdval_t) > sizeof(long))
625 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
626 val, (u64)val >> 32);
627 else
628 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
629 val);
630 }
631
632 static inline void pgd_clear(pgd_t *pgdp)
633 {
634 set_pgd(pgdp, __pgd(0));
635 }
636
637 static inline void pud_clear(pud_t *pudp)
638 {
639 set_pud(pudp, __pud(0));
640 }
641
642 #endif /* PAGETABLE_LEVELS == 4 */
643
644 #endif /* PAGETABLE_LEVELS >= 3 */
645
646 #ifdef CONFIG_X86_PAE
647 /* Special-case pte-setting operations for PAE, which can't update a
648 64-bit pte atomically */
649 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
650 {
651 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
652 pte.pte, pte.pte >> 32);
653 }
654
655 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
656 pte_t *ptep)
657 {
658 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
659 }
660
661 static inline void pmd_clear(pmd_t *pmdp)
662 {
663 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
664 }
665 #else /* !CONFIG_X86_PAE */
666 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
667 {
668 set_pte(ptep, pte);
669 }
670
671 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
672 pte_t *ptep)
673 {
674 set_pte_at(mm, addr, ptep, __pte(0));
675 }
676
677 static inline void pmd_clear(pmd_t *pmdp)
678 {
679 set_pmd(pmdp, __pmd(0));
680 }
681 #endif /* CONFIG_X86_PAE */
682
683 #define __HAVE_ARCH_START_CONTEXT_SWITCH
684 static inline void arch_start_context_switch(struct task_struct *prev)
685 {
686 PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev);
687 }
688
689 static inline void arch_end_context_switch(struct task_struct *next)
690 {
691 PVOP_VCALL1(pv_cpu_ops.end_context_switch, next);
692 }
693
694 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
695 static inline void arch_enter_lazy_mmu_mode(void)
696 {
697 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
698 }
699
700 static inline void arch_leave_lazy_mmu_mode(void)
701 {
702 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
703 }
704
705 void arch_flush_lazy_mmu_mode(void);
706
707 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
708 phys_addr_t phys, pgprot_t flags)
709 {
710 pv_mmu_ops.set_fixmap(idx, phys, flags);
711 }
712
713 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
714
715 static inline int __raw_spin_is_locked(struct raw_spinlock *lock)
716 {
717 return PVOP_CALL1(int, pv_lock_ops.spin_is_locked, lock);
718 }
719
720 static inline int __raw_spin_is_contended(struct raw_spinlock *lock)
721 {
722 return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock);
723 }
724 #define __raw_spin_is_contended __raw_spin_is_contended
725
726 static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
727 {
728 PVOP_VCALL1(pv_lock_ops.spin_lock, lock);
729 }
730
731 static __always_inline void __raw_spin_lock_flags(struct raw_spinlock *lock,
732 unsigned long flags)
733 {
734 PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags);
735 }
736
737 static __always_inline int __raw_spin_trylock(struct raw_spinlock *lock)
738 {
739 return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock);
740 }
741
742 static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
743 {
744 PVOP_VCALL1(pv_lock_ops.spin_unlock, lock);
745 }
746
747 #endif
748
749 #ifdef CONFIG_X86_32
750 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
751 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
752
753 /* save and restore all caller-save registers, except return value */
754 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
755 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
756
757 #define PV_FLAGS_ARG "0"
758 #define PV_EXTRA_CLOBBERS
759 #define PV_VEXTRA_CLOBBERS
760 #else
761 /* save and restore all caller-save registers, except return value */
762 #define PV_SAVE_ALL_CALLER_REGS \
763 "push %rcx;" \
764 "push %rdx;" \
765 "push %rsi;" \
766 "push %rdi;" \
767 "push %r8;" \
768 "push %r9;" \
769 "push %r10;" \
770 "push %r11;"
771 #define PV_RESTORE_ALL_CALLER_REGS \
772 "pop %r11;" \
773 "pop %r10;" \
774 "pop %r9;" \
775 "pop %r8;" \
776 "pop %rdi;" \
777 "pop %rsi;" \
778 "pop %rdx;" \
779 "pop %rcx;"
780
781 /* We save some registers, but all of them, that's too much. We clobber all
782 * caller saved registers but the argument parameter */
783 #define PV_SAVE_REGS "pushq %%rdi;"
784 #define PV_RESTORE_REGS "popq %%rdi;"
785 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
786 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
787 #define PV_FLAGS_ARG "D"
788 #endif
789
790 /*
791 * Generate a thunk around a function which saves all caller-save
792 * registers except for the return value. This allows C functions to
793 * be called from assembler code where fewer than normal registers are
794 * available. It may also help code generation around calls from C
795 * code if the common case doesn't use many registers.
796 *
797 * When a callee is wrapped in a thunk, the caller can assume that all
798 * arg regs and all scratch registers are preserved across the
799 * call. The return value in rax/eax will not be saved, even for void
800 * functions.
801 */
802 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
803 extern typeof(func) __raw_callee_save_##func; \
804 static void *__##func##__ __used = func; \
805 \
806 asm(".pushsection .text;" \
807 "__raw_callee_save_" #func ": " \
808 PV_SAVE_ALL_CALLER_REGS \
809 "call " #func ";" \
810 PV_RESTORE_ALL_CALLER_REGS \
811 "ret;" \
812 ".popsection")
813
814 /* Get a reference to a callee-save function */
815 #define PV_CALLEE_SAVE(func) \
816 ((struct paravirt_callee_save) { __raw_callee_save_##func })
817
818 /* Promise that "func" already uses the right calling convention */
819 #define __PV_IS_CALLEE_SAVE(func) \
820 ((struct paravirt_callee_save) { func })
821
822 static inline unsigned long __raw_local_save_flags(void)
823 {
824 unsigned long f;
825
826 asm volatile(paravirt_alt(PARAVIRT_CALL)
827 : "=a"(f)
828 : paravirt_type(pv_irq_ops.save_fl),
829 paravirt_clobber(CLBR_EAX)
830 : "memory", "cc");
831 return f;
832 }
833
834 static inline void raw_local_irq_restore(unsigned long f)
835 {
836 asm volatile(paravirt_alt(PARAVIRT_CALL)
837 : "=a"(f)
838 : PV_FLAGS_ARG(f),
839 paravirt_type(pv_irq_ops.restore_fl),
840 paravirt_clobber(CLBR_EAX)
841 : "memory", "cc");
842 }
843
844 static inline void raw_local_irq_disable(void)
845 {
846 asm volatile(paravirt_alt(PARAVIRT_CALL)
847 :
848 : paravirt_type(pv_irq_ops.irq_disable),
849 paravirt_clobber(CLBR_EAX)
850 : "memory", "eax", "cc");
851 }
852
853 static inline void raw_local_irq_enable(void)
854 {
855 asm volatile(paravirt_alt(PARAVIRT_CALL)
856 :
857 : paravirt_type(pv_irq_ops.irq_enable),
858 paravirt_clobber(CLBR_EAX)
859 : "memory", "eax", "cc");
860 }
861
862 static inline unsigned long __raw_local_irq_save(void)
863 {
864 unsigned long f;
865
866 f = __raw_local_save_flags();
867 raw_local_irq_disable();
868 return f;
869 }
870
871
872 /* Make sure as little as possible of this mess escapes. */
873 #undef PARAVIRT_CALL
874 #undef __PVOP_CALL
875 #undef __PVOP_VCALL
876 #undef PVOP_VCALL0
877 #undef PVOP_CALL0
878 #undef PVOP_VCALL1
879 #undef PVOP_CALL1
880 #undef PVOP_VCALL2
881 #undef PVOP_CALL2
882 #undef PVOP_VCALL3
883 #undef PVOP_CALL3
884 #undef PVOP_VCALL4
885 #undef PVOP_CALL4
886
887 extern void default_banner(void);
888
889 #else /* __ASSEMBLY__ */
890
891 #define _PVSITE(ptype, clobbers, ops, word, algn) \
892 771:; \
893 ops; \
894 772:; \
895 .pushsection .parainstructions,"a"; \
896 .align algn; \
897 word 771b; \
898 .byte ptype; \
899 .byte 772b-771b; \
900 .short clobbers; \
901 .popsection
902
903
904 #define COND_PUSH(set, mask, reg) \
905 .if ((~(set)) & mask); push %reg; .endif
906 #define COND_POP(set, mask, reg) \
907 .if ((~(set)) & mask); pop %reg; .endif
908
909 #ifdef CONFIG_X86_64
910
911 #define PV_SAVE_REGS(set) \
912 COND_PUSH(set, CLBR_RAX, rax); \
913 COND_PUSH(set, CLBR_RCX, rcx); \
914 COND_PUSH(set, CLBR_RDX, rdx); \
915 COND_PUSH(set, CLBR_RSI, rsi); \
916 COND_PUSH(set, CLBR_RDI, rdi); \
917 COND_PUSH(set, CLBR_R8, r8); \
918 COND_PUSH(set, CLBR_R9, r9); \
919 COND_PUSH(set, CLBR_R10, r10); \
920 COND_PUSH(set, CLBR_R11, r11)
921 #define PV_RESTORE_REGS(set) \
922 COND_POP(set, CLBR_R11, r11); \
923 COND_POP(set, CLBR_R10, r10); \
924 COND_POP(set, CLBR_R9, r9); \
925 COND_POP(set, CLBR_R8, r8); \
926 COND_POP(set, CLBR_RDI, rdi); \
927 COND_POP(set, CLBR_RSI, rsi); \
928 COND_POP(set, CLBR_RDX, rdx); \
929 COND_POP(set, CLBR_RCX, rcx); \
930 COND_POP(set, CLBR_RAX, rax)
931
932 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
933 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
934 #define PARA_INDIRECT(addr) *addr(%rip)
935 #else
936 #define PV_SAVE_REGS(set) \
937 COND_PUSH(set, CLBR_EAX, eax); \
938 COND_PUSH(set, CLBR_EDI, edi); \
939 COND_PUSH(set, CLBR_ECX, ecx); \
940 COND_PUSH(set, CLBR_EDX, edx)
941 #define PV_RESTORE_REGS(set) \
942 COND_POP(set, CLBR_EDX, edx); \
943 COND_POP(set, CLBR_ECX, ecx); \
944 COND_POP(set, CLBR_EDI, edi); \
945 COND_POP(set, CLBR_EAX, eax)
946
947 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
948 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
949 #define PARA_INDIRECT(addr) *%cs:addr
950 #endif
951
952 #define INTERRUPT_RETURN \
953 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
954 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
955
956 #define DISABLE_INTERRUPTS(clobbers) \
957 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
958 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
959 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
960 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
961
962 #define ENABLE_INTERRUPTS(clobbers) \
963 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
964 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
965 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
966 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
967
968 #define USERGS_SYSRET32 \
969 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \
970 CLBR_NONE, \
971 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32))
972
973 #ifdef CONFIG_X86_32
974 #define GET_CR0_INTO_EAX \
975 push %ecx; push %edx; \
976 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
977 pop %edx; pop %ecx
978
979 #define ENABLE_INTERRUPTS_SYSEXIT \
980 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
981 CLBR_NONE, \
982 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
983
984
985 #else /* !CONFIG_X86_32 */
986
987 /*
988 * If swapgs is used while the userspace stack is still current,
989 * there's no way to call a pvop. The PV replacement *must* be
990 * inlined, or the swapgs instruction must be trapped and emulated.
991 */
992 #define SWAPGS_UNSAFE_STACK \
993 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
994 swapgs)
995
996 /*
997 * Note: swapgs is very special, and in practise is either going to be
998 * implemented with a single "swapgs" instruction or something very
999 * special. Either way, we don't need to save any registers for
1000 * it.
1001 */
1002 #define SWAPGS \
1003 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1004 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \
1005 )
1006
1007 #define GET_CR2_INTO_RCX \
1008 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \
1009 movq %rax, %rcx; \
1010 xorq %rax, %rax;
1011
1012 #define PARAVIRT_ADJUST_EXCEPTION_FRAME \
1013 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
1014 CLBR_NONE, \
1015 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame))
1016
1017 #define USERGS_SYSRET64 \
1018 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
1019 CLBR_NONE, \
1020 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
1021
1022 #define ENABLE_INTERRUPTS_SYSEXIT32 \
1023 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1024 CLBR_NONE, \
1025 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1026 #endif /* CONFIG_X86_32 */
1027
1028 #endif /* __ASSEMBLY__ */
1029 #else /* CONFIG_PARAVIRT */
1030 # define default_banner x86_init_noop
1031 #endif /* !CONFIG_PARAVIRT */
1032 #endif /* _ASM_X86_PARAVIRT_H */
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