2 * Low-Level PCI Access for i386 machines.
4 * (c) 1999 Martin Mares <mj@ucw.cz>
10 #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
12 #define DBG(fmt, ...) \
15 printk(fmt, ##__VA_ARGS__); \
19 #define PCI_PROBE_BIOS 0x0001
20 #define PCI_PROBE_CONF1 0x0002
21 #define PCI_PROBE_CONF2 0x0004
22 #define PCI_PROBE_MMCONF 0x0008
23 #define PCI_PROBE_MASK 0x000f
24 #define PCI_PROBE_NOEARLY 0x0010
26 #define PCI_NO_CHECKS 0x0400
27 #define PCI_USE_PIRQ_MASK 0x0800
28 #define PCI_ASSIGN_ROMS 0x1000
29 #define PCI_BIOS_IRQ_SCAN 0x2000
30 #define PCI_ASSIGN_ALL_BUSSES 0x4000
31 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
32 #define PCI_USE__CRS 0x10000
33 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
34 #define PCI_HAS_IO_ECS 0x40000
35 #define PCI_NOASSIGN_ROMS 0x80000
36 #define PCI_ROOT_NO_CRS 0x100000
37 #define PCI_NOASSIGN_BARS 0x200000
39 extern unsigned int pci_probe
;
40 extern unsigned long pirq_table_addr
;
42 enum pci_bf_sort_state
{
51 void pcibios_resource_survey(void);
52 void pcibios_set_cache_line_size(void);
56 extern int pcibios_last_bus
;
57 extern struct pci_bus
*pci_root_bus
;
58 extern struct pci_ops pci_root_ops
;
60 void pcibios_scan_specific_bus(int busn
);
65 u8 bus
, devfn
; /* Bus, device and function */
67 u8 link
; /* IRQ line ID, chipset dependent,
69 u16 bitmap
; /* Available IRQs */
70 } __attribute__((packed
)) irq
[4];
71 u8 slot
; /* Slot number, 0=onboard */
73 } __attribute__((packed
));
75 struct irq_routing_table
{
76 u32 signature
; /* PIRQ_SIGNATURE should be here */
77 u16 version
; /* PIRQ_VERSION */
78 u16 size
; /* Table size in bytes */
79 u8 rtr_bus
, rtr_devfn
; /* Where the interrupt router lies */
80 u16 exclusive_irqs
; /* IRQs devoted exclusively to
82 u16 rtr_vendor
, rtr_device
; /* Vendor and device ID of
84 u32 miniport_data
; /* Crap */
86 u8 checksum
; /* Modulo 256 checksum must give 0 */
87 struct irq_info slots
[0];
88 } __attribute__((packed
));
90 extern unsigned int pcibios_irq_mask
;
92 extern raw_spinlock_t pci_config_lock
;
94 extern int (*pcibios_enable_irq
)(struct pci_dev
*dev
);
95 extern void (*pcibios_disable_irq
)(struct pci_dev
*dev
);
98 int (*read
)(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
99 int reg
, int len
, u32
*val
);
100 int (*write
)(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
101 int reg
, int len
, u32 val
);
104 extern const struct pci_raw_ops
*raw_pci_ops
;
105 extern const struct pci_raw_ops
*raw_pci_ext_ops
;
107 extern const struct pci_raw_ops pci_direct_conf1
;
108 extern bool port_cf9_safe
;
110 /* arch_initcall level */
111 extern int pci_direct_probe(void);
112 extern void pci_direct_init(int type
);
113 extern void pci_pcbios_init(void);
114 extern void __init
dmi_check_pciprobe(void);
115 extern void __init
dmi_check_skip_isa_align(void);
117 /* some common used subsys_initcalls */
118 extern int __init
pci_acpi_init(void);
119 extern void __init
pcibios_irq_init(void);
120 extern int __init
pcibios_init(void);
121 extern int pci_legacy_init(void);
122 extern void pcibios_fixup_irqs(void);
126 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
127 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
129 struct pci_mmcfg_region
{
130 struct list_head list
;
137 char name
[PCI_MMCFG_RESOURCE_NAME_LEN
];
140 extern int __init
pci_mmcfg_arch_init(void);
141 extern void __init
pci_mmcfg_arch_free(void);
142 extern struct pci_mmcfg_region
*pci_mmconfig_lookup(int segment
, int bus
);
144 extern struct list_head pci_mmcfg_list
;
146 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
149 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
150 * on their northbrige except through the * %eax register. As such, you MUST
151 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
152 * accessor functions.
153 * In fact just use pci_config_*, nothing else please.
155 static inline unsigned char mmio_config_readb(void __iomem
*pos
)
158 asm volatile("movb (%1),%%al" : "=a" (val
) : "r" (pos
));
162 static inline unsigned short mmio_config_readw(void __iomem
*pos
)
165 asm volatile("movw (%1),%%ax" : "=a" (val
) : "r" (pos
));
169 static inline unsigned int mmio_config_readl(void __iomem
*pos
)
172 asm volatile("movl (%1),%%eax" : "=a" (val
) : "r" (pos
));
176 static inline void mmio_config_writeb(void __iomem
*pos
, u8 val
)
178 asm volatile("movb %%al,(%1)" : : "a" (val
), "r" (pos
) : "memory");
181 static inline void mmio_config_writew(void __iomem
*pos
, u16 val
)
183 asm volatile("movw %%ax,(%1)" : : "a" (val
), "r" (pos
) : "memory");
186 static inline void mmio_config_writel(void __iomem
*pos
, u32 val
)
188 asm volatile("movl %%eax,(%1)" : : "a" (val
), "r" (pos
) : "memory");
193 # define x86_default_pci_init pci_acpi_init
195 # define x86_default_pci_init pci_legacy_init
197 # define x86_default_pci_init_irq pcibios_irq_init
198 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
200 # define x86_default_pci_init NULL
201 # define x86_default_pci_init_irq NULL
202 # define x86_default_pci_fixup_irqs NULL