arch/x86/include/asm/pgtable-3level.h

   1 #ifndef _ASM_X86_PGTABLE_3LEVEL_H
   2 #define _ASM_X86_PGTABLE_3LEVEL_H
   3
   4 /*
   5  * Intel Physical Address Extension (PAE) Mode - three-level page
   6  * tables on PPro+ CPUs.
   7  *
   8  * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
   9  */
  10
  11 #define pte_ERROR(e)                                                    \
  12         printk("%s:%d: bad pte %p(%08lx%08lx).\n",                      \
  13                __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
  14 #define pmd_ERROR(e)                                                    \
  15         printk("%s:%d: bad pmd %p(%016Lx).\n",                          \
  16                __FILE__, __LINE__, &(e), pmd_val(e))
  17 #define pgd_ERROR(e)                                                    \
  18         printk("%s:%d: bad pgd %p(%016Lx).\n",                          \
  19                __FILE__, __LINE__, &(e), pgd_val(e))
  20
  21 static inline int pud_none(pud_t pud)
  22 {
  23         return pud_val(pud) == 0;
  24 }
  25
  26 /* Rules for using set_pte: the pte being assigned *must* be
  27  * either not present or in a state where the hardware will
  28  * not attempt to update the pte.  In places where this is
  29  * not possible, use pte_get_and_clear to obtain the old pte
  30  * value and then use set_pte to update it.  -ben
  31  */
  32 static inline void native_set_pte(pte_t *ptep, pte_t pte)
  33 {
  34         ptep->pte_high = pte.pte_high;
  35         smp_wmb();
  36         ptep->pte_low = pte.pte_low;
  37 }
  38
  39 /*
  40  * Since this is only called on user PTEs, and the page fault handler
  41  * must handle the already racy situation of simultaneous page faults,
  42  * we are justified in merely clearing the PTE present bit, followed
  43  * by a set.  The ordering here is important.
  44  */
  45 static inline void native_set_pte_present(struct mm_struct *mm,
  46                                           unsigned long addr,
  47                                           pte_t *ptep, pte_t pte)
  48 {
  49         ptep->pte_low = 0;
  50         smp_wmb();
  51         ptep->pte_high = pte.pte_high;
  52         smp_wmb();
  53         ptep->pte_low = pte.pte_low;
  54 }
  55
  56 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
  57 {
  58         set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
  59 }
  60
  61 static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
  62 {
  63         set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
  64 }
  65
  66 static inline void native_set_pud(pud_t *pudp, pud_t pud)
  67 {
  68         set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
  69 }
  70
  71 /*
  72  * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
  73  * entry, so clear the bottom half first and enforce ordering with a compiler
  74  * barrier.
  75  */
  76 static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
  77                                     pte_t *ptep)
  78 {
  79         ptep->pte_low = 0;
  80         smp_wmb();
  81         ptep->pte_high = 0;
  82 }
  83
  84 static inline void native_pmd_clear(pmd_t *pmd)
  85 {
  86         u32 *tmp = (u32 *)pmd;
  87         *tmp = 0;
  88         smp_wmb();
  89         *(tmp + 1) = 0;
  90 }
  91
  92 static inline void pud_clear(pud_t *pudp)
  93 {
  94         unsigned long pgd;
  95
  96         set_pud(pudp, __pud(0));
  97
  98         /*
  99          * According to Intel App note "TLBs, Paging-Structure Caches,
 100          * and Their Invalidation", April 2007, document 317080-001,
 101          * section 8.1: in PAE mode we explicitly have to flush the
 102          * TLB via cr3 if the top-level pgd is changed...
 103          *
 104          * Make sure the pud entry we're updating is within the
 105          * current pgd to avoid unnecessary TLB flushes.
 106          */
 107         pgd = read_cr3();
 108         if (__pa(pudp) >= pgd && __pa(pudp) <
 109             (pgd + sizeof(pgd_t)*PTRS_PER_PGD))
 110                 write_cr3(pgd);
 111 }
 112
 113 #ifdef CONFIG_SMP
 114 static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
 115 {
 116         pte_t res;
 117
 118         /* xchg acts as a barrier before the setting of the high bits */
 119         res.pte_low = xchg(&ptep->pte_low, 0);
 120         res.pte_high = ptep->pte_high;
 121         ptep->pte_high = 0;
 122
 123         return res;
 124 }
 125 #else
 126 #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
 127 #endif
 128
 129 /*
 130  * Bits 0, 6 and 7 are taken in the low part of the pte,
 131  * put the 32 bits of offset into the high part.
 132  */
 133 #define pte_to_pgoff(pte) ((pte).pte_high)
 134 #define pgoff_to_pte(off)                                               \
 135         ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
 136 #define PTE_FILE_MAX_BITS       32
 137
 138 /* Encode and de-code a swap entry */
 139 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
 140 #define __swp_type(x)                   (((x).val) & 0x1f)
 141 #define __swp_offset(x)                 ((x).val >> 5)
 142 #define __swp_entry(type, offset)       ((swp_entry_t){(type) | (offset) << 5})
 143 #define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
 144 #define __swp_entry_to_pte(x)           ((pte_t){ { .pte_high = (x).val } })
 145
 146 #endif /* _ASM_X86_PGTABLE_3LEVEL_H */