1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc
));
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
65 * CPU type and hardware bug flags. Kept separately for each CPU.
66 * Members of this structure are referenced in head.S, so think twice
67 * before touching them. [mj]
71 __u8 x86
; /* CPU family */
72 __u8 x86_vendor
; /* CPU vendor */
76 char wp_works_ok
; /* It doesn't on 386's */
78 /* Problems on some 486Dx4's and old 386's: */
87 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
92 /* CPUID returned core id bits: */
94 /* Max extended CPUID function supported: */
95 __u32 extended_cpuid_level
;
96 /* Maximum supported CPUID level, -1=no CPUID: */
98 __u32 x86_capability
[NCAPINTS
];
99 char x86_vendor_id
[16];
100 char x86_model_id
[64];
101 /* in KB - valid for CPUS which support this call: */
103 int x86_cache_alignment
; /* In bytes */
105 unsigned long loops_per_jiffy
;
106 /* cpuid returned max cores value: */
110 u16 x86_clflush_size
;
111 /* number of cores as seen by the OS: */
113 /* Physical processor id: */
117 /* Compute unit id */
119 /* Index into per_cpu list: */
122 } __attribute__((__aligned__(SMP_CACHE_BYTES
)));
124 #define X86_VENDOR_INTEL 0
125 #define X86_VENDOR_CYRIX 1
126 #define X86_VENDOR_AMD 2
127 #define X86_VENDOR_UMC 3
128 #define X86_VENDOR_CENTAUR 5
129 #define X86_VENDOR_TRANSMETA 7
130 #define X86_VENDOR_NSC 8
131 #define X86_VENDOR_NUM 9
133 #define X86_VENDOR_UNKNOWN 0xff
136 * capabilities of CPUs
138 extern struct cpuinfo_x86 boot_cpu_data
;
139 extern struct cpuinfo_x86 new_cpu_data
;
141 extern struct tss_struct doublefault_tss
;
142 extern __u32 cpu_caps_cleared
[NCAPINTS
];
143 extern __u32 cpu_caps_set
[NCAPINTS
];
146 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
147 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
149 #define cpu_info boot_cpu_data
150 #define cpu_data(cpu) boot_cpu_data
153 extern const struct seq_operations cpuinfo_op
;
155 static inline int hlt_works(int cpu
)
158 return cpu_data(cpu
).hlt_works_ok
;
164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
166 extern void cpu_detect(struct cpuinfo_x86
*c
);
168 extern struct pt_regs
*idle_regs(struct pt_regs
*);
170 extern void early_cpu_init(void);
171 extern void identify_boot_cpu(void);
172 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
173 extern void print_cpu_info(struct cpuinfo_x86
*);
174 void print_cpu_msr(struct cpuinfo_x86
*);
175 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
176 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
177 extern unsigned short num_cache_leaves
;
179 extern void detect_extended_topology(struct cpuinfo_x86
*c
);
180 extern void detect_ht(struct cpuinfo_x86
*c
);
182 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
183 unsigned int *ecx
, unsigned int *edx
)
185 /* ecx is often an input as well as an output. */
191 : "0" (*eax
), "2" (*ecx
)
195 static inline void load_cr3(pgd_t
*pgdir
)
197 write_cr3(__pa(pgdir
));
201 /* This is the TSS defined by the hardware. */
203 unsigned short back_link
, __blh
;
205 unsigned short ss0
, __ss0h
;
207 /* ss1 caches MSR_IA32_SYSENTER_CS: */
208 unsigned short ss1
, __ss1h
;
210 unsigned short ss2
, __ss2h
;
222 unsigned short es
, __esh
;
223 unsigned short cs
, __csh
;
224 unsigned short ss
, __ssh
;
225 unsigned short ds
, __dsh
;
226 unsigned short fs
, __fsh
;
227 unsigned short gs
, __gsh
;
228 unsigned short ldt
, __ldth
;
229 unsigned short trace
;
230 unsigned short io_bitmap_base
;
232 } __attribute__((packed
));
246 } __attribute__((packed
)) ____cacheline_aligned
;
252 #define IO_BITMAP_BITS 65536
253 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
254 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
255 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
256 #define INVALID_IO_BITMAP_OFFSET 0x8000
260 * The hardware state:
262 struct x86_hw_tss x86_tss
;
265 * The extra 1 is there because the CPU will access an
266 * additional byte beyond the end of the IO permission
267 * bitmap. The extra byte must be all 1 bits, and must
268 * be within the limit.
270 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
273 * .. and then another 0x100 bytes for the emergency kernel stack:
275 unsigned long stack
[64];
277 } ____cacheline_aligned
;
279 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, init_tss
);
282 * Save the original ist values for checking stack pointers during debugging
285 unsigned long ist
[7];
288 #define MXCSR_DEFAULT 0x1f80
290 struct i387_fsave_struct
{
291 u32 cwd
; /* FPU Control Word */
292 u32 swd
; /* FPU Status Word */
293 u32 twd
; /* FPU Tag Word */
294 u32 fip
; /* FPU IP Offset */
295 u32 fcs
; /* FPU IP Selector */
296 u32 foo
; /* FPU Operand Pointer Offset */
297 u32 fos
; /* FPU Operand Pointer Selector */
299 /* 8*10 bytes for each FP-reg = 80 bytes: */
302 /* Software status information [not touched by FSAVE ]: */
306 struct i387_fxsave_struct
{
307 u16 cwd
; /* Control Word */
308 u16 swd
; /* Status Word */
309 u16 twd
; /* Tag Word */
310 u16 fop
; /* Last Instruction Opcode */
313 u64 rip
; /* Instruction Pointer */
314 u64 rdp
; /* Data Pointer */
317 u32 fip
; /* FPU IP Offset */
318 u32 fcs
; /* FPU IP Selector */
319 u32 foo
; /* FPU Operand Offset */
320 u32 fos
; /* FPU Operand Selector */
323 u32 mxcsr
; /* MXCSR Register State */
324 u32 mxcsr_mask
; /* MXCSR Mask */
326 /* 8*16 bytes for each FP-reg = 128 bytes: */
329 /* 16*16 bytes for each XMM-reg = 256 bytes: */
339 } __attribute__((aligned(16)));
341 struct i387_soft_struct
{
349 /* 8*10 bytes for each FP-reg = 80 bytes: */
357 struct math_emu_info
*info
;
362 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
366 struct xsave_hdr_struct
{
370 } __attribute__((packed
));
372 struct xsave_struct
{
373 struct i387_fxsave_struct i387
;
374 struct xsave_hdr_struct xsave_hdr
;
375 struct ymmh_struct ymmh
;
376 /* new processor state extensions will go here */
377 } __attribute__ ((packed
, aligned (64)));
379 union thread_xstate
{
380 struct i387_fsave_struct fsave
;
381 struct i387_fxsave_struct fxsave
;
382 struct i387_soft_struct soft
;
383 struct xsave_struct xsave
;
387 unsigned int last_cpu
;
388 unsigned int has_fpu
;
389 union thread_xstate
*state
;
393 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
395 union irq_stack_union
{
396 char irq_stack
[IRQ_STACK_SIZE
];
398 * GCC hardcodes the stack canary as %gs:40. Since the
399 * irq_stack is the object at %gs:0, we reserve the bottom
400 * 48 bytes of the irq stack for the canary.
404 unsigned long stack_canary
;
408 DECLARE_PER_CPU_FIRST(union irq_stack_union
, irq_stack_union
);
409 DECLARE_INIT_PER_CPU(irq_stack_union
);
411 DECLARE_PER_CPU(char *, irq_stack_ptr
);
412 DECLARE_PER_CPU(unsigned int, irq_count
);
413 extern unsigned long kernel_eflags
;
414 extern asmlinkage
void ignore_sysret(void);
416 #ifdef CONFIG_CC_STACKPROTECTOR
418 * Make sure stack canary segment base is cached-aligned:
419 * "For Intel Atom processors, avoid non zero segment base address
420 * that is not aligned to cache line boundary at all cost."
421 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
423 struct stack_canary
{
424 char __pad
[20]; /* canary at %gs:20 */
425 unsigned long canary
;
427 DECLARE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
431 extern unsigned int xstate_size
;
432 extern void free_thread_xstate(struct task_struct
*);
433 extern struct kmem_cache
*task_xstate_cachep
;
437 struct thread_struct
{
438 /* Cached TLS descriptors: */
439 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
443 unsigned long sysenter_cs
;
445 unsigned long usersp
; /* Copy from PDA */
448 unsigned short fsindex
;
449 unsigned short gsindex
;
458 /* Save middle states of ptrace breakpoints */
459 struct perf_event
*ptrace_bps
[HBP_NUM
];
460 /* Debug status used for traps, single steps, etc... */
461 unsigned long debugreg6
;
462 /* Keep track of the exact dr7 value set by the user */
463 unsigned long ptrace_dr7
;
466 unsigned long trap_nr
;
467 unsigned long error_code
;
468 /* floating point and extended processor state */
471 /* Virtual 86 mode info */
472 struct vm86_struct __user
*vm86_info
;
473 unsigned long screen_bitmap
;
474 unsigned long v86flags
;
475 unsigned long v86mask
;
476 unsigned long saved_sp0
;
477 unsigned int saved_fs
;
478 unsigned int saved_gs
;
480 /* IO permissions: */
481 unsigned long *io_bitmap_ptr
;
483 /* Max allowed port in the bitmap, in bytes: */
484 unsigned io_bitmap_max
;
488 * Set IOPL bits in EFLAGS from given mask
490 static inline void native_set_iopl_mask(unsigned mask
)
495 asm volatile ("pushfl;"
502 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
507 native_load_sp0(struct tss_struct
*tss
, struct thread_struct
*thread
)
509 tss
->x86_tss
.sp0
= thread
->sp0
;
511 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
512 if (unlikely(tss
->x86_tss
.ss1
!= thread
->sysenter_cs
)) {
513 tss
->x86_tss
.ss1
= thread
->sysenter_cs
;
514 wrmsr(MSR_IA32_SYSENTER_CS
, thread
->sysenter_cs
, 0);
519 static inline void native_swapgs(void)
522 asm volatile("swapgs" ::: "memory");
526 #ifdef CONFIG_PARAVIRT
527 #include <asm/paravirt.h>
529 #define __cpuid native_cpuid
530 #define paravirt_enabled() 0
532 static inline void load_sp0(struct tss_struct
*tss
,
533 struct thread_struct
*thread
)
535 native_load_sp0(tss
, thread
);
538 #define set_iopl_mask native_set_iopl_mask
539 #endif /* CONFIG_PARAVIRT */
542 * Save the cr4 feature set we're using (ie
543 * Pentium 4MB enable and PPro Global page
544 * enable), so that any CPU's that boot up
545 * after us can get the correct flags.
547 extern unsigned long mmu_cr4_features
;
549 static inline void set_in_cr4(unsigned long mask
)
553 mmu_cr4_features
|= mask
;
559 static inline void clear_in_cr4(unsigned long mask
)
563 mmu_cr4_features
&= ~mask
;
575 * create a kernel thread without removing it from tasklists
577 extern int kernel_thread(int (*fn
)(void *), void *arg
, unsigned long flags
);
579 /* Free all resources held by a thread. */
580 extern void release_thread(struct task_struct
*);
582 /* Prepare to copy thread state - unlazy all lazy state */
583 extern void prepare_to_copy(struct task_struct
*tsk
);
585 unsigned long get_wchan(struct task_struct
*p
);
588 * Generic CPUID function
589 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
590 * resulting in stale register contents being returned.
592 static inline void cpuid(unsigned int op
,
593 unsigned int *eax
, unsigned int *ebx
,
594 unsigned int *ecx
, unsigned int *edx
)
598 __cpuid(eax
, ebx
, ecx
, edx
);
601 /* Some CPUID calls want 'count' to be placed in ecx */
602 static inline void cpuid_count(unsigned int op
, int count
,
603 unsigned int *eax
, unsigned int *ebx
,
604 unsigned int *ecx
, unsigned int *edx
)
608 __cpuid(eax
, ebx
, ecx
, edx
);
612 * CPUID functions returning a single datum
614 static inline unsigned int cpuid_eax(unsigned int op
)
616 unsigned int eax
, ebx
, ecx
, edx
;
618 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
623 static inline unsigned int cpuid_ebx(unsigned int op
)
625 unsigned int eax
, ebx
, ecx
, edx
;
627 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
632 static inline unsigned int cpuid_ecx(unsigned int op
)
634 unsigned int eax
, ebx
, ecx
, edx
;
636 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
641 static inline unsigned int cpuid_edx(unsigned int op
)
643 unsigned int eax
, ebx
, ecx
, edx
;
645 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
650 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
651 static inline void rep_nop(void)
653 asm volatile("rep; nop" ::: "memory");
656 static inline void cpu_relax(void)
661 /* Stop speculative execution and prefetching of modified code. */
662 static inline void sync_core(void)
666 #if defined(CONFIG_M386) || defined(CONFIG_M486)
667 if (boot_cpu_data
.x86
< 5)
668 /* There is no speculative execution.
669 * jmp is a barrier to prefetching. */
670 asm volatile("jmp 1f\n1:\n" ::: "memory");
673 /* cpuid is a barrier to speculative execution.
674 * Prefetched instructions are automatically
675 * invalidated when modified. */
676 asm volatile("cpuid" : "=a" (tmp
) : "0" (1)
677 : "ebx", "ecx", "edx", "memory");
680 static inline void __monitor(const void *eax
, unsigned long ecx
,
683 /* "monitor %eax, %ecx, %edx;" */
684 asm volatile(".byte 0x0f, 0x01, 0xc8;"
685 :: "a" (eax
), "c" (ecx
), "d"(edx
));
688 static inline void __mwait(unsigned long eax
, unsigned long ecx
)
690 /* "mwait %eax, %ecx;" */
691 asm volatile(".byte 0x0f, 0x01, 0xc9;"
692 :: "a" (eax
), "c" (ecx
));
695 static inline void __sti_mwait(unsigned long eax
, unsigned long ecx
)
698 /* "mwait %eax, %ecx;" */
699 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
700 :: "a" (eax
), "c" (ecx
));
703 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
704 extern void init_amd_e400_c1e_mask(void);
706 extern unsigned long boot_option_idle_override
;
707 extern bool amd_e400_c1e_detected
;
709 enum idle_boot_override
{IDLE_NO_OVERRIDE
=0, IDLE_HALT
, IDLE_NOMWAIT
,
710 IDLE_POLL
, IDLE_FORCE_MWAIT
};
712 extern void enable_sep_cpu(void);
713 extern int sysenter_setup(void);
715 extern void early_trap_init(void);
717 /* Defined in head.S */
718 extern struct desc_ptr early_gdt_descr
;
720 extern void cpu_set_gdt(int);
721 extern void switch_to_new_gdt(int);
722 extern void load_percpu_segment(int);
723 extern void cpu_init(void);
725 static inline unsigned long get_debugctlmsr(void)
727 unsigned long debugctlmsr
= 0;
729 #ifndef CONFIG_X86_DEBUGCTLMSR
730 if (boot_cpu_data
.x86
< 6)
733 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
738 static inline void update_debugctlmsr(unsigned long debugctlmsr
)
740 #ifndef CONFIG_X86_DEBUGCTLMSR
741 if (boot_cpu_data
.x86
< 6)
744 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
748 * from system description table in BIOS. Mostly for MCA use, but
749 * others may find it useful:
751 extern unsigned int machine_id
;
752 extern unsigned int machine_submodel_id
;
753 extern unsigned int BIOS_revision
;
755 /* Boot loader type from the setup header: */
756 extern int bootloader_type
;
757 extern int bootloader_version
;
759 extern char ignore_fpu_irq
;
761 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
762 #define ARCH_HAS_PREFETCHW
763 #define ARCH_HAS_SPINLOCK_PREFETCH
766 # define BASE_PREFETCH ASM_NOP4
767 # define ARCH_HAS_PREFETCH
769 # define BASE_PREFETCH "prefetcht0 (%1)"
773 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
775 * It's not worth to care about 3dnow prefetches for the K6
776 * because they are microcoded there and very slow.
778 static inline void prefetch(const void *x
)
780 alternative_input(BASE_PREFETCH
,
787 * 3dnow prefetch to get an exclusive cache line.
788 * Useful for spinlocks to avoid one state transition in the
789 * cache coherency protocol:
791 static inline void prefetchw(const void *x
)
793 alternative_input(BASE_PREFETCH
,
799 static inline void spin_lock_prefetch(const void *x
)
806 * User space process size: 3GB (default).
808 #define TASK_SIZE PAGE_OFFSET
809 #define TASK_SIZE_MAX TASK_SIZE
810 #define STACK_TOP TASK_SIZE
811 #define STACK_TOP_MAX STACK_TOP
813 #define INIT_THREAD { \
814 .sp0 = sizeof(init_stack) + (long)&init_stack, \
816 .sysenter_cs = __KERNEL_CS, \
817 .io_bitmap_ptr = NULL, \
821 * Note that the .io_bitmap member must be extra-big. This is because
822 * the CPU will access an additional byte beyond the end of the IO
823 * permission bitmap. The extra byte must be all 1 bits, and must
824 * be within the limit.
828 .sp0 = sizeof(init_stack) + (long)&init_stack, \
829 .ss0 = __KERNEL_DS, \
830 .ss1 = __KERNEL_CS, \
831 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
833 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
836 extern unsigned long thread_saved_pc(struct task_struct
*tsk
);
838 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
839 #define KSTK_TOP(info) \
841 unsigned long *__ptr = (unsigned long *)(info); \
842 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
846 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
847 * This is necessary to guarantee that the entire "struct pt_regs"
848 * is accessible even if the CPU haven't stored the SS/ESP registers
849 * on the stack (interrupt gate does not save these registers
850 * when switching to the same priv ring).
851 * Therefore beware: accessing the ss/esp fields of the
852 * "struct pt_regs" is possible, but they may contain the
853 * completely wrong values.
855 #define task_pt_regs(task) \
857 struct pt_regs *__regs__; \
858 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
862 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
866 * User space process size. 47bits minus one guard page.
868 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
870 /* This decides where the kernel will search for a free chunk of vm
871 * space during mmap's.
873 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
874 0xc0000000 : 0xFFFFe000)
876 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
877 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
878 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
879 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
881 #define STACK_TOP TASK_SIZE
882 #define STACK_TOP_MAX TASK_SIZE_MAX
884 #define INIT_THREAD { \
885 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
889 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
893 * Return saved PC of a blocked thread.
894 * What is this good for? it will be always the scheduler or ret_from_fork.
896 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
898 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
899 extern unsigned long KSTK_ESP(struct task_struct
*task
);
902 * User space RSP while inside the SYSCALL fast path
904 DECLARE_PER_CPU(unsigned long, old_rsp
);
906 #endif /* CONFIG_X86_64 */
908 extern void start_thread(struct pt_regs
*regs
, unsigned long new_ip
,
909 unsigned long new_sp
);
912 * This decides where the kernel will search for a free chunk of vm
913 * space during mmap's.
915 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
917 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
919 /* Get/set a process' ability to use the timestamp counter instruction */
920 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
921 #define SET_TSC_CTL(val) set_tsc_mode((val))
923 extern int get_tsc_mode(unsigned long adr
);
924 extern int set_tsc_mode(unsigned int val
);
926 extern int amd_get_nb_id(int cpu
);
932 static inline void get_aperfmperf(struct aperfmperf
*am
)
934 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF
));
936 rdmsrl(MSR_IA32_APERF
, am
->aperf
);
937 rdmsrl(MSR_IA32_MPERF
, am
->mperf
);
940 #define APERFMPERF_SHIFT 10
943 unsigned long calc_aperfmperf_ratio(struct aperfmperf
*old
,
944 struct aperfmperf
*new)
946 u64 aperf
= new->aperf
- old
->aperf
;
947 u64 mperf
= new->mperf
- old
->mperf
;
948 unsigned long ratio
= aperf
;
950 mperf
>>= APERFMPERF_SHIFT
;
952 ratio
= div64_u64(aperf
, mperf
);
958 * AMD errata checking
960 #ifdef CONFIG_CPU_SUP_AMD
961 extern const int amd_erratum_383
[];
962 extern const int amd_erratum_400
[];
963 extern bool cpu_has_amd_erratum(const int *);
965 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
966 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
967 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
968 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
969 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
970 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
971 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
974 #define cpu_has_amd_erratum(x) (false)
975 #endif /* CONFIG_CPU_SUP_AMD */
979 * disable hlt during certain critical i/o operations
981 #define HAVE_DISABLE_HLT
984 void disable_hlt(void);
985 void enable_hlt(void);
987 void cpu_idle_wait(void);
989 extern unsigned long arch_align_stack(unsigned long sp
);
990 extern void free_init_pages(char *what
, unsigned long begin
, unsigned long end
);
992 void default_idle(void);
993 bool set_pm_idle_to_default(void);
995 void stop_this_cpu(void *dummy
);
997 #endif /* _ASM_X86_PROCESSOR_H */