arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable_types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24 #include <asm/ds.h>
  25
  26 #include <linux/personality.h>
  27 #include <linux/cpumask.h>
  28 #include <linux/cache.h>
  29 #include <linux/threads.h>
  30 #include <linux/init.h>
  31
  32 /*
  33  * Default implementation of macro that returns current
  34  * instruction pointer ("program counter").
  35  */
  36 static inline void *current_text_addr(void)
  37 {
  38         void *pc;
  39
  40         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  41
  42         return pc;
  43 }
  44
  45 #ifdef CONFIG_X86_VSMP
  46 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  47 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  48 #else
  49 # define ARCH_MIN_TASKALIGN             16
  50 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  51 #endif
  52
  53 /*
  54  *  CPU type and hardware bug flags. Kept separately for each CPU.
  55  *  Members of this structure are referenced in head.S, so think twice
  56  *  before touching them. [mj]
  57  */
  58
  59 struct cpuinfo_x86 {
  60         __u8                    x86;            /* CPU family */
  61         __u8                    x86_vendor;     /* CPU vendor */
  62         __u8                    x86_model;
  63         __u8                    x86_mask;
  64 #ifdef CONFIG_X86_32
  65         char                    wp_works_ok;    /* It doesn't on 386's */
  66
  67         /* Problems on some 486Dx4's and old 386's: */
  68         char                    hlt_works_ok;
  69         char                    hard_math;
  70         char                    rfu;
  71         char                    fdiv_bug;
  72         char                    f00f_bug;
  73         char                    coma_bug;
  74         char                    pad0;
  75 #else
  76         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  77         int                     x86_tlbsize;
  78 #endif
  79         __u8                    x86_virt_bits;
  80         __u8                    x86_phys_bits;
  81         /* CPUID returned core id bits: */
  82         __u8                    x86_coreid_bits;
  83         /* Max extended CPUID function supported: */
  84         __u32                   extended_cpuid_level;
  85         /* Maximum supported CPUID level, -1=no CPUID: */
  86         int                     cpuid_level;
  87         __u32                   x86_capability[NCAPINTS];
  88         char                    x86_vendor_id[16];
  89         char                    x86_model_id[64];
  90         /* in KB - valid for CPUS which support this call: */
  91         int                     x86_cache_size;
  92         int                     x86_cache_alignment;    /* In bytes */
  93         int                     x86_power;
  94         unsigned long           loops_per_jiffy;
  95 #ifdef CONFIG_SMP
  96         /* cpus sharing the last level cache: */
  97         cpumask_var_t           llc_shared_map;
  98 #endif
  99         /* cpuid returned max cores value: */
 100         u16                      x86_max_cores;
 101         u16                     apicid;
 102         u16                     initial_apicid;
 103         u16                     x86_clflush_size;
 104 #ifdef CONFIG_SMP
 105         /* number of cores as seen by the OS: */
 106         u16                     booted_cores;
 107         /* Physical processor id: */
 108         u16                     phys_proc_id;
 109         /* Core id: */
 110         u16                     cpu_core_id;
 111         /* Index into per_cpu list: */
 112         u16                     cpu_index;
 113 #endif
 114         unsigned int            x86_hyper_vendor;
 115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 116
 117 #define X86_VENDOR_INTEL        0
 118 #define X86_VENDOR_CYRIX        1
 119 #define X86_VENDOR_AMD          2
 120 #define X86_VENDOR_UMC          3
 121 #define X86_VENDOR_CENTAUR      5
 122 #define X86_VENDOR_TRANSMETA    7
 123 #define X86_VENDOR_NSC          8
 124 #define X86_VENDOR_NUM          9
 125
 126 #define X86_VENDOR_UNKNOWN      0xff
 127
 128 #define X86_HYPER_VENDOR_NONE  0
 129 #define X86_HYPER_VENDOR_VMWARE 1
 130
 131 /*
 132  * capabilities of CPUs
 133  */
 134 extern struct cpuinfo_x86       boot_cpu_data;
 135 extern struct cpuinfo_x86       new_cpu_data;
 136
 137 extern struct tss_struct        doublefault_tss;
 138 extern __u32                    cpu_caps_cleared[NCAPINTS];
 139 extern __u32                    cpu_caps_set[NCAPINTS];
 140
 141 #ifdef CONFIG_SMP
 142 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 143 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 144 #define current_cpu_data        __get_cpu_var(cpu_info)
 145 #else
 146 #define cpu_data(cpu)           boot_cpu_data
 147 #define current_cpu_data        boot_cpu_data
 148 #endif
 149
 150 extern const struct seq_operations cpuinfo_op;
 151
 152 static inline int hlt_works(int cpu)
 153 {
 154 #ifdef CONFIG_X86_32
 155         return cpu_data(cpu).hlt_works_ok;
 156 #else
 157         return 1;
 158 #endif
 159 }
 160
 161 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 162
 163 extern void cpu_detect(struct cpuinfo_x86 *c);
 164
 165 extern struct pt_regs *idle_regs(struct pt_regs *);
 166
 167 extern void early_cpu_init(void);
 168 extern void identify_boot_cpu(void);
 169 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 170 extern void print_cpu_info(struct cpuinfo_x86 *);
 171 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 172 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 173 extern unsigned short num_cache_leaves;
 174
 175 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 176 extern void detect_ht(struct cpuinfo_x86 *c);
 177
 178 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 179                                 unsigned int *ecx, unsigned int *edx)
 180 {
 181         /* ecx is often an input as well as an output. */
 182         asm("cpuid"
 183             : "=a" (*eax),
 184               "=b" (*ebx),
 185               "=c" (*ecx),
 186               "=d" (*edx)
 187             : "0" (*eax), "2" (*ecx));
 188 }
 189
 190 static inline void load_cr3(pgd_t *pgdir)
 191 {
 192         write_cr3(__pa(pgdir));
 193 }
 194
 195 #ifdef CONFIG_X86_32
 196 /* This is the TSS defined by the hardware. */
 197 struct x86_hw_tss {
 198         unsigned short          back_link, __blh;
 199         unsigned long           sp0;
 200         unsigned short          ss0, __ss0h;
 201         unsigned long           sp1;
 202         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 203         unsigned short          ss1, __ss1h;
 204         unsigned long           sp2;
 205         unsigned short          ss2, __ss2h;
 206         unsigned long           __cr3;
 207         unsigned long           ip;
 208         unsigned long           flags;
 209         unsigned long           ax;
 210         unsigned long           cx;
 211         unsigned long           dx;
 212         unsigned long           bx;
 213         unsigned long           sp;
 214         unsigned long           bp;
 215         unsigned long           si;
 216         unsigned long           di;
 217         unsigned short          es, __esh;
 218         unsigned short          cs, __csh;
 219         unsigned short          ss, __ssh;
 220         unsigned short          ds, __dsh;
 221         unsigned short          fs, __fsh;
 222         unsigned short          gs, __gsh;
 223         unsigned short          ldt, __ldth;
 224         unsigned short          trace;
 225         unsigned short          io_bitmap_base;
 226
 227 } __attribute__((packed));
 228 #else
 229 struct x86_hw_tss {
 230         u32                     reserved1;
 231         u64                     sp0;
 232         u64                     sp1;
 233         u64                     sp2;
 234         u64                     reserved2;
 235         u64                     ist[7];
 236         u32                     reserved3;
 237         u32                     reserved4;
 238         u16                     reserved5;
 239         u16                     io_bitmap_base;
 240
 241 } __attribute__((packed)) ____cacheline_aligned;
 242 #endif
 243
 244 /*
 245  * IO-bitmap sizes:
 246  */
 247 #define IO_BITMAP_BITS                  65536
 248 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 249 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 250 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 251 #define INVALID_IO_BITMAP_OFFSET        0x8000
 252
 253 struct tss_struct {
 254         /*
 255          * The hardware state:
 256          */
 257         struct x86_hw_tss       x86_tss;
 258
 259         /*
 260          * The extra 1 is there because the CPU will access an
 261          * additional byte beyond the end of the IO permission
 262          * bitmap. The extra byte must be all 1 bits, and must
 263          * be within the limit.
 264          */
 265         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 266
 267         /*
 268          * .. and then another 0x100 bytes for the emergency kernel stack:
 269          */
 270         unsigned long           stack[64];
 271
 272 } ____cacheline_aligned;
 273
 274 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 275
 276 /*
 277  * Save the original ist values for checking stack pointers during debugging
 278  */
 279 struct orig_ist {
 280         unsigned long           ist[7];
 281 };
 282
 283 #define MXCSR_DEFAULT           0x1f80
 284
 285 struct i387_fsave_struct {
 286         u32                     cwd;    /* FPU Control Word             */
 287         u32                     swd;    /* FPU Status Word              */
 288         u32                     twd;    /* FPU Tag Word                 */
 289         u32                     fip;    /* FPU IP Offset                */
 290         u32                     fcs;    /* FPU IP Selector              */
 291         u32                     foo;    /* FPU Operand Pointer Offset   */
 292         u32                     fos;    /* FPU Operand Pointer Selector */
 293
 294         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 295         u32                     st_space[20];
 296
 297         /* Software status information [not touched by FSAVE ]:         */
 298         u32                     status;
 299 };
 300
 301 struct i387_fxsave_struct {
 302         u16                     cwd; /* Control Word                    */
 303         u16                     swd; /* Status Word                     */
 304         u16                     twd; /* Tag Word                        */
 305         u16                     fop; /* Last Instruction Opcode         */
 306         union {
 307                 struct {
 308                         u64     rip; /* Instruction Pointer             */
 309                         u64     rdp; /* Data Pointer                    */
 310                 };
 311                 struct {
 312                         u32     fip; /* FPU IP Offset                   */
 313                         u32     fcs; /* FPU IP Selector                 */
 314                         u32     foo; /* FPU Operand Offset              */
 315                         u32     fos; /* FPU Operand Selector            */
 316                 };
 317         };
 318         u32                     mxcsr;          /* MXCSR Register State */
 319         u32                     mxcsr_mask;     /* MXCSR Mask           */
 320
 321         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 322         u32                     st_space[32];
 323
 324         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 325         u32                     xmm_space[64];
 326
 327         u32                     padding[12];
 328
 329         union {
 330                 u32             padding1[12];
 331                 u32             sw_reserved[12];
 332         };
 333
 334 } __attribute__((aligned(16)));
 335
 336 struct i387_soft_struct {
 337         u32                     cwd;
 338         u32                     swd;
 339         u32                     twd;
 340         u32                     fip;
 341         u32                     fcs;
 342         u32                     foo;
 343         u32                     fos;
 344         /* 8*10 bytes for each FP-reg = 80 bytes: */
 345         u32                     st_space[20];
 346         u8                      ftop;
 347         u8                      changed;
 348         u8                      lookahead;
 349         u8                      no_update;
 350         u8                      rm;
 351         u8                      alimit;
 352         struct math_emu_info    *info;
 353         u32                     entry_eip;
 354 };
 355
 356 struct ymmh_struct {
 357         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 358         u32 ymmh_space[64];
 359 };
 360
 361 struct xsave_hdr_struct {
 362         u64 xstate_bv;
 363         u64 reserved1[2];
 364         u64 reserved2[5];
 365 } __attribute__((packed));
 366
 367 struct xsave_struct {
 368         struct i387_fxsave_struct i387;
 369         struct xsave_hdr_struct xsave_hdr;
 370         struct ymmh_struct ymmh;
 371         /* new processor state extensions will go here */
 372 } __attribute__ ((packed, aligned (64)));
 373
 374 union thread_xstate {
 375         struct i387_fsave_struct        fsave;
 376         struct i387_fxsave_struct       fxsave;
 377         struct i387_soft_struct         soft;
 378         struct xsave_struct             xsave;
 379 };
 380
 381 #ifdef CONFIG_X86_64
 382 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 383
 384 union irq_stack_union {
 385         char irq_stack[IRQ_STACK_SIZE];
 386         /*
 387          * GCC hardcodes the stack canary as %gs:40.  Since the
 388          * irq_stack is the object at %gs:0, we reserve the bottom
 389          * 48 bytes of the irq stack for the canary.
 390          */
 391         struct {
 392                 char gs_base[40];
 393                 unsigned long stack_canary;
 394         };
 395 };
 396
 397 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 398 DECLARE_INIT_PER_CPU(irq_stack_union);
 399
 400 DECLARE_PER_CPU(char *, irq_stack_ptr);
 401 DECLARE_PER_CPU(unsigned int, irq_count);
 402 extern unsigned long kernel_eflags;
 403 extern asmlinkage void ignore_sysret(void);
 404 #else   /* X86_64 */
 405 #ifdef CONFIG_CC_STACKPROTECTOR
 406 DECLARE_PER_CPU(unsigned long, stack_canary);
 407 #endif
 408 #endif  /* X86_64 */
 409
 410 extern unsigned int xstate_size;
 411 extern void free_thread_xstate(struct task_struct *);
 412 extern struct kmem_cache *task_xstate_cachep;
 413
 414 struct thread_struct {
 415         /* Cached TLS descriptors: */
 416         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 417         unsigned long           sp0;
 418         unsigned long           sp;
 419 #ifdef CONFIG_X86_32
 420         unsigned long           sysenter_cs;
 421 #else
 422         unsigned long           usersp; /* Copy from PDA */
 423         unsigned short          es;
 424         unsigned short          ds;
 425         unsigned short          fsindex;
 426         unsigned short          gsindex;
 427 #endif
 428 #ifdef CONFIG_X86_32
 429         unsigned long           ip;
 430 #endif
 431 #ifdef CONFIG_X86_64
 432         unsigned long           fs;
 433 #endif
 434         unsigned long           gs;
 435         /* Hardware debugging registers: */
 436         unsigned long           debugreg0;
 437         unsigned long           debugreg1;
 438         unsigned long           debugreg2;
 439         unsigned long           debugreg3;
 440         unsigned long           debugreg6;
 441         unsigned long           debugreg7;
 442         /* Fault info: */
 443         unsigned long           cr2;
 444         unsigned long           trap_no;
 445         unsigned long           error_code;
 446         /* floating point and extended processor state */
 447         union thread_xstate     *xstate;
 448 #ifdef CONFIG_X86_32
 449         /* Virtual 86 mode info */
 450         struct vm86_struct __user *vm86_info;
 451         unsigned long           screen_bitmap;
 452         unsigned long           v86flags;
 453         unsigned long           v86mask;
 454         unsigned long           saved_sp0;
 455         unsigned int            saved_fs;
 456         unsigned int            saved_gs;
 457 #endif
 458         /* IO permissions: */
 459         unsigned long           *io_bitmap_ptr;
 460         unsigned long           iopl;
 461         /* Max allowed port in the bitmap, in bytes: */
 462         unsigned                io_bitmap_max;
 463 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 464         unsigned long   debugctlmsr;
 465 #ifdef CONFIG_X86_DS
 466 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
 467         struct ds_context       *ds_ctx;
 468 #endif /* CONFIG_X86_DS */
 469 #ifdef CONFIG_X86_PTRACE_BTS
 470 /* the signal to send on a bts buffer overflow */
 471         unsigned int    bts_ovfl_signal;
 472 #endif /* CONFIG_X86_PTRACE_BTS */
 473 };
 474
 475 static inline unsigned long native_get_debugreg(int regno)
 476 {
 477         unsigned long val = 0;  /* Damn you, gcc! */
 478
 479         switch (regno) {
 480         case 0:
 481                 asm("mov %%db0, %0" :"=r" (val));
 482                 break;
 483         case 1:
 484                 asm("mov %%db1, %0" :"=r" (val));
 485                 break;
 486         case 2:
 487                 asm("mov %%db2, %0" :"=r" (val));
 488                 break;
 489         case 3:
 490                 asm("mov %%db3, %0" :"=r" (val));
 491                 break;
 492         case 6:
 493                 asm("mov %%db6, %0" :"=r" (val));
 494                 break;
 495         case 7:
 496                 asm("mov %%db7, %0" :"=r" (val));
 497                 break;
 498         default:
 499                 BUG();
 500         }
 501         return val;
 502 }
 503
 504 static inline void native_set_debugreg(int regno, unsigned long value)
 505 {
 506         switch (regno) {
 507         case 0:
 508                 asm("mov %0, %%db0"     ::"r" (value));
 509                 break;
 510         case 1:
 511                 asm("mov %0, %%db1"     ::"r" (value));
 512                 break;
 513         case 2:
 514                 asm("mov %0, %%db2"     ::"r" (value));
 515                 break;
 516         case 3:
 517                 asm("mov %0, %%db3"     ::"r" (value));
 518                 break;
 519         case 6:
 520                 asm("mov %0, %%db6"     ::"r" (value));
 521                 break;
 522         case 7:
 523                 asm("mov %0, %%db7"     ::"r" (value));
 524                 break;
 525         default:
 526                 BUG();
 527         }
 528 }
 529
 530 /*
 531  * Set IOPL bits in EFLAGS from given mask
 532  */
 533 static inline void native_set_iopl_mask(unsigned mask)
 534 {
 535 #ifdef CONFIG_X86_32
 536         unsigned int reg;
 537
 538         asm volatile ("pushfl;"
 539                       "popl %0;"
 540                       "andl %1, %0;"
 541                       "orl %2, %0;"
 542                       "pushl %0;"
 543                       "popfl"
 544                       : "=&r" (reg)
 545                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 546 #endif
 547 }
 548
 549 static inline void
 550 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 551 {
 552         tss->x86_tss.sp0 = thread->sp0;
 553 #ifdef CONFIG_X86_32
 554         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 555         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 556                 tss->x86_tss.ss1 = thread->sysenter_cs;
 557                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 558         }
 559 #endif
 560 }
 561
 562 static inline void native_swapgs(void)
 563 {
 564 #ifdef CONFIG_X86_64
 565         asm volatile("swapgs" ::: "memory");
 566 #endif
 567 }
 568
 569 #ifdef CONFIG_PARAVIRT
 570 #include <asm/paravirt.h>
 571 #else
 572 #define __cpuid                 native_cpuid
 573 #define paravirt_enabled()      0
 574
 575 /*
 576  * These special macros can be used to get or set a debugging register
 577  */
 578 #define get_debugreg(var, register)                             \
 579         (var) = native_get_debugreg(register)
 580 #define set_debugreg(value, register)                           \
 581         native_set_debugreg(register, value)
 582
 583 static inline void load_sp0(struct tss_struct *tss,
 584                             struct thread_struct *thread)
 585 {
 586         native_load_sp0(tss, thread);
 587 }
 588
 589 #define set_iopl_mask native_set_iopl_mask
 590 #endif /* CONFIG_PARAVIRT */
 591
 592 /*
 593  * Save the cr4 feature set we're using (ie
 594  * Pentium 4MB enable and PPro Global page
 595  * enable), so that any CPU's that boot up
 596  * after us can get the correct flags.
 597  */
 598 extern unsigned long            mmu_cr4_features;
 599
 600 static inline void set_in_cr4(unsigned long mask)
 601 {
 602         unsigned cr4;
 603
 604         mmu_cr4_features |= mask;
 605         cr4 = read_cr4();
 606         cr4 |= mask;
 607         write_cr4(cr4);
 608 }
 609
 610 static inline void clear_in_cr4(unsigned long mask)
 611 {
 612         unsigned cr4;
 613
 614         mmu_cr4_features &= ~mask;
 615         cr4 = read_cr4();
 616         cr4 &= ~mask;
 617         write_cr4(cr4);
 618 }
 619
 620 typedef struct {
 621         unsigned long           seg;
 622 } mm_segment_t;
 623
 624
 625 /*
 626  * create a kernel thread without removing it from tasklists
 627  */
 628 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 629
 630 /* Free all resources held by a thread. */
 631 extern void release_thread(struct task_struct *);
 632
 633 /* Prepare to copy thread state - unlazy all lazy state */
 634 extern void prepare_to_copy(struct task_struct *tsk);
 635
 636 unsigned long get_wchan(struct task_struct *p);
 637
 638 /*
 639  * Generic CPUID function
 640  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 641  * resulting in stale register contents being returned.
 642  */
 643 static inline void cpuid(unsigned int op,
 644                          unsigned int *eax, unsigned int *ebx,
 645                          unsigned int *ecx, unsigned int *edx)
 646 {
 647         *eax = op;
 648         *ecx = 0;
 649         __cpuid(eax, ebx, ecx, edx);
 650 }
 651
 652 /* Some CPUID calls want 'count' to be placed in ecx */
 653 static inline void cpuid_count(unsigned int op, int count,
 654                                unsigned int *eax, unsigned int *ebx,
 655                                unsigned int *ecx, unsigned int *edx)
 656 {
 657         *eax = op;
 658         *ecx = count;
 659         __cpuid(eax, ebx, ecx, edx);
 660 }
 661
 662 /*
 663  * CPUID functions returning a single datum
 664  */
 665 static inline unsigned int cpuid_eax(unsigned int op)
 666 {
 667         unsigned int eax, ebx, ecx, edx;
 668
 669         cpuid(op, &eax, &ebx, &ecx, &edx);
 670
 671         return eax;
 672 }
 673
 674 static inline unsigned int cpuid_ebx(unsigned int op)
 675 {
 676         unsigned int eax, ebx, ecx, edx;
 677
 678         cpuid(op, &eax, &ebx, &ecx, &edx);
 679
 680         return ebx;
 681 }
 682
 683 static inline unsigned int cpuid_ecx(unsigned int op)
 684 {
 685         unsigned int eax, ebx, ecx, edx;
 686
 687         cpuid(op, &eax, &ebx, &ecx, &edx);
 688
 689         return ecx;
 690 }
 691
 692 static inline unsigned int cpuid_edx(unsigned int op)
 693 {
 694         unsigned int eax, ebx, ecx, edx;
 695
 696         cpuid(op, &eax, &ebx, &ecx, &edx);
 697
 698         return edx;
 699 }
 700
 701 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 702 static inline void rep_nop(void)
 703 {
 704         asm volatile("rep; nop" ::: "memory");
 705 }
 706
 707 static inline void cpu_relax(void)
 708 {
 709         rep_nop();
 710 }
 711
 712 /* Stop speculative execution: */
 713 static inline void sync_core(void)
 714 {
 715         int tmp;
 716
 717         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 718                      : "ebx", "ecx", "edx", "memory");
 719 }
 720
 721 static inline void __monitor(const void *eax, unsigned long ecx,
 722                              unsigned long edx)
 723 {
 724         /* "monitor %eax, %ecx, %edx;" */
 725         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 726                      :: "a" (eax), "c" (ecx), "d"(edx));
 727 }
 728
 729 static inline void __mwait(unsigned long eax, unsigned long ecx)
 730 {
 731         /* "mwait %eax, %ecx;" */
 732         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 733                      :: "a" (eax), "c" (ecx));
 734 }
 735
 736 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 737 {
 738         trace_hardirqs_on();
 739         /* "mwait %eax, %ecx;" */
 740         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 741                      :: "a" (eax), "c" (ecx));
 742 }
 743
 744 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 745
 746 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 747 extern void init_c1e_mask(void);
 748
 749 extern unsigned long            boot_option_idle_override;
 750 extern unsigned long            idle_halt;
 751 extern unsigned long            idle_nomwait;
 752
 753 /*
 754  * on systems with caches, caches must be flashed as the absolute
 755  * last instruction before going into a suspended halt.  Otherwise,
 756  * dirty data can linger in the cache and become stale on resume,
 757  * leading to strange errors.
 758  *
 759  * perform a variety of operations to guarantee that the compiler
 760  * will not reorder instructions.  wbinvd itself is serializing
 761  * so the processor will not reorder.
 762  *
 763  * Systems without cache can just go into halt.
 764  */
 765 static inline void wbinvd_halt(void)
 766 {
 767         mb();
 768         /* check for clflush to determine if wbinvd is legal */
 769         if (cpu_has_clflush)
 770                 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
 771         else
 772                 while (1)
 773                         halt();
 774 }
 775
 776 extern void enable_sep_cpu(void);
 777 extern int sysenter_setup(void);
 778
 779 /* Defined in head.S */
 780 extern struct desc_ptr          early_gdt_descr;
 781
 782 extern void cpu_set_gdt(int);
 783 extern void switch_to_new_gdt(int);
 784 extern void load_percpu_segment(int);
 785 extern void cpu_init(void);
 786
 787 static inline unsigned long get_debugctlmsr(void)
 788 {
 789     unsigned long debugctlmsr = 0;
 790
 791 #ifndef CONFIG_X86_DEBUGCTLMSR
 792         if (boot_cpu_data.x86 < 6)
 793                 return 0;
 794 #endif
 795         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 796
 797     return debugctlmsr;
 798 }
 799
 800 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 801 {
 802 #ifndef CONFIG_X86_DEBUGCTLMSR
 803         if (boot_cpu_data.x86 < 6)
 804                 return;
 805 #endif
 806         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 807 }
 808
 809 /*
 810  * from system description table in BIOS. Mostly for MCA use, but
 811  * others may find it useful:
 812  */
 813 extern unsigned int             machine_id;
 814 extern unsigned int             machine_submodel_id;
 815 extern unsigned int             BIOS_revision;
 816
 817 /* Boot loader type from the setup header: */
 818 extern int                      bootloader_type;
 819 extern int                      bootloader_version;
 820
 821 extern char                     ignore_fpu_irq;
 822
 823 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 824 #define ARCH_HAS_PREFETCHW
 825 #define ARCH_HAS_SPINLOCK_PREFETCH
 826
 827 #ifdef CONFIG_X86_32
 828 # define BASE_PREFETCH          ASM_NOP4
 829 # define ARCH_HAS_PREFETCH
 830 #else
 831 # define BASE_PREFETCH          "prefetcht0 (%1)"
 832 #endif
 833
 834 /*
 835  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 836  *
 837  * It's not worth to care about 3dnow prefetches for the K6
 838  * because they are microcoded there and very slow.
 839  */
 840 static inline void prefetch(const void *x)
 841 {
 842         alternative_input(BASE_PREFETCH,
 843                           "prefetchnta (%1)",
 844                           X86_FEATURE_XMM,
 845                           "r" (x));
 846 }
 847
 848 /*
 849  * 3dnow prefetch to get an exclusive cache line.
 850  * Useful for spinlocks to avoid one state transition in the
 851  * cache coherency protocol:
 852  */
 853 static inline void prefetchw(const void *x)
 854 {
 855         alternative_input(BASE_PREFETCH,
 856                           "prefetchw (%1)",
 857                           X86_FEATURE_3DNOW,
 858                           "r" (x));
 859 }
 860
 861 static inline void spin_lock_prefetch(const void *x)
 862 {
 863         prefetchw(x);
 864 }
 865
 866 #ifdef CONFIG_X86_32
 867 /*
 868  * User space process size: 3GB (default).
 869  */
 870 #define TASK_SIZE               PAGE_OFFSET
 871 #define TASK_SIZE_MAX           TASK_SIZE
 872 #define STACK_TOP               TASK_SIZE
 873 #define STACK_TOP_MAX           STACK_TOP
 874
 875 #define INIT_THREAD  {                                                    \
 876         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 877         .vm86_info              = NULL,                                   \
 878         .sysenter_cs            = __KERNEL_CS,                            \
 879         .io_bitmap_ptr          = NULL,                                   \
 880 }
 881
 882 /*
 883  * Note that the .io_bitmap member must be extra-big. This is because
 884  * the CPU will access an additional byte beyond the end of the IO
 885  * permission bitmap. The extra byte must be all 1 bits, and must
 886  * be within the limit.
 887  */
 888 #define INIT_TSS  {                                                       \
 889         .x86_tss = {                                                      \
 890                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 891                 .ss0            = __KERNEL_DS,                            \
 892                 .ss1            = __KERNEL_CS,                            \
 893                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 894          },                                                               \
 895         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 896 }
 897
 898 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 899
 900 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 901 #define KSTK_TOP(info)                                                 \
 902 ({                                                                     \
 903        unsigned long *__ptr = (unsigned long *)(info);                 \
 904        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 905 })
 906
 907 /*
 908  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 909  * This is necessary to guarantee that the entire "struct pt_regs"
 910  * is accessable even if the CPU haven't stored the SS/ESP registers
 911  * on the stack (interrupt gate does not save these registers
 912  * when switching to the same priv ring).
 913  * Therefore beware: accessing the ss/esp fields of the
 914  * "struct pt_regs" is possible, but they may contain the
 915  * completely wrong values.
 916  */
 917 #define task_pt_regs(task)                                             \
 918 ({                                                                     \
 919        struct pt_regs *__regs__;                                       \
 920        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 921        __regs__ - 1;                                                   \
 922 })
 923
 924 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 925
 926 #else
 927 /*
 928  * User space process size. 47bits minus one guard page.
 929  */
 930 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 931
 932 /* This decides where the kernel will search for a free chunk of vm
 933  * space during mmap's.
 934  */
 935 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 936                                         0xc0000000 : 0xFFFFe000)
 937
 938 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 939                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 940 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 941                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 942
 943 #define STACK_TOP               TASK_SIZE
 944 #define STACK_TOP_MAX           TASK_SIZE_MAX
 945
 946 #define INIT_THREAD  { \
 947         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 948 }
 949
 950 #define INIT_TSS  { \
 951         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 952 }
 953
 954 /*
 955  * Return saved PC of a blocked thread.
 956  * What is this good for? it will be always the scheduler or ret_from_fork.
 957  */
 958 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 959
 960 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 961 #define KSTK_ESP(tsk)           -1 /* sorry. doesn't work for syscall. */
 962 #endif /* CONFIG_X86_64 */
 963
 964 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 965                                                unsigned long new_sp);
 966
 967 /*
 968  * This decides where the kernel will search for a free chunk of vm
 969  * space during mmap's.
 970  */
 971 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 972
 973 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 974
 975 /* Get/set a process' ability to use the timestamp counter instruction */
 976 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 977 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 978
 979 extern int get_tsc_mode(unsigned long adr);
 980 extern int set_tsc_mode(unsigned int val);
 981
 982 #endif /* _ASM_X86_PROCESSOR_H */