arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable_types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32
  33 #define HBP_NUM 4
  34 /*
  35  * Default implementation of macro that returns current
  36  * instruction pointer ("program counter").
  37  */
  38 static inline void *current_text_addr(void)
  39 {
  40         void *pc;
  41
  42         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  43
  44         return pc;
  45 }
  46
  47 #ifdef CONFIG_X86_VSMP
  48 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  49 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  50 #else
  51 # define ARCH_MIN_TASKALIGN             16
  52 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  53 #endif
  54
  55 /*
  56  *  CPU type and hardware bug flags. Kept separately for each CPU.
  57  *  Members of this structure are referenced in head.S, so think twice
  58  *  before touching them. [mj]
  59  */
  60
  61 struct cpuinfo_x86 {
  62         __u8                    x86;            /* CPU family */
  63         __u8                    x86_vendor;     /* CPU vendor */
  64         __u8                    x86_model;
  65         __u8                    x86_mask;
  66 #ifdef CONFIG_X86_32
  67         char                    wp_works_ok;    /* It doesn't on 386's */
  68
  69         /* Problems on some 486Dx4's and old 386's: */
  70         char                    hlt_works_ok;
  71         char                    hard_math;
  72         char                    rfu;
  73         char                    fdiv_bug;
  74         char                    f00f_bug;
  75         char                    coma_bug;
  76         char                    pad0;
  77 #else
  78         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  79         int                     x86_tlbsize;
  80 #endif
  81         __u8                    x86_virt_bits;
  82         __u8                    x86_phys_bits;
  83         /* CPUID returned core id bits: */
  84         __u8                    x86_coreid_bits;
  85         /* Max extended CPUID function supported: */
  86         __u32                   extended_cpuid_level;
  87         /* Maximum supported CPUID level, -1=no CPUID: */
  88         int                     cpuid_level;
  89         __u32                   x86_capability[NCAPINTS];
  90         char                    x86_vendor_id[16];
  91         char                    x86_model_id[64];
  92         /* in KB - valid for CPUS which support this call: */
  93         int                     x86_cache_size;
  94         int                     x86_cache_alignment;    /* In bytes */
  95         int                     x86_power;
  96         unsigned long           loops_per_jiffy;
  97         /* cpuid returned max cores value: */
  98         u16                      x86_max_cores;
  99         u16                     apicid;
 100         u16                     initial_apicid;
 101         u16                     x86_clflush_size;
 102 #ifdef CONFIG_SMP
 103         /* number of cores as seen by the OS: */
 104         u16                     booted_cores;
 105         /* Physical processor id: */
 106         u16                     phys_proc_id;
 107         /* Core id: */
 108         u16                     cpu_core_id;
 109         /* Compute unit id */
 110         u8                      compute_unit_id;
 111         /* Index into per_cpu list: */
 112         u16                     cpu_index;
 113 #endif
 114         u32                     microcode;
 115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 116
 117 #define X86_VENDOR_INTEL        0
 118 #define X86_VENDOR_CYRIX        1
 119 #define X86_VENDOR_AMD          2
 120 #define X86_VENDOR_UMC          3
 121 #define X86_VENDOR_CENTAUR      5
 122 #define X86_VENDOR_TRANSMETA    7
 123 #define X86_VENDOR_NSC          8
 124 #define X86_VENDOR_NUM          9
 125
 126 #define X86_VENDOR_UNKNOWN      0xff
 127
 128 /*
 129  * capabilities of CPUs
 130  */
 131 extern struct cpuinfo_x86       boot_cpu_data;
 132 extern struct cpuinfo_x86       new_cpu_data;
 133
 134 extern struct tss_struct        doublefault_tss;
 135 extern __u32                    cpu_caps_cleared[NCAPINTS];
 136 extern __u32                    cpu_caps_set[NCAPINTS];
 137
 138 #ifdef CONFIG_SMP
 139 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 140 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 141 #else
 142 #define cpu_info                boot_cpu_data
 143 #define cpu_data(cpu)           boot_cpu_data
 144 #endif
 145
 146 extern const struct seq_operations cpuinfo_op;
 147
 148 static inline int hlt_works(int cpu)
 149 {
 150 #ifdef CONFIG_X86_32
 151         return cpu_data(cpu).hlt_works_ok;
 152 #else
 153         return 1;
 154 #endif
 155 }
 156
 157 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 158
 159 extern void cpu_detect(struct cpuinfo_x86 *c);
 160
 161 extern struct pt_regs *idle_regs(struct pt_regs *);
 162
 163 extern void early_cpu_init(void);
 164 extern void identify_boot_cpu(void);
 165 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 166 extern void print_cpu_info(struct cpuinfo_x86 *);
 167 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 168 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 169 extern unsigned short num_cache_leaves;
 170
 171 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 172 extern void detect_ht(struct cpuinfo_x86 *c);
 173
 174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 175                                 unsigned int *ecx, unsigned int *edx)
 176 {
 177         /* ecx is often an input as well as an output. */
 178         asm volatile("cpuid"
 179             : "=a" (*eax),
 180               "=b" (*ebx),
 181               "=c" (*ecx),
 182               "=d" (*edx)
 183             : "0" (*eax), "2" (*ecx)
 184             : "memory");
 185 }
 186
 187 static inline void load_cr3(pgd_t *pgdir)
 188 {
 189         write_cr3(__pa(pgdir));
 190 }
 191
 192 #ifdef CONFIG_X86_32
 193 /* This is the TSS defined by the hardware. */
 194 struct x86_hw_tss {
 195         unsigned short          back_link, __blh;
 196         unsigned long           sp0;
 197         unsigned short          ss0, __ss0h;
 198         unsigned long           sp1;
 199         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 200         unsigned short          ss1, __ss1h;
 201         unsigned long           sp2;
 202         unsigned short          ss2, __ss2h;
 203         unsigned long           __cr3;
 204         unsigned long           ip;
 205         unsigned long           flags;
 206         unsigned long           ax;
 207         unsigned long           cx;
 208         unsigned long           dx;
 209         unsigned long           bx;
 210         unsigned long           sp;
 211         unsigned long           bp;
 212         unsigned long           si;
 213         unsigned long           di;
 214         unsigned short          es, __esh;
 215         unsigned short          cs, __csh;
 216         unsigned short          ss, __ssh;
 217         unsigned short          ds, __dsh;
 218         unsigned short          fs, __fsh;
 219         unsigned short          gs, __gsh;
 220         unsigned short          ldt, __ldth;
 221         unsigned short          trace;
 222         unsigned short          io_bitmap_base;
 223
 224 } __attribute__((packed));
 225 #else
 226 struct x86_hw_tss {
 227         u32                     reserved1;
 228         u64                     sp0;
 229         u64                     sp1;
 230         u64                     sp2;
 231         u64                     reserved2;
 232         u64                     ist[7];
 233         u32                     reserved3;
 234         u32                     reserved4;
 235         u16                     reserved5;
 236         u16                     io_bitmap_base;
 237
 238 } __attribute__((packed)) ____cacheline_aligned;
 239 #endif
 240
 241 /*
 242  * IO-bitmap sizes:
 243  */
 244 #define IO_BITMAP_BITS                  65536
 245 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 246 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 247 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 248 #define INVALID_IO_BITMAP_OFFSET        0x8000
 249
 250 struct tss_struct {
 251         /*
 252          * The hardware state:
 253          */
 254         struct x86_hw_tss       x86_tss;
 255
 256         /*
 257          * The extra 1 is there because the CPU will access an
 258          * additional byte beyond the end of the IO permission
 259          * bitmap. The extra byte must be all 1 bits, and must
 260          * be within the limit.
 261          */
 262         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 263
 264         /*
 265          * .. and then another 0x100 bytes for the emergency kernel stack:
 266          */
 267         unsigned long           stack[64];
 268
 269 } ____cacheline_aligned;
 270
 271 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 272
 273 /*
 274  * Save the original ist values for checking stack pointers during debugging
 275  */
 276 struct orig_ist {
 277         unsigned long           ist[7];
 278 };
 279
 280 #define MXCSR_DEFAULT           0x1f80
 281
 282 struct i387_fsave_struct {
 283         u32                     cwd;    /* FPU Control Word             */
 284         u32                     swd;    /* FPU Status Word              */
 285         u32                     twd;    /* FPU Tag Word                 */
 286         u32                     fip;    /* FPU IP Offset                */
 287         u32                     fcs;    /* FPU IP Selector              */
 288         u32                     foo;    /* FPU Operand Pointer Offset   */
 289         u32                     fos;    /* FPU Operand Pointer Selector */
 290
 291         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 292         u32                     st_space[20];
 293
 294         /* Software status information [not touched by FSAVE ]:         */
 295         u32                     status;
 296 };
 297
 298 struct i387_fxsave_struct {
 299         u16                     cwd; /* Control Word                    */
 300         u16                     swd; /* Status Word                     */
 301         u16                     twd; /* Tag Word                        */
 302         u16                     fop; /* Last Instruction Opcode         */
 303         union {
 304                 struct {
 305                         u64     rip; /* Instruction Pointer             */
 306                         u64     rdp; /* Data Pointer                    */
 307                 };
 308                 struct {
 309                         u32     fip; /* FPU IP Offset                   */
 310                         u32     fcs; /* FPU IP Selector                 */
 311                         u32     foo; /* FPU Operand Offset              */
 312                         u32     fos; /* FPU Operand Selector            */
 313                 };
 314         };
 315         u32                     mxcsr;          /* MXCSR Register State */
 316         u32                     mxcsr_mask;     /* MXCSR Mask           */
 317
 318         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 319         u32                     st_space[32];
 320
 321         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 322         u32                     xmm_space[64];
 323
 324         u32                     padding[12];
 325
 326         union {
 327                 u32             padding1[12];
 328                 u32             sw_reserved[12];
 329         };
 330
 331 } __attribute__((aligned(16)));
 332
 333 struct i387_soft_struct {
 334         u32                     cwd;
 335         u32                     swd;
 336         u32                     twd;
 337         u32                     fip;
 338         u32                     fcs;
 339         u32                     foo;
 340         u32                     fos;
 341         /* 8*10 bytes for each FP-reg = 80 bytes: */
 342         u32                     st_space[20];
 343         u8                      ftop;
 344         u8                      changed;
 345         u8                      lookahead;
 346         u8                      no_update;
 347         u8                      rm;
 348         u8                      alimit;
 349         struct math_emu_info    *info;
 350         u32                     entry_eip;
 351 };
 352
 353 struct ymmh_struct {
 354         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 355         u32 ymmh_space[64];
 356 };
 357
 358 struct xsave_hdr_struct {
 359         u64 xstate_bv;
 360         u64 reserved1[2];
 361         u64 reserved2[5];
 362 } __attribute__((packed));
 363
 364 struct xsave_struct {
 365         struct i387_fxsave_struct i387;
 366         struct xsave_hdr_struct xsave_hdr;
 367         struct ymmh_struct ymmh;
 368         /* new processor state extensions will go here */
 369 } __attribute__ ((packed, aligned (64)));
 370
 371 union thread_xstate {
 372         struct i387_fsave_struct        fsave;
 373         struct i387_fxsave_struct       fxsave;
 374         struct i387_soft_struct         soft;
 375         struct xsave_struct             xsave;
 376 };
 377
 378 struct fpu {
 379         union thread_xstate *state;
 380 };
 381
 382 #ifdef CONFIG_X86_64
 383 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 384
 385 union irq_stack_union {
 386         char irq_stack[IRQ_STACK_SIZE];
 387         /*
 388          * GCC hardcodes the stack canary as %gs:40.  Since the
 389          * irq_stack is the object at %gs:0, we reserve the bottom
 390          * 48 bytes of the irq stack for the canary.
 391          */
 392         struct {
 393                 char gs_base[40];
 394                 unsigned long stack_canary;
 395         };
 396 };
 397
 398 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 399 DECLARE_INIT_PER_CPU(irq_stack_union);
 400
 401 DECLARE_PER_CPU(char *, irq_stack_ptr);
 402 DECLARE_PER_CPU(unsigned int, irq_count);
 403 extern unsigned long kernel_eflags;
 404 extern asmlinkage void ignore_sysret(void);
 405 #else   /* X86_64 */
 406 #ifdef CONFIG_CC_STACKPROTECTOR
 407 /*
 408  * Make sure stack canary segment base is cached-aligned:
 409  *   "For Intel Atom processors, avoid non zero segment base address
 410  *    that is not aligned to cache line boundary at all cost."
 411  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 412  */
 413 struct stack_canary {
 414         char __pad[20];         /* canary at %gs:20 */
 415         unsigned long canary;
 416 };
 417 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 418 #endif
 419 #endif  /* X86_64 */
 420
 421 extern unsigned int xstate_size;
 422 extern void free_thread_xstate(struct task_struct *);
 423 extern struct kmem_cache *task_xstate_cachep;
 424
 425 struct perf_event;
 426
 427 struct thread_struct {
 428         /* Cached TLS descriptors: */
 429         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 430         unsigned long           sp0;
 431         unsigned long           sp;
 432 #ifdef CONFIG_X86_32
 433         unsigned long           sysenter_cs;
 434 #else
 435         unsigned long           usersp; /* Copy from PDA */
 436         unsigned short          es;
 437         unsigned short          ds;
 438         unsigned short          fsindex;
 439         unsigned short          gsindex;
 440 #endif
 441 #ifdef CONFIG_X86_32
 442         unsigned long           ip;
 443 #endif
 444 #ifdef CONFIG_X86_64
 445         unsigned long           fs;
 446 #endif
 447         unsigned long           gs;
 448         /* Save middle states of ptrace breakpoints */
 449         struct perf_event       *ptrace_bps[HBP_NUM];
 450         /* Debug status used for traps, single steps, etc... */
 451         unsigned long           debugreg6;
 452         /* Keep track of the exact dr7 value set by the user */
 453         unsigned long           ptrace_dr7;
 454         /* Fault info: */
 455         unsigned long           cr2;
 456         unsigned long           trap_no;
 457         unsigned long           error_code;
 458         /* floating point and extended processor state */
 459         struct fpu              fpu;
 460 #ifdef CONFIG_X86_32
 461         /* Virtual 86 mode info */
 462         struct vm86_struct __user *vm86_info;
 463         unsigned long           screen_bitmap;
 464         unsigned long           v86flags;
 465         unsigned long           v86mask;
 466         unsigned long           saved_sp0;
 467         unsigned int            saved_fs;
 468         unsigned int            saved_gs;
 469 #endif
 470         /* IO permissions: */
 471         unsigned long           *io_bitmap_ptr;
 472         unsigned long           iopl;
 473         /* Max allowed port in the bitmap, in bytes: */
 474         unsigned                io_bitmap_max;
 475 };
 476
 477 static inline unsigned long native_get_debugreg(int regno)
 478 {
 479         unsigned long val = 0;  /* Damn you, gcc! */
 480
 481         switch (regno) {
 482         case 0:
 483                 asm("mov %%db0, %0" :"=r" (val));
 484                 break;
 485         case 1:
 486                 asm("mov %%db1, %0" :"=r" (val));
 487                 break;
 488         case 2:
 489                 asm("mov %%db2, %0" :"=r" (val));
 490                 break;
 491         case 3:
 492                 asm("mov %%db3, %0" :"=r" (val));
 493                 break;
 494         case 6:
 495                 asm("mov %%db6, %0" :"=r" (val));
 496                 break;
 497         case 7:
 498                 asm("mov %%db7, %0" :"=r" (val));
 499                 break;
 500         default:
 501                 BUG();
 502         }
 503         return val;
 504 }
 505
 506 static inline void native_set_debugreg(int regno, unsigned long value)
 507 {
 508         switch (regno) {
 509         case 0:
 510                 asm("mov %0, %%db0"     ::"r" (value));
 511                 break;
 512         case 1:
 513                 asm("mov %0, %%db1"     ::"r" (value));
 514                 break;
 515         case 2:
 516                 asm("mov %0, %%db2"     ::"r" (value));
 517                 break;
 518         case 3:
 519                 asm("mov %0, %%db3"     ::"r" (value));
 520                 break;
 521         case 6:
 522                 asm("mov %0, %%db6"     ::"r" (value));
 523                 break;
 524         case 7:
 525                 asm("mov %0, %%db7"     ::"r" (value));
 526                 break;
 527         default:
 528                 BUG();
 529         }
 530 }
 531
 532 /*
 533  * Set IOPL bits in EFLAGS from given mask
 534  */
 535 static inline void native_set_iopl_mask(unsigned mask)
 536 {
 537 #ifdef CONFIG_X86_32
 538         unsigned int reg;
 539
 540         asm volatile ("pushfl;"
 541                       "popl %0;"
 542                       "andl %1, %0;"
 543                       "orl %2, %0;"
 544                       "pushl %0;"
 545                       "popfl"
 546                       : "=&r" (reg)
 547                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 548 #endif
 549 }
 550
 551 static inline void
 552 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 553 {
 554         tss->x86_tss.sp0 = thread->sp0;
 555 #ifdef CONFIG_X86_32
 556         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 557         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 558                 tss->x86_tss.ss1 = thread->sysenter_cs;
 559                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 560         }
 561 #endif
 562 }
 563
 564 static inline void native_swapgs(void)
 565 {
 566 #ifdef CONFIG_X86_64
 567         asm volatile("swapgs" ::: "memory");
 568 #endif
 569 }
 570
 571 #ifdef CONFIG_PARAVIRT
 572 #include <asm/paravirt.h>
 573 #else
 574 #define __cpuid                 native_cpuid
 575 #define paravirt_enabled()      0
 576
 577 /*
 578  * These special macros can be used to get or set a debugging register
 579  */
 580 #define get_debugreg(var, register)                             \
 581         (var) = native_get_debugreg(register)
 582 #define set_debugreg(value, register)                           \
 583         native_set_debugreg(register, value)
 584
 585 static inline void load_sp0(struct tss_struct *tss,
 586                             struct thread_struct *thread)
 587 {
 588         native_load_sp0(tss, thread);
 589 }
 590
 591 #define set_iopl_mask native_set_iopl_mask
 592 #endif /* CONFIG_PARAVIRT */
 593
 594 /*
 595  * Save the cr4 feature set we're using (ie
 596  * Pentium 4MB enable and PPro Global page
 597  * enable), so that any CPU's that boot up
 598  * after us can get the correct flags.
 599  */
 600 extern unsigned long            mmu_cr4_features;
 601
 602 static inline void set_in_cr4(unsigned long mask)
 603 {
 604         unsigned long cr4;
 605
 606         mmu_cr4_features |= mask;
 607         cr4 = read_cr4();
 608         cr4 |= mask;
 609         write_cr4(cr4);
 610 }
 611
 612 static inline void clear_in_cr4(unsigned long mask)
 613 {
 614         unsigned long cr4;
 615
 616         mmu_cr4_features &= ~mask;
 617         cr4 = read_cr4();
 618         cr4 &= ~mask;
 619         write_cr4(cr4);
 620 }
 621
 622 typedef struct {
 623         unsigned long           seg;
 624 } mm_segment_t;
 625
 626
 627 /*
 628  * create a kernel thread without removing it from tasklists
 629  */
 630 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 631
 632 /* Free all resources held by a thread. */
 633 extern void release_thread(struct task_struct *);
 634
 635 /* Prepare to copy thread state - unlazy all lazy state */
 636 extern void prepare_to_copy(struct task_struct *tsk);
 637
 638 unsigned long get_wchan(struct task_struct *p);
 639
 640 /*
 641  * Generic CPUID function
 642  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 643  * resulting in stale register contents being returned.
 644  */
 645 static inline void cpuid(unsigned int op,
 646                          unsigned int *eax, unsigned int *ebx,
 647                          unsigned int *ecx, unsigned int *edx)
 648 {
 649         *eax = op;
 650         *ecx = 0;
 651         __cpuid(eax, ebx, ecx, edx);
 652 }
 653
 654 /* Some CPUID calls want 'count' to be placed in ecx */
 655 static inline void cpuid_count(unsigned int op, int count,
 656                                unsigned int *eax, unsigned int *ebx,
 657                                unsigned int *ecx, unsigned int *edx)
 658 {
 659         *eax = op;
 660         *ecx = count;
 661         __cpuid(eax, ebx, ecx, edx);
 662 }
 663
 664 /*
 665  * CPUID functions returning a single datum
 666  */
 667 static inline unsigned int cpuid_eax(unsigned int op)
 668 {
 669         unsigned int eax, ebx, ecx, edx;
 670
 671         cpuid(op, &eax, &ebx, &ecx, &edx);
 672
 673         return eax;
 674 }
 675
 676 static inline unsigned int cpuid_ebx(unsigned int op)
 677 {
 678         unsigned int eax, ebx, ecx, edx;
 679
 680         cpuid(op, &eax, &ebx, &ecx, &edx);
 681
 682         return ebx;
 683 }
 684
 685 static inline unsigned int cpuid_ecx(unsigned int op)
 686 {
 687         unsigned int eax, ebx, ecx, edx;
 688
 689         cpuid(op, &eax, &ebx, &ecx, &edx);
 690
 691         return ecx;
 692 }
 693
 694 static inline unsigned int cpuid_edx(unsigned int op)
 695 {
 696         unsigned int eax, ebx, ecx, edx;
 697
 698         cpuid(op, &eax, &ebx, &ecx, &edx);
 699
 700         return edx;
 701 }
 702
 703 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 704 static inline void rep_nop(void)
 705 {
 706         asm volatile("rep; nop" ::: "memory");
 707 }
 708
 709 static inline void cpu_relax(void)
 710 {
 711         rep_nop();
 712 }
 713
 714 /* Stop speculative execution and prefetching of modified code. */
 715 static inline void sync_core(void)
 716 {
 717         int tmp;
 718
 719 #if defined(CONFIG_M386) || defined(CONFIG_M486)
 720         if (boot_cpu_data.x86 < 5)
 721                 /* There is no speculative execution.
 722                  * jmp is a barrier to prefetching. */
 723                 asm volatile("jmp 1f\n1:\n" ::: "memory");
 724         else
 725 #endif
 726                 /* cpuid is a barrier to speculative execution.
 727                  * Prefetched instructions are automatically
 728                  * invalidated when modified. */
 729                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 730                              : "ebx", "ecx", "edx", "memory");
 731 }
 732
 733 static inline void __monitor(const void *eax, unsigned long ecx,
 734                              unsigned long edx)
 735 {
 736         /* "monitor %eax, %ecx, %edx;" */
 737         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 738                      :: "a" (eax), "c" (ecx), "d"(edx));
 739 }
 740
 741 static inline void __mwait(unsigned long eax, unsigned long ecx)
 742 {
 743         /* "mwait %eax, %ecx;" */
 744         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 745                      :: "a" (eax), "c" (ecx));
 746 }
 747
 748 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 749 {
 750         trace_hardirqs_on();
 751         /* "mwait %eax, %ecx;" */
 752         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 753                      :: "a" (eax), "c" (ecx));
 754 }
 755
 756 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 757 extern void init_amd_e400_c1e_mask(void);
 758
 759 extern unsigned long            boot_option_idle_override;
 760 extern bool                     amd_e400_c1e_detected;
 761
 762 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 763                          IDLE_POLL, IDLE_FORCE_MWAIT};
 764
 765 extern void enable_sep_cpu(void);
 766 extern int sysenter_setup(void);
 767
 768 extern void early_trap_init(void);
 769
 770 /* Defined in head.S */
 771 extern struct desc_ptr          early_gdt_descr;
 772
 773 extern void cpu_set_gdt(int);
 774 extern void switch_to_new_gdt(int);
 775 extern void load_percpu_segment(int);
 776 extern void cpu_init(void);
 777
 778 static inline unsigned long get_debugctlmsr(void)
 779 {
 780         unsigned long debugctlmsr = 0;
 781
 782 #ifndef CONFIG_X86_DEBUGCTLMSR
 783         if (boot_cpu_data.x86 < 6)
 784                 return 0;
 785 #endif
 786         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 787
 788         return debugctlmsr;
 789 }
 790
 791 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 792 {
 793 #ifndef CONFIG_X86_DEBUGCTLMSR
 794         if (boot_cpu_data.x86 < 6)
 795                 return;
 796 #endif
 797         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 798 }
 799
 800 /*
 801  * from system description table in BIOS. Mostly for MCA use, but
 802  * others may find it useful:
 803  */
 804 extern unsigned int             machine_id;
 805 extern unsigned int             machine_submodel_id;
 806 extern unsigned int             BIOS_revision;
 807
 808 /* Boot loader type from the setup header: */
 809 extern int                      bootloader_type;
 810 extern int                      bootloader_version;
 811
 812 extern char                     ignore_fpu_irq;
 813
 814 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 815 #define ARCH_HAS_PREFETCHW
 816 #define ARCH_HAS_SPINLOCK_PREFETCH
 817
 818 #ifdef CONFIG_X86_32
 819 # define BASE_PREFETCH          ASM_NOP4
 820 # define ARCH_HAS_PREFETCH
 821 #else
 822 # define BASE_PREFETCH          "prefetcht0 (%1)"
 823 #endif
 824
 825 /*
 826  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 827  *
 828  * It's not worth to care about 3dnow prefetches for the K6
 829  * because they are microcoded there and very slow.
 830  */
 831 static inline void prefetch(const void *x)
 832 {
 833         alternative_input(BASE_PREFETCH,
 834                           "prefetchnta (%1)",
 835                           X86_FEATURE_XMM,
 836                           "r" (x));
 837 }
 838
 839 /*
 840  * 3dnow prefetch to get an exclusive cache line.
 841  * Useful for spinlocks to avoid one state transition in the
 842  * cache coherency protocol:
 843  */
 844 static inline void prefetchw(const void *x)
 845 {
 846         alternative_input(BASE_PREFETCH,
 847                           "prefetchw (%1)",
 848                           X86_FEATURE_3DNOW,
 849                           "r" (x));
 850 }
 851
 852 static inline void spin_lock_prefetch(const void *x)
 853 {
 854         prefetchw(x);
 855 }
 856
 857 #ifdef CONFIG_X86_32
 858 /*
 859  * User space process size: 3GB (default).
 860  */
 861 #define TASK_SIZE               PAGE_OFFSET
 862 #define TASK_SIZE_MAX           TASK_SIZE
 863 #define STACK_TOP               TASK_SIZE
 864 #define STACK_TOP_MAX           STACK_TOP
 865
 866 #define INIT_THREAD  {                                                    \
 867         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 868         .vm86_info              = NULL,                                   \
 869         .sysenter_cs            = __KERNEL_CS,                            \
 870         .io_bitmap_ptr          = NULL,                                   \
 871 }
 872
 873 /*
 874  * Note that the .io_bitmap member must be extra-big. This is because
 875  * the CPU will access an additional byte beyond the end of the IO
 876  * permission bitmap. The extra byte must be all 1 bits, and must
 877  * be within the limit.
 878  */
 879 #define INIT_TSS  {                                                       \
 880         .x86_tss = {                                                      \
 881                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 882                 .ss0            = __KERNEL_DS,                            \
 883                 .ss1            = __KERNEL_CS,                            \
 884                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 885          },                                                               \
 886         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 887 }
 888
 889 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 890
 891 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 892 #define KSTK_TOP(info)                                                 \
 893 ({                                                                     \
 894        unsigned long *__ptr = (unsigned long *)(info);                 \
 895        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 896 })
 897
 898 /*
 899  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 900  * This is necessary to guarantee that the entire "struct pt_regs"
 901  * is accessible even if the CPU haven't stored the SS/ESP registers
 902  * on the stack (interrupt gate does not save these registers
 903  * when switching to the same priv ring).
 904  * Therefore beware: accessing the ss/esp fields of the
 905  * "struct pt_regs" is possible, but they may contain the
 906  * completely wrong values.
 907  */
 908 #define task_pt_regs(task)                                             \
 909 ({                                                                     \
 910        struct pt_regs *__regs__;                                       \
 911        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 912        __regs__ - 1;                                                   \
 913 })
 914
 915 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 916
 917 #else
 918 /*
 919  * User space process size. 47bits minus one guard page.
 920  */
 921 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 922
 923 /* This decides where the kernel will search for a free chunk of vm
 924  * space during mmap's.
 925  */
 926 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 927                                         0xc0000000 : 0xFFFFe000)
 928
 929 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 930                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 931 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 932                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 933
 934 #define STACK_TOP               TASK_SIZE
 935 #define STACK_TOP_MAX           TASK_SIZE_MAX
 936
 937 #define INIT_THREAD  { \
 938         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 939 }
 940
 941 #define INIT_TSS  { \
 942         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 943 }
 944
 945 /*
 946  * Return saved PC of a blocked thread.
 947  * What is this good for? it will be always the scheduler or ret_from_fork.
 948  */
 949 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 950
 951 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 952 extern unsigned long KSTK_ESP(struct task_struct *task);
 953 #endif /* CONFIG_X86_64 */
 954
 955 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 956                                                unsigned long new_sp);
 957
 958 /*
 959  * This decides where the kernel will search for a free chunk of vm
 960  * space during mmap's.
 961  */
 962 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 963
 964 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 965
 966 /* Get/set a process' ability to use the timestamp counter instruction */
 967 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 968 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 969
 970 extern int get_tsc_mode(unsigned long adr);
 971 extern int set_tsc_mode(unsigned int val);
 972
 973 extern int amd_get_nb_id(int cpu);
 974
 975 struct aperfmperf {
 976         u64 aperf, mperf;
 977 };
 978
 979 static inline void get_aperfmperf(struct aperfmperf *am)
 980 {
 981         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
 982
 983         rdmsrl(MSR_IA32_APERF, am->aperf);
 984         rdmsrl(MSR_IA32_MPERF, am->mperf);
 985 }
 986
 987 #define APERFMPERF_SHIFT 10
 988
 989 static inline
 990 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
 991                                     struct aperfmperf *new)
 992 {
 993         u64 aperf = new->aperf - old->aperf;
 994         u64 mperf = new->mperf - old->mperf;
 995         unsigned long ratio = aperf;
 996
 997         mperf >>= APERFMPERF_SHIFT;
 998         if (mperf)
 999                 ratio = div64_u64(aperf, mperf);
1000
1001         return ratio;
1002 }
1003
1004 /*
1005  * AMD errata checking
1006  */
1007 #ifdef CONFIG_CPU_SUP_AMD
1008 extern const int amd_erratum_383[];
1009 extern const int amd_erratum_400[];
1010 extern bool cpu_has_amd_erratum(const int *);
1011
1012 #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
1013 #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
1014 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1015         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1016 #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
1017 #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
1018 #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
1019
1020 #else
1021 #define cpu_has_amd_erratum(x)  (false)
1022 #endif /* CONFIG_CPU_SUP_AMD */
1023
1024 #endif /* _ASM_X86_PROCESSOR_H */