arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable_types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32
  33 #define HBP_NUM 4
  34 /*
  35  * Default implementation of macro that returns current
  36  * instruction pointer ("program counter").
  37  */
  38 static inline void *current_text_addr(void)
  39 {
  40         void *pc;
  41
  42         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  43
  44         return pc;
  45 }
  46
  47 #ifdef CONFIG_X86_VSMP
  48 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  49 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  50 #else
  51 # define ARCH_MIN_TASKALIGN             16
  52 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  53 #endif
  54
  55 /*
  56  *  CPU type and hardware bug flags. Kept separately for each CPU.
  57  *  Members of this structure are referenced in head.S, so think twice
  58  *  before touching them. [mj]
  59  */
  60
  61 struct cpuinfo_x86 {
  62         __u8                    x86;            /* CPU family */
  63         __u8                    x86_vendor;     /* CPU vendor */
  64         __u8                    x86_model;
  65         __u8                    x86_mask;
  66 #ifdef CONFIG_X86_32
  67         char                    wp_works_ok;    /* It doesn't on 386's */
  68
  69         /* Problems on some 486Dx4's and old 386's: */
  70         char                    hlt_works_ok;
  71         char                    hard_math;
  72         char                    rfu;
  73         char                    fdiv_bug;
  74         char                    f00f_bug;
  75         char                    coma_bug;
  76         char                    pad0;
  77 #else
  78         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  79         int                     x86_tlbsize;
  80 #endif
  81         __u8                    x86_virt_bits;
  82         __u8                    x86_phys_bits;
  83         /* CPUID returned core id bits: */
  84         __u8                    x86_coreid_bits;
  85         /* Max extended CPUID function supported: */
  86         __u32                   extended_cpuid_level;
  87         /* Maximum supported CPUID level, -1=no CPUID: */
  88         int                     cpuid_level;
  89         __u32                   x86_capability[NCAPINTS];
  90         char                    x86_vendor_id[16];
  91         char                    x86_model_id[64];
  92         /* in KB - valid for CPUS which support this call: */
  93         int                     x86_cache_size;
  94         int                     x86_cache_alignment;    /* In bytes */
  95         int                     x86_power;
  96         unsigned long           loops_per_jiffy;
  97         /* cpuid returned max cores value: */
  98         u16                      x86_max_cores;
  99         u16                     apicid;
 100         u16                     initial_apicid;
 101         u16                     x86_clflush_size;
 102         /* number of cores as seen by the OS: */
 103         u16                     booted_cores;
 104         /* Physical processor id: */
 105         u16                     phys_proc_id;
 106         /* Core id: */
 107         u16                     cpu_core_id;
 108         /* Compute unit id */
 109         u8                      compute_unit_id;
 110         /* Index into per_cpu list: */
 111         u16                     cpu_index;
 112         u32                     microcode;
 113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 114
 115 #define X86_VENDOR_INTEL        0
 116 #define X86_VENDOR_CYRIX        1
 117 #define X86_VENDOR_AMD          2
 118 #define X86_VENDOR_UMC          3
 119 #define X86_VENDOR_CENTAUR      5
 120 #define X86_VENDOR_TRANSMETA    7
 121 #define X86_VENDOR_NSC          8
 122 #define X86_VENDOR_NUM          9
 123
 124 #define X86_VENDOR_UNKNOWN      0xff
 125
 126 /*
 127  * capabilities of CPUs
 128  */
 129 extern struct cpuinfo_x86       boot_cpu_data;
 130 extern struct cpuinfo_x86       new_cpu_data;
 131
 132 extern struct tss_struct        doublefault_tss;
 133 extern __u32                    cpu_caps_cleared[NCAPINTS];
 134 extern __u32                    cpu_caps_set[NCAPINTS];
 135
 136 #ifdef CONFIG_SMP
 137 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 138 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 139 #else
 140 #define cpu_info                boot_cpu_data
 141 #define cpu_data(cpu)           boot_cpu_data
 142 #endif
 143
 144 extern const struct seq_operations cpuinfo_op;
 145
 146 static inline int hlt_works(int cpu)
 147 {
 148 #ifdef CONFIG_X86_32
 149         return cpu_data(cpu).hlt_works_ok;
 150 #else
 151         return 1;
 152 #endif
 153 }
 154
 155 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 156
 157 extern void cpu_detect(struct cpuinfo_x86 *c);
 158
 159 extern struct pt_regs *idle_regs(struct pt_regs *);
 160
 161 extern void early_cpu_init(void);
 162 extern void identify_boot_cpu(void);
 163 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 164 extern void print_cpu_info(struct cpuinfo_x86 *);
 165 void print_cpu_msr(struct cpuinfo_x86 *);
 166 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 167 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 168 extern unsigned short num_cache_leaves;
 169
 170 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 171 extern void detect_ht(struct cpuinfo_x86 *c);
 172
 173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 174                                 unsigned int *ecx, unsigned int *edx)
 175 {
 176         /* ecx is often an input as well as an output. */
 177         asm volatile("cpuid"
 178             : "=a" (*eax),
 179               "=b" (*ebx),
 180               "=c" (*ecx),
 181               "=d" (*edx)
 182             : "0" (*eax), "2" (*ecx)
 183             : "memory");
 184 }
 185
 186 static inline void load_cr3(pgd_t *pgdir)
 187 {
 188         write_cr3(__pa(pgdir));
 189 }
 190
 191 #ifdef CONFIG_X86_32
 192 /* This is the TSS defined by the hardware. */
 193 struct x86_hw_tss {
 194         unsigned short          back_link, __blh;
 195         unsigned long           sp0;
 196         unsigned short          ss0, __ss0h;
 197         unsigned long           sp1;
 198         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 199         unsigned short          ss1, __ss1h;
 200         unsigned long           sp2;
 201         unsigned short          ss2, __ss2h;
 202         unsigned long           __cr3;
 203         unsigned long           ip;
 204         unsigned long           flags;
 205         unsigned long           ax;
 206         unsigned long           cx;
 207         unsigned long           dx;
 208         unsigned long           bx;
 209         unsigned long           sp;
 210         unsigned long           bp;
 211         unsigned long           si;
 212         unsigned long           di;
 213         unsigned short          es, __esh;
 214         unsigned short          cs, __csh;
 215         unsigned short          ss, __ssh;
 216         unsigned short          ds, __dsh;
 217         unsigned short          fs, __fsh;
 218         unsigned short          gs, __gsh;
 219         unsigned short          ldt, __ldth;
 220         unsigned short          trace;
 221         unsigned short          io_bitmap_base;
 222
 223 } __attribute__((packed));
 224 #else
 225 struct x86_hw_tss {
 226         u32                     reserved1;
 227         u64                     sp0;
 228         u64                     sp1;
 229         u64                     sp2;
 230         u64                     reserved2;
 231         u64                     ist[7];
 232         u32                     reserved3;
 233         u32                     reserved4;
 234         u16                     reserved5;
 235         u16                     io_bitmap_base;
 236
 237 } __attribute__((packed)) ____cacheline_aligned;
 238 #endif
 239
 240 /*
 241  * IO-bitmap sizes:
 242  */
 243 #define IO_BITMAP_BITS                  65536
 244 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 245 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 246 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 247 #define INVALID_IO_BITMAP_OFFSET        0x8000
 248
 249 struct tss_struct {
 250         /*
 251          * The hardware state:
 252          */
 253         struct x86_hw_tss       x86_tss;
 254
 255         /*
 256          * The extra 1 is there because the CPU will access an
 257          * additional byte beyond the end of the IO permission
 258          * bitmap. The extra byte must be all 1 bits, and must
 259          * be within the limit.
 260          */
 261         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 262
 263         /*
 264          * .. and then another 0x100 bytes for the emergency kernel stack:
 265          */
 266         unsigned long           stack[64];
 267
 268 } ____cacheline_aligned;
 269
 270 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 271
 272 /*
 273  * Save the original ist values for checking stack pointers during debugging
 274  */
 275 struct orig_ist {
 276         unsigned long           ist[7];
 277 };
 278
 279 #define MXCSR_DEFAULT           0x1f80
 280
 281 struct i387_fsave_struct {
 282         u32                     cwd;    /* FPU Control Word             */
 283         u32                     swd;    /* FPU Status Word              */
 284         u32                     twd;    /* FPU Tag Word                 */
 285         u32                     fip;    /* FPU IP Offset                */
 286         u32                     fcs;    /* FPU IP Selector              */
 287         u32                     foo;    /* FPU Operand Pointer Offset   */
 288         u32                     fos;    /* FPU Operand Pointer Selector */
 289
 290         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 291         u32                     st_space[20];
 292
 293         /* Software status information [not touched by FSAVE ]:         */
 294         u32                     status;
 295 };
 296
 297 struct i387_fxsave_struct {
 298         u16                     cwd; /* Control Word                    */
 299         u16                     swd; /* Status Word                     */
 300         u16                     twd; /* Tag Word                        */
 301         u16                     fop; /* Last Instruction Opcode         */
 302         union {
 303                 struct {
 304                         u64     rip; /* Instruction Pointer             */
 305                         u64     rdp; /* Data Pointer                    */
 306                 };
 307                 struct {
 308                         u32     fip; /* FPU IP Offset                   */
 309                         u32     fcs; /* FPU IP Selector                 */
 310                         u32     foo; /* FPU Operand Offset              */
 311                         u32     fos; /* FPU Operand Selector            */
 312                 };
 313         };
 314         u32                     mxcsr;          /* MXCSR Register State */
 315         u32                     mxcsr_mask;     /* MXCSR Mask           */
 316
 317         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 318         u32                     st_space[32];
 319
 320         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 321         u32                     xmm_space[64];
 322
 323         u32                     padding[12];
 324
 325         union {
 326                 u32             padding1[12];
 327                 u32             sw_reserved[12];
 328         };
 329
 330 } __attribute__((aligned(16)));
 331
 332 struct i387_soft_struct {
 333         u32                     cwd;
 334         u32                     swd;
 335         u32                     twd;
 336         u32                     fip;
 337         u32                     fcs;
 338         u32                     foo;
 339         u32                     fos;
 340         /* 8*10 bytes for each FP-reg = 80 bytes: */
 341         u32                     st_space[20];
 342         u8                      ftop;
 343         u8                      changed;
 344         u8                      lookahead;
 345         u8                      no_update;
 346         u8                      rm;
 347         u8                      alimit;
 348         struct math_emu_info    *info;
 349         u32                     entry_eip;
 350 };
 351
 352 struct ymmh_struct {
 353         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 354         u32 ymmh_space[64];
 355 };
 356
 357 struct xsave_hdr_struct {
 358         u64 xstate_bv;
 359         u64 reserved1[2];
 360         u64 reserved2[5];
 361 } __attribute__((packed));
 362
 363 struct xsave_struct {
 364         struct i387_fxsave_struct i387;
 365         struct xsave_hdr_struct xsave_hdr;
 366         struct ymmh_struct ymmh;
 367         /* new processor state extensions will go here */
 368 } __attribute__ ((packed, aligned (64)));
 369
 370 union thread_xstate {
 371         struct i387_fsave_struct        fsave;
 372         struct i387_fxsave_struct       fxsave;
 373         struct i387_soft_struct         soft;
 374         struct xsave_struct             xsave;
 375 };
 376
 377 struct fpu {
 378         unsigned int last_cpu;
 379         unsigned int has_fpu;
 380         union thread_xstate *state;
 381 };
 382
 383 #ifdef CONFIG_X86_64
 384 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 385
 386 union irq_stack_union {
 387         char irq_stack[IRQ_STACK_SIZE];
 388         /*
 389          * GCC hardcodes the stack canary as %gs:40.  Since the
 390          * irq_stack is the object at %gs:0, we reserve the bottom
 391          * 48 bytes of the irq stack for the canary.
 392          */
 393         struct {
 394                 char gs_base[40];
 395                 unsigned long stack_canary;
 396         };
 397 };
 398
 399 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 400 DECLARE_INIT_PER_CPU(irq_stack_union);
 401
 402 DECLARE_PER_CPU(char *, irq_stack_ptr);
 403 DECLARE_PER_CPU(unsigned int, irq_count);
 404 extern unsigned long kernel_eflags;
 405 extern asmlinkage void ignore_sysret(void);
 406 #else   /* X86_64 */
 407 #ifdef CONFIG_CC_STACKPROTECTOR
 408 /*
 409  * Make sure stack canary segment base is cached-aligned:
 410  *   "For Intel Atom processors, avoid non zero segment base address
 411  *    that is not aligned to cache line boundary at all cost."
 412  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 413  */
 414 struct stack_canary {
 415         char __pad[20];         /* canary at %gs:20 */
 416         unsigned long canary;
 417 };
 418 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 419 #endif
 420 #endif  /* X86_64 */
 421
 422 extern unsigned int xstate_size;
 423 extern void free_thread_xstate(struct task_struct *);
 424 extern struct kmem_cache *task_xstate_cachep;
 425
 426 struct perf_event;
 427
 428 struct thread_struct {
 429         /* Cached TLS descriptors: */
 430         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 431         unsigned long           sp0;
 432         unsigned long           sp;
 433 #ifdef CONFIG_X86_32
 434         unsigned long           sysenter_cs;
 435 #else
 436         unsigned long           usersp; /* Copy from PDA */
 437         unsigned short          es;
 438         unsigned short          ds;
 439         unsigned short          fsindex;
 440         unsigned short          gsindex;
 441 #endif
 442 #ifdef CONFIG_X86_32
 443         unsigned long           ip;
 444 #endif
 445 #ifdef CONFIG_X86_64
 446         unsigned long           fs;
 447 #endif
 448         unsigned long           gs;
 449         /* Save middle states of ptrace breakpoints */
 450         struct perf_event       *ptrace_bps[HBP_NUM];
 451         /* Debug status used for traps, single steps, etc... */
 452         unsigned long           debugreg6;
 453         /* Keep track of the exact dr7 value set by the user */
 454         unsigned long           ptrace_dr7;
 455         /* Fault info: */
 456         unsigned long           cr2;
 457         unsigned long           trap_no;
 458         unsigned long           error_code;
 459         /* floating point and extended processor state */
 460         struct fpu              fpu;
 461 #ifdef CONFIG_X86_32
 462         /* Virtual 86 mode info */
 463         struct vm86_struct __user *vm86_info;
 464         unsigned long           screen_bitmap;
 465         unsigned long           v86flags;
 466         unsigned long           v86mask;
 467         unsigned long           saved_sp0;
 468         unsigned int            saved_fs;
 469         unsigned int            saved_gs;
 470 #endif
 471         /* IO permissions: */
 472         unsigned long           *io_bitmap_ptr;
 473         unsigned long           iopl;
 474         /* Max allowed port in the bitmap, in bytes: */
 475         unsigned                io_bitmap_max;
 476 };
 477
 478 static inline unsigned long native_get_debugreg(int regno)
 479 {
 480         unsigned long val = 0;  /* Damn you, gcc! */
 481
 482         switch (regno) {
 483         case 0:
 484                 asm("mov %%db0, %0" :"=r" (val));
 485                 break;
 486         case 1:
 487                 asm("mov %%db1, %0" :"=r" (val));
 488                 break;
 489         case 2:
 490                 asm("mov %%db2, %0" :"=r" (val));
 491                 break;
 492         case 3:
 493                 asm("mov %%db3, %0" :"=r" (val));
 494                 break;
 495         case 6:
 496                 asm("mov %%db6, %0" :"=r" (val));
 497                 break;
 498         case 7:
 499                 asm("mov %%db7, %0" :"=r" (val));
 500                 break;
 501         default:
 502                 BUG();
 503         }
 504         return val;
 505 }
 506
 507 static inline void native_set_debugreg(int regno, unsigned long value)
 508 {
 509         switch (regno) {
 510         case 0:
 511                 asm("mov %0, %%db0"     ::"r" (value));
 512                 break;
 513         case 1:
 514                 asm("mov %0, %%db1"     ::"r" (value));
 515                 break;
 516         case 2:
 517                 asm("mov %0, %%db2"     ::"r" (value));
 518                 break;
 519         case 3:
 520                 asm("mov %0, %%db3"     ::"r" (value));
 521                 break;
 522         case 6:
 523                 asm("mov %0, %%db6"     ::"r" (value));
 524                 break;
 525         case 7:
 526                 asm("mov %0, %%db7"     ::"r" (value));
 527                 break;
 528         default:
 529                 BUG();
 530         }
 531 }
 532
 533 /*
 534  * Set IOPL bits in EFLAGS from given mask
 535  */
 536 static inline void native_set_iopl_mask(unsigned mask)
 537 {
 538 #ifdef CONFIG_X86_32
 539         unsigned int reg;
 540
 541         asm volatile ("pushfl;"
 542                       "popl %0;"
 543                       "andl %1, %0;"
 544                       "orl %2, %0;"
 545                       "pushl %0;"
 546                       "popfl"
 547                       : "=&r" (reg)
 548                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 549 #endif
 550 }
 551
 552 static inline void
 553 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 554 {
 555         tss->x86_tss.sp0 = thread->sp0;
 556 #ifdef CONFIG_X86_32
 557         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 558         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 559                 tss->x86_tss.ss1 = thread->sysenter_cs;
 560                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 561         }
 562 #endif
 563 }
 564
 565 static inline void native_swapgs(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         asm volatile("swapgs" ::: "memory");
 569 #endif
 570 }
 571
 572 #ifdef CONFIG_PARAVIRT
 573 #include <asm/paravirt.h>
 574 #else
 575 #define __cpuid                 native_cpuid
 576 #define paravirt_enabled()      0
 577
 578 /*
 579  * These special macros can be used to get or set a debugging register
 580  */
 581 #define get_debugreg(var, register)                             \
 582         (var) = native_get_debugreg(register)
 583 #define set_debugreg(value, register)                           \
 584         native_set_debugreg(register, value)
 585
 586 static inline void load_sp0(struct tss_struct *tss,
 587                             struct thread_struct *thread)
 588 {
 589         native_load_sp0(tss, thread);
 590 }
 591
 592 #define set_iopl_mask native_set_iopl_mask
 593 #endif /* CONFIG_PARAVIRT */
 594
 595 /*
 596  * Save the cr4 feature set we're using (ie
 597  * Pentium 4MB enable and PPro Global page
 598  * enable), so that any CPU's that boot up
 599  * after us can get the correct flags.
 600  */
 601 extern unsigned long            mmu_cr4_features;
 602
 603 static inline void set_in_cr4(unsigned long mask)
 604 {
 605         unsigned long cr4;
 606
 607         mmu_cr4_features |= mask;
 608         cr4 = read_cr4();
 609         cr4 |= mask;
 610         write_cr4(cr4);
 611 }
 612
 613 static inline void clear_in_cr4(unsigned long mask)
 614 {
 615         unsigned long cr4;
 616
 617         mmu_cr4_features &= ~mask;
 618         cr4 = read_cr4();
 619         cr4 &= ~mask;
 620         write_cr4(cr4);
 621 }
 622
 623 typedef struct {
 624         unsigned long           seg;
 625 } mm_segment_t;
 626
 627
 628 /*
 629  * create a kernel thread without removing it from tasklists
 630  */
 631 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 632
 633 /* Free all resources held by a thread. */
 634 extern void release_thread(struct task_struct *);
 635
 636 /* Prepare to copy thread state - unlazy all lazy state */
 637 extern void prepare_to_copy(struct task_struct *tsk);
 638
 639 unsigned long get_wchan(struct task_struct *p);
 640
 641 /*
 642  * Generic CPUID function
 643  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 644  * resulting in stale register contents being returned.
 645  */
 646 static inline void cpuid(unsigned int op,
 647                          unsigned int *eax, unsigned int *ebx,
 648                          unsigned int *ecx, unsigned int *edx)
 649 {
 650         *eax = op;
 651         *ecx = 0;
 652         __cpuid(eax, ebx, ecx, edx);
 653 }
 654
 655 /* Some CPUID calls want 'count' to be placed in ecx */
 656 static inline void cpuid_count(unsigned int op, int count,
 657                                unsigned int *eax, unsigned int *ebx,
 658                                unsigned int *ecx, unsigned int *edx)
 659 {
 660         *eax = op;
 661         *ecx = count;
 662         __cpuid(eax, ebx, ecx, edx);
 663 }
 664
 665 /*
 666  * CPUID functions returning a single datum
 667  */
 668 static inline unsigned int cpuid_eax(unsigned int op)
 669 {
 670         unsigned int eax, ebx, ecx, edx;
 671
 672         cpuid(op, &eax, &ebx, &ecx, &edx);
 673
 674         return eax;
 675 }
 676
 677 static inline unsigned int cpuid_ebx(unsigned int op)
 678 {
 679         unsigned int eax, ebx, ecx, edx;
 680
 681         cpuid(op, &eax, &ebx, &ecx, &edx);
 682
 683         return ebx;
 684 }
 685
 686 static inline unsigned int cpuid_ecx(unsigned int op)
 687 {
 688         unsigned int eax, ebx, ecx, edx;
 689
 690         cpuid(op, &eax, &ebx, &ecx, &edx);
 691
 692         return ecx;
 693 }
 694
 695 static inline unsigned int cpuid_edx(unsigned int op)
 696 {
 697         unsigned int eax, ebx, ecx, edx;
 698
 699         cpuid(op, &eax, &ebx, &ecx, &edx);
 700
 701         return edx;
 702 }
 703
 704 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 705 static inline void rep_nop(void)
 706 {
 707         asm volatile("rep; nop" ::: "memory");
 708 }
 709
 710 static inline void cpu_relax(void)
 711 {
 712         rep_nop();
 713 }
 714
 715 /* Stop speculative execution and prefetching of modified code. */
 716 static inline void sync_core(void)
 717 {
 718         int tmp;
 719
 720 #if defined(CONFIG_M386) || defined(CONFIG_M486)
 721         if (boot_cpu_data.x86 < 5)
 722                 /* There is no speculative execution.
 723                  * jmp is a barrier to prefetching. */
 724                 asm volatile("jmp 1f\n1:\n" ::: "memory");
 725         else
 726 #endif
 727                 /* cpuid is a barrier to speculative execution.
 728                  * Prefetched instructions are automatically
 729                  * invalidated when modified. */
 730                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 731                              : "ebx", "ecx", "edx", "memory");
 732 }
 733
 734 static inline void __monitor(const void *eax, unsigned long ecx,
 735                              unsigned long edx)
 736 {
 737         /* "monitor %eax, %ecx, %edx;" */
 738         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 739                      :: "a" (eax), "c" (ecx), "d"(edx));
 740 }
 741
 742 static inline void __mwait(unsigned long eax, unsigned long ecx)
 743 {
 744         /* "mwait %eax, %ecx;" */
 745         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 746                      :: "a" (eax), "c" (ecx));
 747 }
 748
 749 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 750 {
 751         trace_hardirqs_on();
 752         /* "mwait %eax, %ecx;" */
 753         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 754                      :: "a" (eax), "c" (ecx));
 755 }
 756
 757 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 758 extern void init_amd_e400_c1e_mask(void);
 759
 760 extern unsigned long            boot_option_idle_override;
 761 extern bool                     amd_e400_c1e_detected;
 762
 763 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 764                          IDLE_POLL, IDLE_FORCE_MWAIT};
 765
 766 extern void enable_sep_cpu(void);
 767 extern int sysenter_setup(void);
 768
 769 extern void early_trap_init(void);
 770
 771 /* Defined in head.S */
 772 extern struct desc_ptr          early_gdt_descr;
 773
 774 extern void cpu_set_gdt(int);
 775 extern void switch_to_new_gdt(int);
 776 extern void load_percpu_segment(int);
 777 extern void cpu_init(void);
 778
 779 static inline unsigned long get_debugctlmsr(void)
 780 {
 781         unsigned long debugctlmsr = 0;
 782
 783 #ifndef CONFIG_X86_DEBUGCTLMSR
 784         if (boot_cpu_data.x86 < 6)
 785                 return 0;
 786 #endif
 787         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 788
 789         return debugctlmsr;
 790 }
 791
 792 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 793 {
 794 #ifndef CONFIG_X86_DEBUGCTLMSR
 795         if (boot_cpu_data.x86 < 6)
 796                 return;
 797 #endif
 798         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 799 }
 800
 801 /*
 802  * from system description table in BIOS. Mostly for MCA use, but
 803  * others may find it useful:
 804  */
 805 extern unsigned int             machine_id;
 806 extern unsigned int             machine_submodel_id;
 807 extern unsigned int             BIOS_revision;
 808
 809 /* Boot loader type from the setup header: */
 810 extern int                      bootloader_type;
 811 extern int                      bootloader_version;
 812
 813 extern char                     ignore_fpu_irq;
 814
 815 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 816 #define ARCH_HAS_PREFETCHW
 817 #define ARCH_HAS_SPINLOCK_PREFETCH
 818
 819 #ifdef CONFIG_X86_32
 820 # define BASE_PREFETCH          ASM_NOP4
 821 # define ARCH_HAS_PREFETCH
 822 #else
 823 # define BASE_PREFETCH          "prefetcht0 (%1)"
 824 #endif
 825
 826 /*
 827  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 828  *
 829  * It's not worth to care about 3dnow prefetches for the K6
 830  * because they are microcoded there and very slow.
 831  */
 832 static inline void prefetch(const void *x)
 833 {
 834         alternative_input(BASE_PREFETCH,
 835                           "prefetchnta (%1)",
 836                           X86_FEATURE_XMM,
 837                           "r" (x));
 838 }
 839
 840 /*
 841  * 3dnow prefetch to get an exclusive cache line.
 842  * Useful for spinlocks to avoid one state transition in the
 843  * cache coherency protocol:
 844  */
 845 static inline void prefetchw(const void *x)
 846 {
 847         alternative_input(BASE_PREFETCH,
 848                           "prefetchw (%1)",
 849                           X86_FEATURE_3DNOW,
 850                           "r" (x));
 851 }
 852
 853 static inline void spin_lock_prefetch(const void *x)
 854 {
 855         prefetchw(x);
 856 }
 857
 858 #ifdef CONFIG_X86_32
 859 /*
 860  * User space process size: 3GB (default).
 861  */
 862 #define TASK_SIZE               PAGE_OFFSET
 863 #define TASK_SIZE_MAX           TASK_SIZE
 864 #define STACK_TOP               TASK_SIZE
 865 #define STACK_TOP_MAX           STACK_TOP
 866
 867 #define INIT_THREAD  {                                                    \
 868         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 869         .vm86_info              = NULL,                                   \
 870         .sysenter_cs            = __KERNEL_CS,                            \
 871         .io_bitmap_ptr          = NULL,                                   \
 872 }
 873
 874 /*
 875  * Note that the .io_bitmap member must be extra-big. This is because
 876  * the CPU will access an additional byte beyond the end of the IO
 877  * permission bitmap. The extra byte must be all 1 bits, and must
 878  * be within the limit.
 879  */
 880 #define INIT_TSS  {                                                       \
 881         .x86_tss = {                                                      \
 882                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 883                 .ss0            = __KERNEL_DS,                            \
 884                 .ss1            = __KERNEL_CS,                            \
 885                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 886          },                                                               \
 887         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 888 }
 889
 890 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 891
 892 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 893 #define KSTK_TOP(info)                                                 \
 894 ({                                                                     \
 895        unsigned long *__ptr = (unsigned long *)(info);                 \
 896        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 897 })
 898
 899 /*
 900  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 901  * This is necessary to guarantee that the entire "struct pt_regs"
 902  * is accessible even if the CPU haven't stored the SS/ESP registers
 903  * on the stack (interrupt gate does not save these registers
 904  * when switching to the same priv ring).
 905  * Therefore beware: accessing the ss/esp fields of the
 906  * "struct pt_regs" is possible, but they may contain the
 907  * completely wrong values.
 908  */
 909 #define task_pt_regs(task)                                             \
 910 ({                                                                     \
 911        struct pt_regs *__regs__;                                       \
 912        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 913        __regs__ - 1;                                                   \
 914 })
 915
 916 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 917
 918 #else
 919 /*
 920  * User space process size. 47bits minus one guard page.
 921  */
 922 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 923
 924 /* This decides where the kernel will search for a free chunk of vm
 925  * space during mmap's.
 926  */
 927 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 928                                         0xc0000000 : 0xFFFFe000)
 929
 930 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 931                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 932 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 933                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 934
 935 #define STACK_TOP               TASK_SIZE
 936 #define STACK_TOP_MAX           TASK_SIZE_MAX
 937
 938 #define INIT_THREAD  { \
 939         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 940 }
 941
 942 #define INIT_TSS  { \
 943         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 944 }
 945
 946 /*
 947  * Return saved PC of a blocked thread.
 948  * What is this good for? it will be always the scheduler or ret_from_fork.
 949  */
 950 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 951
 952 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 953 extern unsigned long KSTK_ESP(struct task_struct *task);
 954 #endif /* CONFIG_X86_64 */
 955
 956 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 957                                                unsigned long new_sp);
 958
 959 /*
 960  * This decides where the kernel will search for a free chunk of vm
 961  * space during mmap's.
 962  */
 963 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 964
 965 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 966
 967 /* Get/set a process' ability to use the timestamp counter instruction */
 968 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 969 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 970
 971 extern int get_tsc_mode(unsigned long adr);
 972 extern int set_tsc_mode(unsigned int val);
 973
 974 extern int amd_get_nb_id(int cpu);
 975
 976 struct aperfmperf {
 977         u64 aperf, mperf;
 978 };
 979
 980 static inline void get_aperfmperf(struct aperfmperf *am)
 981 {
 982         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
 983
 984         rdmsrl(MSR_IA32_APERF, am->aperf);
 985         rdmsrl(MSR_IA32_MPERF, am->mperf);
 986 }
 987
 988 #define APERFMPERF_SHIFT 10
 989
 990 static inline
 991 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
 992                                     struct aperfmperf *new)
 993 {
 994         u64 aperf = new->aperf - old->aperf;
 995         u64 mperf = new->mperf - old->mperf;
 996         unsigned long ratio = aperf;
 997
 998         mperf >>= APERFMPERF_SHIFT;
 999         if (mperf)
1000                 ratio = div64_u64(aperf, mperf);
1001
1002         return ratio;
1003 }
1004
1005 /*
1006  * AMD errata checking
1007  */
1008 #ifdef CONFIG_CPU_SUP_AMD
1009 extern const int amd_erratum_383[];
1010 extern const int amd_erratum_400[];
1011 extern bool cpu_has_amd_erratum(const int *);
1012
1013 #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
1014 #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
1015 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1016         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1017 #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
1018 #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
1019 #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
1020
1021 #else
1022 #define cpu_has_amd_erratum(x)  (false)
1023 #endif /* CONFIG_CPU_SUP_AMD */
1024
1025 #endif /* _ASM_X86_PROCESSOR_H */