arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable_types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32
  33 #define HBP_NUM 4
  34 /*
  35  * Default implementation of macro that returns current
  36  * instruction pointer ("program counter").
  37  */
  38 static inline void *current_text_addr(void)
  39 {
  40         void *pc;
  41
  42         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  43
  44         return pc;
  45 }
  46
  47 #ifdef CONFIG_X86_VSMP
  48 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  49 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  50 #else
  51 # define ARCH_MIN_TASKALIGN             16
  52 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  53 #endif
  54
  55 /*
  56  *  CPU type and hardware bug flags. Kept separately for each CPU.
  57  *  Members of this structure are referenced in head.S, so think twice
  58  *  before touching them. [mj]
  59  */
  60
  61 struct cpuinfo_x86 {
  62         __u8                    x86;            /* CPU family */
  63         __u8                    x86_vendor;     /* CPU vendor */
  64         __u8                    x86_model;
  65         __u8                    x86_mask;
  66 #ifdef CONFIG_X86_32
  67         char                    wp_works_ok;    /* It doesn't on 386's */
  68
  69         /* Problems on some 486Dx4's and old 386's: */
  70         char                    hlt_works_ok;
  71         char                    hard_math;
  72         char                    rfu;
  73         char                    fdiv_bug;
  74         char                    f00f_bug;
  75         char                    coma_bug;
  76         char                    pad0;
  77 #else
  78         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  79         int                     x86_tlbsize;
  80 #endif
  81         __u8                    x86_virt_bits;
  82         __u8                    x86_phys_bits;
  83         /* CPUID returned core id bits: */
  84         __u8                    x86_coreid_bits;
  85         /* Max extended CPUID function supported: */
  86         __u32                   extended_cpuid_level;
  87         /* Maximum supported CPUID level, -1=no CPUID: */
  88         int                     cpuid_level;
  89         __u32                   x86_capability[NCAPINTS];
  90         char                    x86_vendor_id[16];
  91         char                    x86_model_id[64];
  92         /* in KB - valid for CPUS which support this call: */
  93         int                     x86_cache_size;
  94         int                     x86_cache_alignment;    /* In bytes */
  95         int                     x86_power;
  96         unsigned long           loops_per_jiffy;
  97         /* cpuid returned max cores value: */
  98         u16                      x86_max_cores;
  99         u16                     apicid;
 100         u16                     initial_apicid;
 101         u16                     x86_clflush_size;
 102         /* number of cores as seen by the OS: */
 103         u16                     booted_cores;
 104         /* Physical processor id: */
 105         u16                     phys_proc_id;
 106         /* Core id: */
 107         u16                     cpu_core_id;
 108         /* Compute unit id */
 109         u8                      compute_unit_id;
 110         /* Index into per_cpu list: */
 111         u16                     cpu_index;
 112         u32                     microcode;
 113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 114
 115 #define X86_VENDOR_INTEL        0
 116 #define X86_VENDOR_CYRIX        1
 117 #define X86_VENDOR_AMD          2
 118 #define X86_VENDOR_UMC          3
 119 #define X86_VENDOR_CENTAUR      5
 120 #define X86_VENDOR_TRANSMETA    7
 121 #define X86_VENDOR_NSC          8
 122 #define X86_VENDOR_NUM          9
 123
 124 #define X86_VENDOR_UNKNOWN      0xff
 125
 126 /*
 127  * capabilities of CPUs
 128  */
 129 extern struct cpuinfo_x86       boot_cpu_data;
 130 extern struct cpuinfo_x86       new_cpu_data;
 131
 132 extern struct tss_struct        doublefault_tss;
 133 extern __u32                    cpu_caps_cleared[NCAPINTS];
 134 extern __u32                    cpu_caps_set[NCAPINTS];
 135
 136 #ifdef CONFIG_SMP
 137 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 138 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 139 #else
 140 #define cpu_info                boot_cpu_data
 141 #define cpu_data(cpu)           boot_cpu_data
 142 #endif
 143
 144 extern const struct seq_operations cpuinfo_op;
 145
 146 static inline int hlt_works(int cpu)
 147 {
 148 #ifdef CONFIG_X86_32
 149         return cpu_data(cpu).hlt_works_ok;
 150 #else
 151         return 1;
 152 #endif
 153 }
 154
 155 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 156
 157 extern void cpu_detect(struct cpuinfo_x86 *c);
 158
 159 extern struct pt_regs *idle_regs(struct pt_regs *);
 160
 161 extern void early_cpu_init(void);
 162 extern void identify_boot_cpu(void);
 163 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 164 extern void print_cpu_info(struct cpuinfo_x86 *);
 165 void print_cpu_msr(struct cpuinfo_x86 *);
 166 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 167 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 168 extern unsigned short num_cache_leaves;
 169
 170 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 171 extern void detect_ht(struct cpuinfo_x86 *c);
 172
 173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 174                                 unsigned int *ecx, unsigned int *edx)
 175 {
 176         /* ecx is often an input as well as an output. */
 177         asm volatile("cpuid"
 178             : "=a" (*eax),
 179               "=b" (*ebx),
 180               "=c" (*ecx),
 181               "=d" (*edx)
 182             : "0" (*eax), "2" (*ecx)
 183             : "memory");
 184 }
 185
 186 static inline void load_cr3(pgd_t *pgdir)
 187 {
 188         write_cr3(__pa(pgdir));
 189 }
 190
 191 #ifdef CONFIG_X86_32
 192 /* This is the TSS defined by the hardware. */
 193 struct x86_hw_tss {
 194         unsigned short          back_link, __blh;
 195         unsigned long           sp0;
 196         unsigned short          ss0, __ss0h;
 197         unsigned long           sp1;
 198         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 199         unsigned short          ss1, __ss1h;
 200         unsigned long           sp2;
 201         unsigned short          ss2, __ss2h;
 202         unsigned long           __cr3;
 203         unsigned long           ip;
 204         unsigned long           flags;
 205         unsigned long           ax;
 206         unsigned long           cx;
 207         unsigned long           dx;
 208         unsigned long           bx;
 209         unsigned long           sp;
 210         unsigned long           bp;
 211         unsigned long           si;
 212         unsigned long           di;
 213         unsigned short          es, __esh;
 214         unsigned short          cs, __csh;
 215         unsigned short          ss, __ssh;
 216         unsigned short          ds, __dsh;
 217         unsigned short          fs, __fsh;
 218         unsigned short          gs, __gsh;
 219         unsigned short          ldt, __ldth;
 220         unsigned short          trace;
 221         unsigned short          io_bitmap_base;
 222
 223 } __attribute__((packed));
 224 #else
 225 struct x86_hw_tss {
 226         u32                     reserved1;
 227         u64                     sp0;
 228         u64                     sp1;
 229         u64                     sp2;
 230         u64                     reserved2;
 231         u64                     ist[7];
 232         u32                     reserved3;
 233         u32                     reserved4;
 234         u16                     reserved5;
 235         u16                     io_bitmap_base;
 236
 237 } __attribute__((packed)) ____cacheline_aligned;
 238 #endif
 239
 240 /*
 241  * IO-bitmap sizes:
 242  */
 243 #define IO_BITMAP_BITS                  65536
 244 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 245 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 246 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 247 #define INVALID_IO_BITMAP_OFFSET        0x8000
 248
 249 struct tss_struct {
 250         /*
 251          * The hardware state:
 252          */
 253         struct x86_hw_tss       x86_tss;
 254
 255         /*
 256          * The extra 1 is there because the CPU will access an
 257          * additional byte beyond the end of the IO permission
 258          * bitmap. The extra byte must be all 1 bits, and must
 259          * be within the limit.
 260          */
 261         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 262
 263         /*
 264          * .. and then another 0x100 bytes for the emergency kernel stack:
 265          */
 266         unsigned long           stack[64];
 267
 268 } ____cacheline_aligned;
 269
 270 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 271
 272 /*
 273  * Save the original ist values for checking stack pointers during debugging
 274  */
 275 struct orig_ist {
 276         unsigned long           ist[7];
 277 };
 278
 279 #define MXCSR_DEFAULT           0x1f80
 280
 281 struct i387_fsave_struct {
 282         u32                     cwd;    /* FPU Control Word             */
 283         u32                     swd;    /* FPU Status Word              */
 284         u32                     twd;    /* FPU Tag Word                 */
 285         u32                     fip;    /* FPU IP Offset                */
 286         u32                     fcs;    /* FPU IP Selector              */
 287         u32                     foo;    /* FPU Operand Pointer Offset   */
 288         u32                     fos;    /* FPU Operand Pointer Selector */
 289
 290         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 291         u32                     st_space[20];
 292
 293         /* Software status information [not touched by FSAVE ]:         */
 294         u32                     status;
 295 };
 296
 297 struct i387_fxsave_struct {
 298         u16                     cwd; /* Control Word                    */
 299         u16                     swd; /* Status Word                     */
 300         u16                     twd; /* Tag Word                        */
 301         u16                     fop; /* Last Instruction Opcode         */
 302         union {
 303                 struct {
 304                         u64     rip; /* Instruction Pointer             */
 305                         u64     rdp; /* Data Pointer                    */
 306                 };
 307                 struct {
 308                         u32     fip; /* FPU IP Offset                   */
 309                         u32     fcs; /* FPU IP Selector                 */
 310                         u32     foo; /* FPU Operand Offset              */
 311                         u32     fos; /* FPU Operand Selector            */
 312                 };
 313         };
 314         u32                     mxcsr;          /* MXCSR Register State */
 315         u32                     mxcsr_mask;     /* MXCSR Mask           */
 316
 317         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 318         u32                     st_space[32];
 319
 320         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 321         u32                     xmm_space[64];
 322
 323         u32                     padding[12];
 324
 325         union {
 326                 u32             padding1[12];
 327                 u32             sw_reserved[12];
 328         };
 329
 330 } __attribute__((aligned(16)));
 331
 332 struct i387_soft_struct {
 333         u32                     cwd;
 334         u32                     swd;
 335         u32                     twd;
 336         u32                     fip;
 337         u32                     fcs;
 338         u32                     foo;
 339         u32                     fos;
 340         /* 8*10 bytes for each FP-reg = 80 bytes: */
 341         u32                     st_space[20];
 342         u8                      ftop;
 343         u8                      changed;
 344         u8                      lookahead;
 345         u8                      no_update;
 346         u8                      rm;
 347         u8                      alimit;
 348         struct math_emu_info    *info;
 349         u32                     entry_eip;
 350 };
 351
 352 struct ymmh_struct {
 353         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 354         u32 ymmh_space[64];
 355 };
 356
 357 struct xsave_hdr_struct {
 358         u64 xstate_bv;
 359         u64 reserved1[2];
 360         u64 reserved2[5];
 361 } __attribute__((packed));
 362
 363 struct xsave_struct {
 364         struct i387_fxsave_struct i387;
 365         struct xsave_hdr_struct xsave_hdr;
 366         struct ymmh_struct ymmh;
 367         /* new processor state extensions will go here */
 368 } __attribute__ ((packed, aligned (64)));
 369
 370 union thread_xstate {
 371         struct i387_fsave_struct        fsave;
 372         struct i387_fxsave_struct       fxsave;
 373         struct i387_soft_struct         soft;
 374         struct xsave_struct             xsave;
 375 };
 376
 377 struct fpu {
 378         unsigned int last_cpu;
 379         unsigned int has_fpu;
 380         union thread_xstate *state;
 381 };
 382
 383 #ifdef CONFIG_X86_64
 384 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 385
 386 union irq_stack_union {
 387         char irq_stack[IRQ_STACK_SIZE];
 388         /*
 389          * GCC hardcodes the stack canary as %gs:40.  Since the
 390          * irq_stack is the object at %gs:0, we reserve the bottom
 391          * 48 bytes of the irq stack for the canary.
 392          */
 393         struct {
 394                 char gs_base[40];
 395                 unsigned long stack_canary;
 396         };
 397 };
 398
 399 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 400 DECLARE_INIT_PER_CPU(irq_stack_union);
 401
 402 DECLARE_PER_CPU(char *, irq_stack_ptr);
 403 DECLARE_PER_CPU(unsigned int, irq_count);
 404 extern unsigned long kernel_eflags;
 405 extern asmlinkage void ignore_sysret(void);
 406 #else   /* X86_64 */
 407 #ifdef CONFIG_CC_STACKPROTECTOR
 408 /*
 409  * Make sure stack canary segment base is cached-aligned:
 410  *   "For Intel Atom processors, avoid non zero segment base address
 411  *    that is not aligned to cache line boundary at all cost."
 412  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 413  */
 414 struct stack_canary {
 415         char __pad[20];         /* canary at %gs:20 */
 416         unsigned long canary;
 417 };
 418 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 419 #endif
 420 #endif  /* X86_64 */
 421
 422 extern unsigned int xstate_size;
 423 extern void free_thread_xstate(struct task_struct *);
 424 extern struct kmem_cache *task_xstate_cachep;
 425
 426 struct perf_event;
 427
 428 struct thread_struct {
 429         /* Cached TLS descriptors: */
 430         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 431         unsigned long           sp0;
 432         unsigned long           sp;
 433 #ifdef CONFIG_X86_32
 434         unsigned long           sysenter_cs;
 435 #else
 436         unsigned long           usersp; /* Copy from PDA */
 437         unsigned short          es;
 438         unsigned short          ds;
 439         unsigned short          fsindex;
 440         unsigned short          gsindex;
 441 #endif
 442 #ifdef CONFIG_X86_32
 443         unsigned long           ip;
 444 #endif
 445 #ifdef CONFIG_X86_64
 446         unsigned long           fs;
 447 #endif
 448         unsigned long           gs;
 449         /* Save middle states of ptrace breakpoints */
 450         struct perf_event       *ptrace_bps[HBP_NUM];
 451         /* Debug status used for traps, single steps, etc... */
 452         unsigned long           debugreg6;
 453         /* Keep track of the exact dr7 value set by the user */
 454         unsigned long           ptrace_dr7;
 455         /* Fault info: */
 456         unsigned long           cr2;
 457         unsigned long           trap_no;
 458         unsigned long           error_code;
 459         /* floating point and extended processor state */
 460         struct fpu              fpu;
 461 #ifdef CONFIG_X86_32
 462         /* Virtual 86 mode info */
 463         struct vm86_struct __user *vm86_info;
 464         unsigned long           screen_bitmap;
 465         unsigned long           v86flags;
 466         unsigned long           v86mask;
 467         unsigned long           saved_sp0;
 468         unsigned int            saved_fs;
 469         unsigned int            saved_gs;
 470 #endif
 471         /* IO permissions: */
 472         unsigned long           *io_bitmap_ptr;
 473         unsigned long           iopl;
 474         /* Max allowed port in the bitmap, in bytes: */
 475         unsigned                io_bitmap_max;
 476 };
 477
 478 /*
 479  * Set IOPL bits in EFLAGS from given mask
 480  */
 481 static inline void native_set_iopl_mask(unsigned mask)
 482 {
 483 #ifdef CONFIG_X86_32
 484         unsigned int reg;
 485
 486         asm volatile ("pushfl;"
 487                       "popl %0;"
 488                       "andl %1, %0;"
 489                       "orl %2, %0;"
 490                       "pushl %0;"
 491                       "popfl"
 492                       : "=&r" (reg)
 493                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 494 #endif
 495 }
 496
 497 static inline void
 498 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 499 {
 500         tss->x86_tss.sp0 = thread->sp0;
 501 #ifdef CONFIG_X86_32
 502         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 503         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 504                 tss->x86_tss.ss1 = thread->sysenter_cs;
 505                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 506         }
 507 #endif
 508 }
 509
 510 static inline void native_swapgs(void)
 511 {
 512 #ifdef CONFIG_X86_64
 513         asm volatile("swapgs" ::: "memory");
 514 #endif
 515 }
 516
 517 #ifdef CONFIG_PARAVIRT
 518 #include <asm/paravirt.h>
 519 #else
 520 #define __cpuid                 native_cpuid
 521 #define paravirt_enabled()      0
 522
 523 static inline void load_sp0(struct tss_struct *tss,
 524                             struct thread_struct *thread)
 525 {
 526         native_load_sp0(tss, thread);
 527 }
 528
 529 #define set_iopl_mask native_set_iopl_mask
 530 #endif /* CONFIG_PARAVIRT */
 531
 532 /*
 533  * Save the cr4 feature set we're using (ie
 534  * Pentium 4MB enable and PPro Global page
 535  * enable), so that any CPU's that boot up
 536  * after us can get the correct flags.
 537  */
 538 extern unsigned long            mmu_cr4_features;
 539
 540 static inline void set_in_cr4(unsigned long mask)
 541 {
 542         unsigned long cr4;
 543
 544         mmu_cr4_features |= mask;
 545         cr4 = read_cr4();
 546         cr4 |= mask;
 547         write_cr4(cr4);
 548 }
 549
 550 static inline void clear_in_cr4(unsigned long mask)
 551 {
 552         unsigned long cr4;
 553
 554         mmu_cr4_features &= ~mask;
 555         cr4 = read_cr4();
 556         cr4 &= ~mask;
 557         write_cr4(cr4);
 558 }
 559
 560 typedef struct {
 561         unsigned long           seg;
 562 } mm_segment_t;
 563
 564
 565 /*
 566  * create a kernel thread without removing it from tasklists
 567  */
 568 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 569
 570 /* Free all resources held by a thread. */
 571 extern void release_thread(struct task_struct *);
 572
 573 /* Prepare to copy thread state - unlazy all lazy state */
 574 extern void prepare_to_copy(struct task_struct *tsk);
 575
 576 unsigned long get_wchan(struct task_struct *p);
 577
 578 /*
 579  * Generic CPUID function
 580  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 581  * resulting in stale register contents being returned.
 582  */
 583 static inline void cpuid(unsigned int op,
 584                          unsigned int *eax, unsigned int *ebx,
 585                          unsigned int *ecx, unsigned int *edx)
 586 {
 587         *eax = op;
 588         *ecx = 0;
 589         __cpuid(eax, ebx, ecx, edx);
 590 }
 591
 592 /* Some CPUID calls want 'count' to be placed in ecx */
 593 static inline void cpuid_count(unsigned int op, int count,
 594                                unsigned int *eax, unsigned int *ebx,
 595                                unsigned int *ecx, unsigned int *edx)
 596 {
 597         *eax = op;
 598         *ecx = count;
 599         __cpuid(eax, ebx, ecx, edx);
 600 }
 601
 602 /*
 603  * CPUID functions returning a single datum
 604  */
 605 static inline unsigned int cpuid_eax(unsigned int op)
 606 {
 607         unsigned int eax, ebx, ecx, edx;
 608
 609         cpuid(op, &eax, &ebx, &ecx, &edx);
 610
 611         return eax;
 612 }
 613
 614 static inline unsigned int cpuid_ebx(unsigned int op)
 615 {
 616         unsigned int eax, ebx, ecx, edx;
 617
 618         cpuid(op, &eax, &ebx, &ecx, &edx);
 619
 620         return ebx;
 621 }
 622
 623 static inline unsigned int cpuid_ecx(unsigned int op)
 624 {
 625         unsigned int eax, ebx, ecx, edx;
 626
 627         cpuid(op, &eax, &ebx, &ecx, &edx);
 628
 629         return ecx;
 630 }
 631
 632 static inline unsigned int cpuid_edx(unsigned int op)
 633 {
 634         unsigned int eax, ebx, ecx, edx;
 635
 636         cpuid(op, &eax, &ebx, &ecx, &edx);
 637
 638         return edx;
 639 }
 640
 641 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 642 static inline void rep_nop(void)
 643 {
 644         asm volatile("rep; nop" ::: "memory");
 645 }
 646
 647 static inline void cpu_relax(void)
 648 {
 649         rep_nop();
 650 }
 651
 652 /* Stop speculative execution and prefetching of modified code. */
 653 static inline void sync_core(void)
 654 {
 655         int tmp;
 656
 657 #if defined(CONFIG_M386) || defined(CONFIG_M486)
 658         if (boot_cpu_data.x86 < 5)
 659                 /* There is no speculative execution.
 660                  * jmp is a barrier to prefetching. */
 661                 asm volatile("jmp 1f\n1:\n" ::: "memory");
 662         else
 663 #endif
 664                 /* cpuid is a barrier to speculative execution.
 665                  * Prefetched instructions are automatically
 666                  * invalidated when modified. */
 667                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 668                              : "ebx", "ecx", "edx", "memory");
 669 }
 670
 671 static inline void __monitor(const void *eax, unsigned long ecx,
 672                              unsigned long edx)
 673 {
 674         /* "monitor %eax, %ecx, %edx;" */
 675         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 676                      :: "a" (eax), "c" (ecx), "d"(edx));
 677 }
 678
 679 static inline void __mwait(unsigned long eax, unsigned long ecx)
 680 {
 681         /* "mwait %eax, %ecx;" */
 682         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 683                      :: "a" (eax), "c" (ecx));
 684 }
 685
 686 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 687 {
 688         trace_hardirqs_on();
 689         /* "mwait %eax, %ecx;" */
 690         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 691                      :: "a" (eax), "c" (ecx));
 692 }
 693
 694 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 695 extern void init_amd_e400_c1e_mask(void);
 696
 697 extern unsigned long            boot_option_idle_override;
 698 extern bool                     amd_e400_c1e_detected;
 699
 700 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 701                          IDLE_POLL, IDLE_FORCE_MWAIT};
 702
 703 extern void enable_sep_cpu(void);
 704 extern int sysenter_setup(void);
 705
 706 extern void early_trap_init(void);
 707
 708 /* Defined in head.S */
 709 extern struct desc_ptr          early_gdt_descr;
 710
 711 extern void cpu_set_gdt(int);
 712 extern void switch_to_new_gdt(int);
 713 extern void load_percpu_segment(int);
 714 extern void cpu_init(void);
 715
 716 static inline unsigned long get_debugctlmsr(void)
 717 {
 718         unsigned long debugctlmsr = 0;
 719
 720 #ifndef CONFIG_X86_DEBUGCTLMSR
 721         if (boot_cpu_data.x86 < 6)
 722                 return 0;
 723 #endif
 724         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 725
 726         return debugctlmsr;
 727 }
 728
 729 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 730 {
 731 #ifndef CONFIG_X86_DEBUGCTLMSR
 732         if (boot_cpu_data.x86 < 6)
 733                 return;
 734 #endif
 735         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 736 }
 737
 738 /*
 739  * from system description table in BIOS. Mostly for MCA use, but
 740  * others may find it useful:
 741  */
 742 extern unsigned int             machine_id;
 743 extern unsigned int             machine_submodel_id;
 744 extern unsigned int             BIOS_revision;
 745
 746 /* Boot loader type from the setup header: */
 747 extern int                      bootloader_type;
 748 extern int                      bootloader_version;
 749
 750 extern char                     ignore_fpu_irq;
 751
 752 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 753 #define ARCH_HAS_PREFETCHW
 754 #define ARCH_HAS_SPINLOCK_PREFETCH
 755
 756 #ifdef CONFIG_X86_32
 757 # define BASE_PREFETCH          ASM_NOP4
 758 # define ARCH_HAS_PREFETCH
 759 #else
 760 # define BASE_PREFETCH          "prefetcht0 (%1)"
 761 #endif
 762
 763 /*
 764  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 765  *
 766  * It's not worth to care about 3dnow prefetches for the K6
 767  * because they are microcoded there and very slow.
 768  */
 769 static inline void prefetch(const void *x)
 770 {
 771         alternative_input(BASE_PREFETCH,
 772                           "prefetchnta (%1)",
 773                           X86_FEATURE_XMM,
 774                           "r" (x));
 775 }
 776
 777 /*
 778  * 3dnow prefetch to get an exclusive cache line.
 779  * Useful for spinlocks to avoid one state transition in the
 780  * cache coherency protocol:
 781  */
 782 static inline void prefetchw(const void *x)
 783 {
 784         alternative_input(BASE_PREFETCH,
 785                           "prefetchw (%1)",
 786                           X86_FEATURE_3DNOW,
 787                           "r" (x));
 788 }
 789
 790 static inline void spin_lock_prefetch(const void *x)
 791 {
 792         prefetchw(x);
 793 }
 794
 795 #ifdef CONFIG_X86_32
 796 /*
 797  * User space process size: 3GB (default).
 798  */
 799 #define TASK_SIZE               PAGE_OFFSET
 800 #define TASK_SIZE_MAX           TASK_SIZE
 801 #define STACK_TOP               TASK_SIZE
 802 #define STACK_TOP_MAX           STACK_TOP
 803
 804 #define INIT_THREAD  {                                                    \
 805         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 806         .vm86_info              = NULL,                                   \
 807         .sysenter_cs            = __KERNEL_CS,                            \
 808         .io_bitmap_ptr          = NULL,                                   \
 809 }
 810
 811 /*
 812  * Note that the .io_bitmap member must be extra-big. This is because
 813  * the CPU will access an additional byte beyond the end of the IO
 814  * permission bitmap. The extra byte must be all 1 bits, and must
 815  * be within the limit.
 816  */
 817 #define INIT_TSS  {                                                       \
 818         .x86_tss = {                                                      \
 819                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 820                 .ss0            = __KERNEL_DS,                            \
 821                 .ss1            = __KERNEL_CS,                            \
 822                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 823          },                                                               \
 824         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 825 }
 826
 827 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 828
 829 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 830 #define KSTK_TOP(info)                                                 \
 831 ({                                                                     \
 832        unsigned long *__ptr = (unsigned long *)(info);                 \
 833        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 834 })
 835
 836 /*
 837  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 838  * This is necessary to guarantee that the entire "struct pt_regs"
 839  * is accessible even if the CPU haven't stored the SS/ESP registers
 840  * on the stack (interrupt gate does not save these registers
 841  * when switching to the same priv ring).
 842  * Therefore beware: accessing the ss/esp fields of the
 843  * "struct pt_regs" is possible, but they may contain the
 844  * completely wrong values.
 845  */
 846 #define task_pt_regs(task)                                             \
 847 ({                                                                     \
 848        struct pt_regs *__regs__;                                       \
 849        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 850        __regs__ - 1;                                                   \
 851 })
 852
 853 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 854
 855 #else
 856 /*
 857  * User space process size. 47bits minus one guard page.
 858  */
 859 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 860
 861 /* This decides where the kernel will search for a free chunk of vm
 862  * space during mmap's.
 863  */
 864 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 865                                         0xc0000000 : 0xFFFFe000)
 866
 867 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 868                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 869 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 870                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 871
 872 #define STACK_TOP               TASK_SIZE
 873 #define STACK_TOP_MAX           TASK_SIZE_MAX
 874
 875 #define INIT_THREAD  { \
 876         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 877 }
 878
 879 #define INIT_TSS  { \
 880         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 881 }
 882
 883 /*
 884  * Return saved PC of a blocked thread.
 885  * What is this good for? it will be always the scheduler or ret_from_fork.
 886  */
 887 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 888
 889 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 890 extern unsigned long KSTK_ESP(struct task_struct *task);
 891 #endif /* CONFIG_X86_64 */
 892
 893 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 894                                                unsigned long new_sp);
 895
 896 /*
 897  * This decides where the kernel will search for a free chunk of vm
 898  * space during mmap's.
 899  */
 900 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 901
 902 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 903
 904 /* Get/set a process' ability to use the timestamp counter instruction */
 905 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 906 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 907
 908 extern int get_tsc_mode(unsigned long adr);
 909 extern int set_tsc_mode(unsigned int val);
 910
 911 extern int amd_get_nb_id(int cpu);
 912
 913 struct aperfmperf {
 914         u64 aperf, mperf;
 915 };
 916
 917 static inline void get_aperfmperf(struct aperfmperf *am)
 918 {
 919         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
 920
 921         rdmsrl(MSR_IA32_APERF, am->aperf);
 922         rdmsrl(MSR_IA32_MPERF, am->mperf);
 923 }
 924
 925 #define APERFMPERF_SHIFT 10
 926
 927 static inline
 928 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
 929                                     struct aperfmperf *new)
 930 {
 931         u64 aperf = new->aperf - old->aperf;
 932         u64 mperf = new->mperf - old->mperf;
 933         unsigned long ratio = aperf;
 934
 935         mperf >>= APERFMPERF_SHIFT;
 936         if (mperf)
 937                 ratio = div64_u64(aperf, mperf);
 938
 939         return ratio;
 940 }
 941
 942 /*
 943  * AMD errata checking
 944  */
 945 #ifdef CONFIG_CPU_SUP_AMD
 946 extern const int amd_erratum_383[];
 947 extern const int amd_erratum_400[];
 948 extern bool cpu_has_amd_erratum(const int *);
 949
 950 #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
 951 #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
 952 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
 953         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
 954 #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
 955 #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
 956 #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
 957
 958 #else
 959 #define cpu_has_amd_erratum(x)  (false)
 960 #endif /* CONFIG_CPU_SUP_AMD */
 961
 962 #endif /* _ASM_X86_PROCESSOR_H */