arch/x86/include/asm/summit/apic.h

   1 #ifndef __ASM_SUMMIT_APIC_H
   2 #define __ASM_SUMMIT_APIC_H
   3
   4 #include <asm/smp.h>
   5 #include <linux/gfp.h>
   6
   7 /* In clustered mode, the high nibble of APIC ID is a cluster number.
   8  * The low nibble is a 4-bit bitmap. */
   9 #define XAPIC_DEST_CPUS_SHIFT   4
  10 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
  11 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
  12
  13 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  14
  15 static inline const cpumask_t *summit_target_cpus(void)
  16 {
  17         /* CPU_MASK_ALL (0xff) has undefined behaviour with
  18          * dest_LowestPrio mode logical clustered apic interrupt routing
  19          * Just start on cpu 0.  IRQ balancing will spread load
  20          */
  21         return &cpumask_of_cpu(0);
  22 }
  23
  24 static inline unsigned long
  25 summit_check_apicid_used(physid_mask_t bitmap, int apicid)
  26 {
  27         return 0;
  28 }
  29
  30 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  31 static inline unsigned long summit_check_apicid_present(int bit)
  32 {
  33         return 1;
  34 }
  35
  36 #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
  37
  38 extern u8 cpu_2_logical_apicid[];
  39
  40 static inline void summit_init_apic_ldr(void)
  41 {
  42         unsigned long val, id;
  43         int count = 0;
  44         u8 my_id = (u8)hard_smp_processor_id();
  45         u8 my_cluster = (u8)apicid_cluster(my_id);
  46 #ifdef CONFIG_SMP
  47         u8 lid;
  48         int i;
  49
  50         /* Create logical APIC IDs by counting CPUs already in cluster. */
  51         for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
  52                 lid = cpu_2_logical_apicid[i];
  53                 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
  54                         ++count;
  55         }
  56 #endif
  57         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
  58          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
  59         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
  60         id = my_cluster | (1UL << count);
  61         apic_write(APIC_DFR, APIC_DFR_VALUE);
  62         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  63         val |= SET_APIC_LOGICAL_ID(id);
  64         apic_write(APIC_LDR, val);
  65 }
  66
  67 static inline int multi_timer_check(int apic, int irq)
  68 {
  69         return 0;
  70 }
  71
  72 static inline int summit_apic_id_registered(void)
  73 {
  74         return 1;
  75 }
  76
  77 static inline void setup_apic_routing(void)
  78 {
  79         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
  80                                                 nr_ioapics);
  81 }
  82
  83 static inline int apicid_to_node(int logical_apicid)
  84 {
  85 #ifdef CONFIG_SMP
  86         return apicid_2_node[hard_smp_processor_id()];
  87 #else
  88         return 0;
  89 #endif
  90 }
  91
  92 /* Mapping from cpu number to logical apicid */
  93 static inline int cpu_to_logical_apicid(int cpu)
  94 {
  95 #ifdef CONFIG_SMP
  96         if (cpu >= nr_cpu_ids)
  97                 return BAD_APICID;
  98         return (int)cpu_2_logical_apicid[cpu];
  99 #else
 100         return logical_smp_processor_id();
 101 #endif
 102 }
 103
 104 static inline int cpu_present_to_apicid(int mps_cpu)
 105 {
 106         if (mps_cpu < nr_cpu_ids)
 107                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 108         else
 109                 return BAD_APICID;
 110 }
 111
 112 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 113 {
 114         /* For clustered we don't have a good way to do this yet - hack */
 115         return physids_promote(0x0F);
 116 }
 117
 118 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 119 {
 120         return physid_mask_of_physid(0);
 121 }
 122
 123 static inline void setup_portio_remap(void)
 124 {
 125 }
 126
 127 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 128 {
 129         return 1;
 130 }
 131
 132 static inline void enable_apic_mode(void)
 133 {
 134 }
 135
 136 static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
 137 {
 138         int num_bits_set;
 139         int cpus_found = 0;
 140         int cpu;
 141         int apicid;
 142
 143         num_bits_set = cpus_weight(*cpumask);
 144         /* Return id to all */
 145         if (num_bits_set >= nr_cpu_ids)
 146                 return (int) 0xFF;
 147         /*
 148          * The cpus in the mask must all be on the apic cluster.  If are not
 149          * on the same apicid cluster return default value of target_cpus():
 150          */
 151         cpu = first_cpu(*cpumask);
 152         apicid = cpu_to_logical_apicid(cpu);
 153         while (cpus_found < num_bits_set) {
 154                 if (cpu_isset(cpu, *cpumask)) {
 155                         int new_apicid = cpu_to_logical_apicid(cpu);
 156                         if (apicid_cluster(apicid) !=
 157                                         apicid_cluster(new_apicid)){
 158                                 printk ("%s: Not a valid mask!\n", __func__);
 159                                 return 0xFF;
 160                         }
 161                         apicid = apicid | new_apicid;
 162                         cpus_found++;
 163                 }
 164                 cpu++;
 165         }
 166         return apicid;
 167 }
 168
 169 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *inmask,
 170                                                   const struct cpumask *andmask)
 171 {
 172         int apicid = cpu_to_logical_apicid(0);
 173         cpumask_var_t cpumask;
 174
 175         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
 176                 return apicid;
 177
 178         cpumask_and(cpumask, inmask, andmask);
 179         cpumask_and(cpumask, cpumask, cpu_online_mask);
 180         apicid = cpu_mask_to_apicid(cpumask);
 181
 182         free_cpumask_var(cpumask);
 183         return apicid;
 184 }
 185
 186 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 187  * register's value.  For any box whose BIOS changes APIC IDs, like
 188  * clustered APIC systems, we must use hard_smp_processor_id.
 189  *
 190  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 191  */
 192 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 193 {
 194         return hard_smp_processor_id() >> index_msb;
 195 }
 196
 197 #endif /* __ASM_SUMMIT_APIC_H */