arch/x86/include/asm/system.h

   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqflags.h>
  12
  13 /* entries in ARCH_DLINFO: */
  14 #ifdef CONFIG_IA32_EMULATION
  15 # define AT_VECTOR_SIZE_ARCH 2
  16 #else
  17 # define AT_VECTOR_SIZE_ARCH 1
  18 #endif
  19
  20 struct task_struct; /* one of the stranger aspects of C forward declarations */
  21 struct task_struct *__switch_to(struct task_struct *prev,
  22                                 struct task_struct *next);
  23
  24 #ifdef CONFIG_X86_32
  25
  26 /*
  27  * Saving eflags is important. It switches not only IOPL between tasks,
  28  * it also protects other tasks from NT leaking through sysenter etc.
  29  */
  30 #define switch_to(prev, next, last)                                     \
  31 do {                                                                    \
  32         /*                                                              \
  33          * Context-switching clobbers all registers, so we clobber      \
  34          * them explicitly, via unused output variables.                \
  35          * (EAX and EBP is not listed because EBP is saved/restored     \
  36          * explicitly for wchan access and EAX is the return value of   \
  37          * __switch_to())                                               \
  38          */                                                             \
  39         unsigned long ebx, ecx, edx, esi, edi;                          \
  40                                                                         \
  41         asm volatile("pushfl\n\t"               /* save    flags */     \
  42                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  43                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  44                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  45                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  46                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  47                      "jmp __switch_to\n"        /* regparm call  */     \
  48                      "1:\t"                                             \
  49                      "popl %%ebp\n\t"           /* restore EBP   */     \
  50                      "popfl\n"                  /* restore flags */     \
  51                                                                         \
  52                      /* output parameters */                            \
  53                      : [prev_sp] "=m" (prev->thread.sp),                \
  54                        [prev_ip] "=m" (prev->thread.ip),                \
  55                        "=a" (last),                                     \
  56                                                                         \
  57                        /* clobbered output registers: */                \
  58                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  59                        "=S" (esi), "=D" (edi)                           \
  60                                                                         \
  61                        /* input parameters: */                          \
  62                      : [next_sp]  "m" (next->thread.sp),                \
  63                        [next_ip]  "m" (next->thread.ip),                \
  64                                                                         \
  65                        /* regparm parameters for __switch_to(): */      \
  66                        [prev]     "a" (prev),                           \
  67                        [next]     "d" (next)                            \
  68                                                                         \
  69                      : /* reloaded segment registers */                 \
  70                         "memory");                                      \
  71 } while (0)
  72
  73 /*
  74  * disable hlt during certain critical i/o operations
  75  */
  76 #define HAVE_DISABLE_HLT
  77 #else
  78 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  79 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  80
  81 /* frame pointer must be last for get_wchan */
  82 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  83 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  84
  85 #define __EXTRA_CLOBBER  \
  86         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
  87           "r12", "r13", "r14", "r15"
  88
  89 #ifdef CONFIG_CC_STACKPROTECTOR
  90 #define __switch_canary                                                   \
  91         "movq %P[task_canary](%%rsi),%%r8\n\t"                            \
  92         "movq %%r8,"__percpu_arg([gs_canary])"\n\t"
  93 #define __switch_canary_oparam                                            \
  94         , [gs_canary] "=m" (per_cpu_var(irq_stack_union.stack_canary))
  95 #define __switch_canary_iparam                                            \
  96         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
  97 #else   /* CC_STACKPROTECTOR */
  98 #define __switch_canary
  99 #define __switch_canary_oparam
 100 #define __switch_canary_iparam
 101 #endif  /* CC_STACKPROTECTOR */
 102
 103 /* Save restore flags to clear handle leaking NT */
 104 #define switch_to(prev, next, last) \
 105         asm volatile(SAVE_CONTEXT                                         \
 106              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
 107              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
 108              "call __switch_to\n\t"                                       \
 109              ".globl thread_return\n"                                     \
 110              "thread_return:\n\t"                                         \
 111              "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
 112              __switch_canary                                              \
 113              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
 114              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
 115              "movq %%rax,%%rdi\n\t"                                       \
 116              "jc   ret_from_fork\n\t"                                     \
 117              RESTORE_CONTEXT                                              \
 118              : "=a" (last)                                                \
 119                __switch_canary_oparam                                     \
 120              : [next] "S" (next), [prev] "D" (prev),                      \
 121                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 122                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 123                [tif_fork] "i" (TIF_FORK),                                 \
 124                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 125                [current_task] "m" (per_cpu_var(current_task))             \
 126                __switch_canary_iparam                                     \
 127              : "memory", "cc" __EXTRA_CLOBBER)
 128 #endif
 129
 130 #ifdef __KERNEL__
 131 #define _set_base(addr, base) do { unsigned long __pr; \
 132 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 133         "rorl $16,%%edx\n\t" \
 134         "movb %%dl,%2\n\t" \
 135         "movb %%dh,%3" \
 136         :"=&d" (__pr) \
 137         :"m" (*((addr)+2)), \
 138          "m" (*((addr)+4)), \
 139          "m" (*((addr)+7)), \
 140          "0" (base) \
 141         ); } while (0)
 142
 143 #define _set_limit(addr, limit) do { unsigned long __lr; \
 144 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 145         "rorl $16,%%edx\n\t" \
 146         "movb %2,%%dh\n\t" \
 147         "andb $0xf0,%%dh\n\t" \
 148         "orb %%dh,%%dl\n\t" \
 149         "movb %%dl,%2" \
 150         :"=&d" (__lr) \
 151         :"m" (*(addr)), \
 152          "m" (*((addr)+6)), \
 153          "0" (limit) \
 154         ); } while (0)
 155
 156 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 157 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 158
 159 extern void native_load_gs_index(unsigned);
 160
 161 /*
 162  * Load a segment. Fall back on loading the zero
 163  * segment if something goes wrong..
 164  */
 165 #define loadsegment(seg, value)                 \
 166         asm volatile("\n"                       \
 167                      "1:\t"                     \
 168                      "movl %k0,%%" #seg "\n"    \
 169                      "2:\n"                     \
 170                      ".section .fixup,\"ax\"\n" \
 171                      "3:\t"                     \
 172                      "movl %k1, %%" #seg "\n\t" \
 173                      "jmp 2b\n"                 \
 174                      ".previous\n"              \
 175                      _ASM_EXTABLE(1b,3b)        \
 176                      : :"r" (value), "r" (0) : "memory")
 177
 178
 179 /*
 180  * Save a segment register away
 181  */
 182 #define savesegment(seg, value)                         \
 183         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 184
 185 /*
 186  * x86_32 user gs accessors.
 187  */
 188 #ifdef CONFIG_X86_32
 189 #ifdef CONFIG_X86_32_LAZY_GS
 190 #define get_user_gs(regs)       (u16)({unsigned long v; savesegment(gs, v); v;})
 191 #define set_user_gs(regs, v)    loadsegment(gs, (unsigned long)(v))
 192 #define task_user_gs(tsk)       ((tsk)->thread.gs)
 193 #define lazy_save_gs(v)         savesegment(gs, (v))
 194 #define lazy_load_gs(v)         loadsegment(gs, (v))
 195 #else   /* X86_32_LAZY_GS */
 196 #define get_user_gs(regs)       (u16)((regs)->gs)
 197 #define set_user_gs(regs, v)    do { (regs)->gs = (v); } while (0)
 198 #define task_user_gs(tsk)       (task_pt_regs(tsk)->gs)
 199 #define lazy_save_gs(v)         do { } while (0)
 200 #define lazy_load_gs(v)         do { } while (0)
 201 #endif  /* X86_32_LAZY_GS */
 202 #endif  /* X86_32 */
 203
 204 static inline unsigned long get_limit(unsigned long segment)
 205 {
 206         unsigned long __limit;
 207         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 208         return __limit + 1;
 209 }
 210
 211 static inline void native_clts(void)
 212 {
 213         asm volatile("clts");
 214 }
 215
 216 /*
 217  * Volatile isn't enough to prevent the compiler from reordering the
 218  * read/write functions for the control registers and messing everything up.
 219  * A memory clobber would solve the problem, but would prevent reordering of
 220  * all loads stores around it, which can hurt performance. Solution is to
 221  * use a variable and mimic reads and writes to it to enforce serialization
 222  */
 223 static unsigned long __force_order;
 224
 225 static inline unsigned long native_read_cr0(void)
 226 {
 227         unsigned long val;
 228         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 229         return val;
 230 }
 231
 232 static inline void native_write_cr0(unsigned long val)
 233 {
 234         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 235 }
 236
 237 static inline unsigned long native_read_cr2(void)
 238 {
 239         unsigned long val;
 240         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
 241         return val;
 242 }
 243
 244 static inline void native_write_cr2(unsigned long val)
 245 {
 246         asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
 247 }
 248
 249 static inline unsigned long native_read_cr3(void)
 250 {
 251         unsigned long val;
 252         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 253         return val;
 254 }
 255
 256 static inline void native_write_cr3(unsigned long val)
 257 {
 258         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 259 }
 260
 261 static inline unsigned long native_read_cr4(void)
 262 {
 263         unsigned long val;
 264         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 265         return val;
 266 }
 267
 268 static inline unsigned long native_read_cr4_safe(void)
 269 {
 270         unsigned long val;
 271         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 272          * exists, so it will never fail. */
 273 #ifdef CONFIG_X86_32
 274         asm volatile("1: mov %%cr4, %0\n"
 275                      "2:\n"
 276                      _ASM_EXTABLE(1b, 2b)
 277                      : "=r" (val), "=m" (__force_order) : "0" (0));
 278 #else
 279         val = native_read_cr4();
 280 #endif
 281         return val;
 282 }
 283
 284 static inline void native_write_cr4(unsigned long val)
 285 {
 286         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 287 }
 288
 289 #ifdef CONFIG_X86_64
 290 static inline unsigned long native_read_cr8(void)
 291 {
 292         unsigned long cr8;
 293         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 294         return cr8;
 295 }
 296
 297 static inline void native_write_cr8(unsigned long val)
 298 {
 299         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 300 }
 301 #endif
 302
 303 static inline void native_wbinvd(void)
 304 {
 305         asm volatile("wbinvd": : :"memory");
 306 }
 307
 308 #ifdef CONFIG_PARAVIRT
 309 #include <asm/paravirt.h>
 310 #else
 311 #define read_cr0()      (native_read_cr0())
 312 #define write_cr0(x)    (native_write_cr0(x))
 313 #define read_cr2()      (native_read_cr2())
 314 #define write_cr2(x)    (native_write_cr2(x))
 315 #define read_cr3()      (native_read_cr3())
 316 #define write_cr3(x)    (native_write_cr3(x))
 317 #define read_cr4()      (native_read_cr4())
 318 #define read_cr4_safe() (native_read_cr4_safe())
 319 #define write_cr4(x)    (native_write_cr4(x))
 320 #define wbinvd()        (native_wbinvd())
 321 #ifdef CONFIG_X86_64
 322 #define read_cr8()      (native_read_cr8())
 323 #define write_cr8(x)    (native_write_cr8(x))
 324 #define load_gs_index   native_load_gs_index
 325 #endif
 326
 327 /* Clear the 'TS' bit */
 328 #define clts()          (native_clts())
 329
 330 #endif/* CONFIG_PARAVIRT */
 331
 332 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
 333
 334 #endif /* __KERNEL__ */
 335
 336 static inline void clflush(volatile void *__p)
 337 {
 338         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 339 }
 340
 341 #define nop() asm volatile ("nop")
 342
 343 void disable_hlt(void);
 344 void enable_hlt(void);
 345
 346 void cpu_idle_wait(void);
 347
 348 extern unsigned long arch_align_stack(unsigned long sp);
 349 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 350
 351 void default_idle(void);
 352
 353 void stop_this_cpu(void *dummy);
 354
 355 /*
 356  * Force strict CPU ordering.
 357  * And yes, this is required on UP too when we're talking
 358  * to devices.
 359  */
 360 #ifdef CONFIG_X86_32
 361 /*
 362  * Some non-Intel clones support out of order store. wmb() ceases to be a
 363  * nop for these.
 364  */
 365 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 366 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 367 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 368 #else
 369 #define mb()    asm volatile("mfence":::"memory")
 370 #define rmb()   asm volatile("lfence":::"memory")
 371 #define wmb()   asm volatile("sfence" ::: "memory")
 372 #endif
 373
 374 /**
 375  * read_barrier_depends - Flush all pending reads that subsequents reads
 376  * depend on.
 377  *
 378  * No data-dependent reads from memory-like regions are ever reordered
 379  * over this barrier.  All reads preceding this primitive are guaranteed
 380  * to access memory (but not necessarily other CPUs' caches) before any
 381  * reads following this primitive that depend on the data return by
 382  * any of the preceding reads.  This primitive is much lighter weight than
 383  * rmb() on most CPUs, and is never heavier weight than is
 384  * rmb().
 385  *
 386  * These ordering constraints are respected by both the local CPU
 387  * and the compiler.
 388  *
 389  * Ordering is not guaranteed by anything other than these primitives,
 390  * not even by data dependencies.  See the documentation for
 391  * memory_barrier() for examples and URLs to more information.
 392  *
 393  * For example, the following code would force ordering (the initial
 394  * value of "a" is zero, "b" is one, and "p" is "&a"):
 395  *
 396  * <programlisting>
 397  *      CPU 0                           CPU 1
 398  *
 399  *      b = 2;
 400  *      memory_barrier();
 401  *      p = &b;                         q = p;
 402  *                                      read_barrier_depends();
 403  *                                      d = *q;
 404  * </programlisting>
 405  *
 406  * because the read of "*q" depends on the read of "p" and these
 407  * two reads are separated by a read_barrier_depends().  However,
 408  * the following code, with the same initial values for "a" and "b":
 409  *
 410  * <programlisting>
 411  *      CPU 0                           CPU 1
 412  *
 413  *      a = 2;
 414  *      memory_barrier();
 415  *      b = 3;                          y = b;
 416  *                                      read_barrier_depends();
 417  *                                      x = a;
 418  * </programlisting>
 419  *
 420  * does not enforce ordering, since there is no data dependency between
 421  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 422  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 423  * in cases like this where there are no data dependencies.
 424  **/
 425
 426 #define read_barrier_depends()  do { } while (0)
 427
 428 #ifdef CONFIG_SMP
 429 #define smp_mb()        mb()
 430 #ifdef CONFIG_X86_PPRO_FENCE
 431 # define smp_rmb()      rmb()
 432 #else
 433 # define smp_rmb()      barrier()
 434 #endif
 435 #ifdef CONFIG_X86_OOSTORE
 436 # define smp_wmb()      wmb()
 437 #else
 438 # define smp_wmb()      barrier()
 439 #endif
 440 #define smp_read_barrier_depends()      read_barrier_depends()
 441 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 442 #else
 443 #define smp_mb()        barrier()
 444 #define smp_rmb()       barrier()
 445 #define smp_wmb()       barrier()
 446 #define smp_read_barrier_depends()      do { } while (0)
 447 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 448 #endif
 449
 450 /*
 451  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 452  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 453  * code region.
 454  *
 455  * (Could use an alternative three way for this if there was one.)
 456  */
 457 static inline void rdtsc_barrier(void)
 458 {
 459         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 460         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 461 }
 462
 463 #endif /* _ASM_X86_SYSTEM_H */