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x86_64: make /proc/interrupts work with dyn irq_desc
[deliverable/linux.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
29
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
31
32 #define EXIT_LOOP_COUNT 10000000
33
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
35
36 /* A list of preallocated protection domains */
37 static LIST_HEAD(iommu_pd_list);
38 static DEFINE_SPINLOCK(iommu_pd_list_lock);
39
40 /*
41 * general struct to manage commands send to an IOMMU
42 */
43 struct iommu_cmd {
44 u32 data[4];
45 };
46
47 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
48 struct unity_map_entry *e);
49
50 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
51 static int iommu_has_npcache(struct amd_iommu *iommu)
52 {
53 return iommu->cap & IOMMU_CAP_NPCACHE;
54 }
55
56 /****************************************************************************
57 *
58 * Interrupt handling functions
59 *
60 ****************************************************************************/
61
62 static void iommu_print_event(void *__evt)
63 {
64 u32 *event = __evt;
65 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
66 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
67 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
68 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
69 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
70
71 printk(KERN_ERR "AMD IOMMU: Event logged [");
72
73 switch (type) {
74 case EVENT_TYPE_ILL_DEV:
75 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
76 "address=0x%016llx flags=0x%04x]\n",
77 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
78 address, flags);
79 break;
80 case EVENT_TYPE_IO_FAULT:
81 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
82 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
83 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
84 domid, address, flags);
85 break;
86 case EVENT_TYPE_DEV_TAB_ERR:
87 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
88 "address=0x%016llx flags=0x%04x]\n",
89 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90 address, flags);
91 break;
92 case EVENT_TYPE_PAGE_TAB_ERR:
93 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
94 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
95 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
96 domid, address, flags);
97 break;
98 case EVENT_TYPE_ILL_CMD:
99 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
100 break;
101 case EVENT_TYPE_CMD_HARD_ERR:
102 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
103 "flags=0x%04x]\n", address, flags);
104 break;
105 case EVENT_TYPE_IOTLB_INV_TO:
106 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
107 "address=0x%016llx]\n",
108 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
109 address);
110 break;
111 case EVENT_TYPE_INV_DEV_REQ:
112 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
113 "address=0x%016llx flags=0x%04x]\n",
114 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
115 address, flags);
116 break;
117 default:
118 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
119 }
120 }
121
122 static void iommu_poll_events(struct amd_iommu *iommu)
123 {
124 u32 head, tail;
125 unsigned long flags;
126
127 spin_lock_irqsave(&iommu->lock, flags);
128
129 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
130 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
131
132 while (head != tail) {
133 iommu_print_event(iommu->evt_buf + head);
134 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
135 }
136
137 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
138
139 spin_unlock_irqrestore(&iommu->lock, flags);
140 }
141
142 irqreturn_t amd_iommu_int_handler(int irq, void *data)
143 {
144 struct amd_iommu *iommu;
145
146 list_for_each_entry(iommu, &amd_iommu_list, list)
147 iommu_poll_events(iommu);
148
149 return IRQ_HANDLED;
150 }
151
152 /****************************************************************************
153 *
154 * IOMMU command queuing functions
155 *
156 ****************************************************************************/
157
158 /*
159 * Writes the command to the IOMMUs command buffer and informs the
160 * hardware about the new command. Must be called with iommu->lock held.
161 */
162 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
163 {
164 u32 tail, head;
165 u8 *target;
166
167 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
168 target = iommu->cmd_buf + tail;
169 memcpy_toio(target, cmd, sizeof(*cmd));
170 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
171 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
172 if (tail == head)
173 return -ENOMEM;
174 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
175
176 return 0;
177 }
178
179 /*
180 * General queuing function for commands. Takes iommu->lock and calls
181 * __iommu_queue_command().
182 */
183 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
184 {
185 unsigned long flags;
186 int ret;
187
188 spin_lock_irqsave(&iommu->lock, flags);
189 ret = __iommu_queue_command(iommu, cmd);
190 spin_unlock_irqrestore(&iommu->lock, flags);
191
192 return ret;
193 }
194
195 /*
196 * This function is called whenever we need to ensure that the IOMMU has
197 * completed execution of all commands we sent. It sends a
198 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
199 * us about that by writing a value to a physical address we pass with
200 * the command.
201 */
202 static int iommu_completion_wait(struct amd_iommu *iommu)
203 {
204 int ret = 0, ready = 0;
205 unsigned status = 0;
206 struct iommu_cmd cmd;
207 unsigned long flags, i = 0;
208
209 memset(&cmd, 0, sizeof(cmd));
210 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
211 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
212
213 iommu->need_sync = 0;
214
215 spin_lock_irqsave(&iommu->lock, flags);
216
217 ret = __iommu_queue_command(iommu, &cmd);
218
219 if (ret)
220 goto out;
221
222 while (!ready && (i < EXIT_LOOP_COUNT)) {
223 ++i;
224 /* wait for the bit to become one */
225 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
226 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
227 }
228
229 /* set bit back to zero */
230 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
231 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
232
233 if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
234 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
235 out:
236 spin_unlock_irqrestore(&iommu->lock, flags);
237
238 return 0;
239 }
240
241 /*
242 * Command send function for invalidating a device table entry
243 */
244 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
245 {
246 struct iommu_cmd cmd;
247 int ret;
248
249 BUG_ON(iommu == NULL);
250
251 memset(&cmd, 0, sizeof(cmd));
252 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
253 cmd.data[0] = devid;
254
255 ret = iommu_queue_command(iommu, &cmd);
256
257 iommu->need_sync = 1;
258
259 return ret;
260 }
261
262 /*
263 * Generic command send function for invalidaing TLB entries
264 */
265 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
266 u64 address, u16 domid, int pde, int s)
267 {
268 struct iommu_cmd cmd;
269 int ret;
270
271 memset(&cmd, 0, sizeof(cmd));
272 address &= PAGE_MASK;
273 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
274 cmd.data[1] |= domid;
275 cmd.data[2] = lower_32_bits(address);
276 cmd.data[3] = upper_32_bits(address);
277 if (s) /* size bit - we flush more than one 4kb page */
278 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
279 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
280 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
281
282 ret = iommu_queue_command(iommu, &cmd);
283
284 iommu->need_sync = 1;
285
286 return ret;
287 }
288
289 /*
290 * TLB invalidation function which is called from the mapping functions.
291 * It invalidates a single PTE if the range to flush is within a single
292 * page. Otherwise it flushes the whole TLB of the IOMMU.
293 */
294 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
295 u64 address, size_t size)
296 {
297 int s = 0;
298 unsigned pages = iommu_num_pages(address, size);
299
300 address &= PAGE_MASK;
301
302 if (pages > 1) {
303 /*
304 * If we have to flush more than one page, flush all
305 * TLB entries for this domain
306 */
307 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
308 s = 1;
309 }
310
311 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
312
313 return 0;
314 }
315
316 /* Flush the whole IO/TLB for a given protection domain */
317 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
318 {
319 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
320
321 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
322 }
323
324 /****************************************************************************
325 *
326 * The functions below are used the create the page table mappings for
327 * unity mapped regions.
328 *
329 ****************************************************************************/
330
331 /*
332 * Generic mapping functions. It maps a physical address into a DMA
333 * address space. It allocates the page table pages if necessary.
334 * In the future it can be extended to a generic mapping function
335 * supporting all features of AMD IOMMU page tables like level skipping
336 * and full 64 bit address spaces.
337 */
338 static int iommu_map(struct protection_domain *dom,
339 unsigned long bus_addr,
340 unsigned long phys_addr,
341 int prot)
342 {
343 u64 __pte, *pte, *page;
344
345 bus_addr = PAGE_ALIGN(bus_addr);
346 phys_addr = PAGE_ALIGN(bus_addr);
347
348 /* only support 512GB address spaces for now */
349 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
350 return -EINVAL;
351
352 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
353
354 if (!IOMMU_PTE_PRESENT(*pte)) {
355 page = (u64 *)get_zeroed_page(GFP_KERNEL);
356 if (!page)
357 return -ENOMEM;
358 *pte = IOMMU_L2_PDE(virt_to_phys(page));
359 }
360
361 pte = IOMMU_PTE_PAGE(*pte);
362 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
363
364 if (!IOMMU_PTE_PRESENT(*pte)) {
365 page = (u64 *)get_zeroed_page(GFP_KERNEL);
366 if (!page)
367 return -ENOMEM;
368 *pte = IOMMU_L1_PDE(virt_to_phys(page));
369 }
370
371 pte = IOMMU_PTE_PAGE(*pte);
372 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
373
374 if (IOMMU_PTE_PRESENT(*pte))
375 return -EBUSY;
376
377 __pte = phys_addr | IOMMU_PTE_P;
378 if (prot & IOMMU_PROT_IR)
379 __pte |= IOMMU_PTE_IR;
380 if (prot & IOMMU_PROT_IW)
381 __pte |= IOMMU_PTE_IW;
382
383 *pte = __pte;
384
385 return 0;
386 }
387
388 /*
389 * This function checks if a specific unity mapping entry is needed for
390 * this specific IOMMU.
391 */
392 static int iommu_for_unity_map(struct amd_iommu *iommu,
393 struct unity_map_entry *entry)
394 {
395 u16 bdf, i;
396
397 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
398 bdf = amd_iommu_alias_table[i];
399 if (amd_iommu_rlookup_table[bdf] == iommu)
400 return 1;
401 }
402
403 return 0;
404 }
405
406 /*
407 * Init the unity mappings for a specific IOMMU in the system
408 *
409 * Basically iterates over all unity mapping entries and applies them to
410 * the default domain DMA of that IOMMU if necessary.
411 */
412 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
413 {
414 struct unity_map_entry *entry;
415 int ret;
416
417 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
418 if (!iommu_for_unity_map(iommu, entry))
419 continue;
420 ret = dma_ops_unity_map(iommu->default_dom, entry);
421 if (ret)
422 return ret;
423 }
424
425 return 0;
426 }
427
428 /*
429 * This function actually applies the mapping to the page table of the
430 * dma_ops domain.
431 */
432 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
433 struct unity_map_entry *e)
434 {
435 u64 addr;
436 int ret;
437
438 for (addr = e->address_start; addr < e->address_end;
439 addr += PAGE_SIZE) {
440 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
441 if (ret)
442 return ret;
443 /*
444 * if unity mapping is in aperture range mark the page
445 * as allocated in the aperture
446 */
447 if (addr < dma_dom->aperture_size)
448 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
449 }
450
451 return 0;
452 }
453
454 /*
455 * Inits the unity mappings required for a specific device
456 */
457 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
458 u16 devid)
459 {
460 struct unity_map_entry *e;
461 int ret;
462
463 list_for_each_entry(e, &amd_iommu_unity_map, list) {
464 if (!(devid >= e->devid_start && devid <= e->devid_end))
465 continue;
466 ret = dma_ops_unity_map(dma_dom, e);
467 if (ret)
468 return ret;
469 }
470
471 return 0;
472 }
473
474 /****************************************************************************
475 *
476 * The next functions belong to the address allocator for the dma_ops
477 * interface functions. They work like the allocators in the other IOMMU
478 * drivers. Its basically a bitmap which marks the allocated pages in
479 * the aperture. Maybe it could be enhanced in the future to a more
480 * efficient allocator.
481 *
482 ****************************************************************************/
483
484 /*
485 * The address allocator core function.
486 *
487 * called with domain->lock held
488 */
489 static unsigned long dma_ops_alloc_addresses(struct device *dev,
490 struct dma_ops_domain *dom,
491 unsigned int pages,
492 unsigned long align_mask,
493 u64 dma_mask)
494 {
495 unsigned long limit;
496 unsigned long address;
497 unsigned long boundary_size;
498
499 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
500 PAGE_SIZE) >> PAGE_SHIFT;
501 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
502 dma_mask >> PAGE_SHIFT);
503
504 if (dom->next_bit >= limit) {
505 dom->next_bit = 0;
506 dom->need_flush = true;
507 }
508
509 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
510 0 , boundary_size, align_mask);
511 if (address == -1) {
512 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
513 0, boundary_size, align_mask);
514 dom->need_flush = true;
515 }
516
517 if (likely(address != -1)) {
518 dom->next_bit = address + pages;
519 address <<= PAGE_SHIFT;
520 } else
521 address = bad_dma_address;
522
523 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
524
525 return address;
526 }
527
528 /*
529 * The address free function.
530 *
531 * called with domain->lock held
532 */
533 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
534 unsigned long address,
535 unsigned int pages)
536 {
537 address >>= PAGE_SHIFT;
538 iommu_area_free(dom->bitmap, address, pages);
539 }
540
541 /****************************************************************************
542 *
543 * The next functions belong to the domain allocation. A domain is
544 * allocated for every IOMMU as the default domain. If device isolation
545 * is enabled, every device get its own domain. The most important thing
546 * about domains is the page table mapping the DMA address space they
547 * contain.
548 *
549 ****************************************************************************/
550
551 static u16 domain_id_alloc(void)
552 {
553 unsigned long flags;
554 int id;
555
556 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
557 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
558 BUG_ON(id == 0);
559 if (id > 0 && id < MAX_DOMAIN_ID)
560 __set_bit(id, amd_iommu_pd_alloc_bitmap);
561 else
562 id = 0;
563 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
564
565 return id;
566 }
567
568 /*
569 * Used to reserve address ranges in the aperture (e.g. for exclusion
570 * ranges.
571 */
572 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
573 unsigned long start_page,
574 unsigned int pages)
575 {
576 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
577
578 if (start_page + pages > last_page)
579 pages = last_page - start_page;
580
581 iommu_area_reserve(dom->bitmap, start_page, pages);
582 }
583
584 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
585 {
586 int i, j;
587 u64 *p1, *p2, *p3;
588
589 p1 = dma_dom->domain.pt_root;
590
591 if (!p1)
592 return;
593
594 for (i = 0; i < 512; ++i) {
595 if (!IOMMU_PTE_PRESENT(p1[i]))
596 continue;
597
598 p2 = IOMMU_PTE_PAGE(p1[i]);
599 for (j = 0; j < 512; ++i) {
600 if (!IOMMU_PTE_PRESENT(p2[j]))
601 continue;
602 p3 = IOMMU_PTE_PAGE(p2[j]);
603 free_page((unsigned long)p3);
604 }
605
606 free_page((unsigned long)p2);
607 }
608
609 free_page((unsigned long)p1);
610 }
611
612 /*
613 * Free a domain, only used if something went wrong in the
614 * allocation path and we need to free an already allocated page table
615 */
616 static void dma_ops_domain_free(struct dma_ops_domain *dom)
617 {
618 if (!dom)
619 return;
620
621 dma_ops_free_pagetable(dom);
622
623 kfree(dom->pte_pages);
624
625 kfree(dom->bitmap);
626
627 kfree(dom);
628 }
629
630 /*
631 * Allocates a new protection domain usable for the dma_ops functions.
632 * It also intializes the page table and the address allocator data
633 * structures required for the dma_ops interface
634 */
635 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
636 unsigned order)
637 {
638 struct dma_ops_domain *dma_dom;
639 unsigned i, num_pte_pages;
640 u64 *l2_pde;
641 u64 address;
642
643 /*
644 * Currently the DMA aperture must be between 32 MB and 1GB in size
645 */
646 if ((order < 25) || (order > 30))
647 return NULL;
648
649 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
650 if (!dma_dom)
651 return NULL;
652
653 spin_lock_init(&dma_dom->domain.lock);
654
655 dma_dom->domain.id = domain_id_alloc();
656 if (dma_dom->domain.id == 0)
657 goto free_dma_dom;
658 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
659 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
660 dma_dom->domain.priv = dma_dom;
661 if (!dma_dom->domain.pt_root)
662 goto free_dma_dom;
663 dma_dom->aperture_size = (1ULL << order);
664 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
665 GFP_KERNEL);
666 if (!dma_dom->bitmap)
667 goto free_dma_dom;
668 /*
669 * mark the first page as allocated so we never return 0 as
670 * a valid dma-address. So we can use 0 as error value
671 */
672 dma_dom->bitmap[0] = 1;
673 dma_dom->next_bit = 0;
674
675 dma_dom->need_flush = false;
676 dma_dom->target_dev = 0xffff;
677
678 /* Intialize the exclusion range if necessary */
679 if (iommu->exclusion_start &&
680 iommu->exclusion_start < dma_dom->aperture_size) {
681 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
682 int pages = iommu_num_pages(iommu->exclusion_start,
683 iommu->exclusion_length);
684 dma_ops_reserve_addresses(dma_dom, startpage, pages);
685 }
686
687 /*
688 * At the last step, build the page tables so we don't need to
689 * allocate page table pages in the dma_ops mapping/unmapping
690 * path.
691 */
692 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
693 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
694 GFP_KERNEL);
695 if (!dma_dom->pte_pages)
696 goto free_dma_dom;
697
698 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
699 if (l2_pde == NULL)
700 goto free_dma_dom;
701
702 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
703
704 for (i = 0; i < num_pte_pages; ++i) {
705 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
706 if (!dma_dom->pte_pages[i])
707 goto free_dma_dom;
708 address = virt_to_phys(dma_dom->pte_pages[i]);
709 l2_pde[i] = IOMMU_L1_PDE(address);
710 }
711
712 return dma_dom;
713
714 free_dma_dom:
715 dma_ops_domain_free(dma_dom);
716
717 return NULL;
718 }
719
720 /*
721 * Find out the protection domain structure for a given PCI device. This
722 * will give us the pointer to the page table root for example.
723 */
724 static struct protection_domain *domain_for_device(u16 devid)
725 {
726 struct protection_domain *dom;
727 unsigned long flags;
728
729 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
730 dom = amd_iommu_pd_table[devid];
731 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
732
733 return dom;
734 }
735
736 /*
737 * If a device is not yet associated with a domain, this function does
738 * assigns it visible for the hardware
739 */
740 static void set_device_domain(struct amd_iommu *iommu,
741 struct protection_domain *domain,
742 u16 devid)
743 {
744 unsigned long flags;
745
746 u64 pte_root = virt_to_phys(domain->pt_root);
747
748 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
749 << DEV_ENTRY_MODE_SHIFT;
750 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
751
752 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
753 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
754 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
755 amd_iommu_dev_table[devid].data[2] = domain->id;
756
757 amd_iommu_pd_table[devid] = domain;
758 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
759
760 iommu_queue_inv_dev_entry(iommu, devid);
761
762 iommu->need_sync = 1;
763 }
764
765 /*****************************************************************************
766 *
767 * The next functions belong to the dma_ops mapping/unmapping code.
768 *
769 *****************************************************************************/
770
771 /*
772 * This function checks if the driver got a valid device from the caller to
773 * avoid dereferencing invalid pointers.
774 */
775 static bool check_device(struct device *dev)
776 {
777 if (!dev || !dev->dma_mask)
778 return false;
779
780 return true;
781 }
782
783 /*
784 * In this function the list of preallocated protection domains is traversed to
785 * find the domain for a specific device
786 */
787 static struct dma_ops_domain *find_protection_domain(u16 devid)
788 {
789 struct dma_ops_domain *entry, *ret = NULL;
790 unsigned long flags;
791
792 if (list_empty(&iommu_pd_list))
793 return NULL;
794
795 spin_lock_irqsave(&iommu_pd_list_lock, flags);
796
797 list_for_each_entry(entry, &iommu_pd_list, list) {
798 if (entry->target_dev == devid) {
799 ret = entry;
800 list_del(&ret->list);
801 break;
802 }
803 }
804
805 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
806
807 return ret;
808 }
809
810 /*
811 * In the dma_ops path we only have the struct device. This function
812 * finds the corresponding IOMMU, the protection domain and the
813 * requestor id for a given device.
814 * If the device is not yet associated with a domain this is also done
815 * in this function.
816 */
817 static int get_device_resources(struct device *dev,
818 struct amd_iommu **iommu,
819 struct protection_domain **domain,
820 u16 *bdf)
821 {
822 struct dma_ops_domain *dma_dom;
823 struct pci_dev *pcidev;
824 u16 _bdf;
825
826 *iommu = NULL;
827 *domain = NULL;
828 *bdf = 0xffff;
829
830 if (dev->bus != &pci_bus_type)
831 return 0;
832
833 pcidev = to_pci_dev(dev);
834 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
835
836 /* device not translated by any IOMMU in the system? */
837 if (_bdf > amd_iommu_last_bdf)
838 return 0;
839
840 *bdf = amd_iommu_alias_table[_bdf];
841
842 *iommu = amd_iommu_rlookup_table[*bdf];
843 if (*iommu == NULL)
844 return 0;
845 *domain = domain_for_device(*bdf);
846 if (*domain == NULL) {
847 dma_dom = find_protection_domain(*bdf);
848 if (!dma_dom)
849 dma_dom = (*iommu)->default_dom;
850 *domain = &dma_dom->domain;
851 set_device_domain(*iommu, *domain, *bdf);
852 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
853 "device ", (*domain)->id);
854 print_devid(_bdf, 1);
855 }
856
857 return 1;
858 }
859
860 /*
861 * This is the generic map function. It maps one 4kb page at paddr to
862 * the given address in the DMA address space for the domain.
863 */
864 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
865 struct dma_ops_domain *dom,
866 unsigned long address,
867 phys_addr_t paddr,
868 int direction)
869 {
870 u64 *pte, __pte;
871
872 WARN_ON(address > dom->aperture_size);
873
874 paddr &= PAGE_MASK;
875
876 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
877 pte += IOMMU_PTE_L0_INDEX(address);
878
879 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
880
881 if (direction == DMA_TO_DEVICE)
882 __pte |= IOMMU_PTE_IR;
883 else if (direction == DMA_FROM_DEVICE)
884 __pte |= IOMMU_PTE_IW;
885 else if (direction == DMA_BIDIRECTIONAL)
886 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
887
888 WARN_ON(*pte);
889
890 *pte = __pte;
891
892 return (dma_addr_t)address;
893 }
894
895 /*
896 * The generic unmapping function for on page in the DMA address space.
897 */
898 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
899 struct dma_ops_domain *dom,
900 unsigned long address)
901 {
902 u64 *pte;
903
904 if (address >= dom->aperture_size)
905 return;
906
907 WARN_ON(address & 0xfffULL || address > dom->aperture_size);
908
909 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
910 pte += IOMMU_PTE_L0_INDEX(address);
911
912 WARN_ON(!*pte);
913
914 *pte = 0ULL;
915 }
916
917 /*
918 * This function contains common code for mapping of a physically
919 * contiguous memory region into DMA address space. It is uses by all
920 * mapping functions provided by this IOMMU driver.
921 * Must be called with the domain lock held.
922 */
923 static dma_addr_t __map_single(struct device *dev,
924 struct amd_iommu *iommu,
925 struct dma_ops_domain *dma_dom,
926 phys_addr_t paddr,
927 size_t size,
928 int dir,
929 bool align,
930 u64 dma_mask)
931 {
932 dma_addr_t offset = paddr & ~PAGE_MASK;
933 dma_addr_t address, start;
934 unsigned int pages;
935 unsigned long align_mask = 0;
936 int i;
937
938 pages = iommu_num_pages(paddr, size);
939 paddr &= PAGE_MASK;
940
941 if (align)
942 align_mask = (1UL << get_order(size)) - 1;
943
944 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
945 dma_mask);
946 if (unlikely(address == bad_dma_address))
947 goto out;
948
949 start = address;
950 for (i = 0; i < pages; ++i) {
951 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
952 paddr += PAGE_SIZE;
953 start += PAGE_SIZE;
954 }
955 address += offset;
956
957 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
958 iommu_flush_tlb(iommu, dma_dom->domain.id);
959 dma_dom->need_flush = false;
960 } else if (unlikely(iommu_has_npcache(iommu)))
961 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
962
963 out:
964 return address;
965 }
966
967 /*
968 * Does the reverse of the __map_single function. Must be called with
969 * the domain lock held too
970 */
971 static void __unmap_single(struct amd_iommu *iommu,
972 struct dma_ops_domain *dma_dom,
973 dma_addr_t dma_addr,
974 size_t size,
975 int dir)
976 {
977 dma_addr_t i, start;
978 unsigned int pages;
979
980 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
981 return;
982
983 pages = iommu_num_pages(dma_addr, size);
984 dma_addr &= PAGE_MASK;
985 start = dma_addr;
986
987 for (i = 0; i < pages; ++i) {
988 dma_ops_domain_unmap(iommu, dma_dom, start);
989 start += PAGE_SIZE;
990 }
991
992 dma_ops_free_addresses(dma_dom, dma_addr, pages);
993
994 if (amd_iommu_unmap_flush)
995 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
996 }
997
998 /*
999 * The exported map_single function for dma_ops.
1000 */
1001 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1002 size_t size, int dir)
1003 {
1004 unsigned long flags;
1005 struct amd_iommu *iommu;
1006 struct protection_domain *domain;
1007 u16 devid;
1008 dma_addr_t addr;
1009 u64 dma_mask;
1010
1011 if (!check_device(dev))
1012 return bad_dma_address;
1013
1014 dma_mask = *dev->dma_mask;
1015
1016 get_device_resources(dev, &iommu, &domain, &devid);
1017
1018 if (iommu == NULL || domain == NULL)
1019 /* device not handled by any AMD IOMMU */
1020 return (dma_addr_t)paddr;
1021
1022 spin_lock_irqsave(&domain->lock, flags);
1023 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1024 dma_mask);
1025 if (addr == bad_dma_address)
1026 goto out;
1027
1028 if (unlikely(iommu->need_sync))
1029 iommu_completion_wait(iommu);
1030
1031 out:
1032 spin_unlock_irqrestore(&domain->lock, flags);
1033
1034 return addr;
1035 }
1036
1037 /*
1038 * The exported unmap_single function for dma_ops.
1039 */
1040 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1041 size_t size, int dir)
1042 {
1043 unsigned long flags;
1044 struct amd_iommu *iommu;
1045 struct protection_domain *domain;
1046 u16 devid;
1047
1048 if (!check_device(dev) ||
1049 !get_device_resources(dev, &iommu, &domain, &devid))
1050 /* device not handled by any AMD IOMMU */
1051 return;
1052
1053 spin_lock_irqsave(&domain->lock, flags);
1054
1055 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1056
1057 if (unlikely(iommu->need_sync))
1058 iommu_completion_wait(iommu);
1059
1060 spin_unlock_irqrestore(&domain->lock, flags);
1061 }
1062
1063 /*
1064 * This is a special map_sg function which is used if we should map a
1065 * device which is not handled by an AMD IOMMU in the system.
1066 */
1067 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1068 int nelems, int dir)
1069 {
1070 struct scatterlist *s;
1071 int i;
1072
1073 for_each_sg(sglist, s, nelems, i) {
1074 s->dma_address = (dma_addr_t)sg_phys(s);
1075 s->dma_length = s->length;
1076 }
1077
1078 return nelems;
1079 }
1080
1081 /*
1082 * The exported map_sg function for dma_ops (handles scatter-gather
1083 * lists).
1084 */
1085 static int map_sg(struct device *dev, struct scatterlist *sglist,
1086 int nelems, int dir)
1087 {
1088 unsigned long flags;
1089 struct amd_iommu *iommu;
1090 struct protection_domain *domain;
1091 u16 devid;
1092 int i;
1093 struct scatterlist *s;
1094 phys_addr_t paddr;
1095 int mapped_elems = 0;
1096 u64 dma_mask;
1097
1098 if (!check_device(dev))
1099 return 0;
1100
1101 dma_mask = *dev->dma_mask;
1102
1103 get_device_resources(dev, &iommu, &domain, &devid);
1104
1105 if (!iommu || !domain)
1106 return map_sg_no_iommu(dev, sglist, nelems, dir);
1107
1108 spin_lock_irqsave(&domain->lock, flags);
1109
1110 for_each_sg(sglist, s, nelems, i) {
1111 paddr = sg_phys(s);
1112
1113 s->dma_address = __map_single(dev, iommu, domain->priv,
1114 paddr, s->length, dir, false,
1115 dma_mask);
1116
1117 if (s->dma_address) {
1118 s->dma_length = s->length;
1119 mapped_elems++;
1120 } else
1121 goto unmap;
1122 }
1123
1124 if (unlikely(iommu->need_sync))
1125 iommu_completion_wait(iommu);
1126
1127 out:
1128 spin_unlock_irqrestore(&domain->lock, flags);
1129
1130 return mapped_elems;
1131 unmap:
1132 for_each_sg(sglist, s, mapped_elems, i) {
1133 if (s->dma_address)
1134 __unmap_single(iommu, domain->priv, s->dma_address,
1135 s->dma_length, dir);
1136 s->dma_address = s->dma_length = 0;
1137 }
1138
1139 mapped_elems = 0;
1140
1141 goto out;
1142 }
1143
1144 /*
1145 * The exported map_sg function for dma_ops (handles scatter-gather
1146 * lists).
1147 */
1148 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1149 int nelems, int dir)
1150 {
1151 unsigned long flags;
1152 struct amd_iommu *iommu;
1153 struct protection_domain *domain;
1154 struct scatterlist *s;
1155 u16 devid;
1156 int i;
1157
1158 if (!check_device(dev) ||
1159 !get_device_resources(dev, &iommu, &domain, &devid))
1160 return;
1161
1162 spin_lock_irqsave(&domain->lock, flags);
1163
1164 for_each_sg(sglist, s, nelems, i) {
1165 __unmap_single(iommu, domain->priv, s->dma_address,
1166 s->dma_length, dir);
1167 s->dma_address = s->dma_length = 0;
1168 }
1169
1170 if (unlikely(iommu->need_sync))
1171 iommu_completion_wait(iommu);
1172
1173 spin_unlock_irqrestore(&domain->lock, flags);
1174 }
1175
1176 /*
1177 * The exported alloc_coherent function for dma_ops.
1178 */
1179 static void *alloc_coherent(struct device *dev, size_t size,
1180 dma_addr_t *dma_addr, gfp_t flag)
1181 {
1182 unsigned long flags;
1183 void *virt_addr;
1184 struct amd_iommu *iommu;
1185 struct protection_domain *domain;
1186 u16 devid;
1187 phys_addr_t paddr;
1188 u64 dma_mask = dev->coherent_dma_mask;
1189
1190 if (!check_device(dev))
1191 return NULL;
1192
1193 if (!get_device_resources(dev, &iommu, &domain, &devid))
1194 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1195
1196 flag |= __GFP_ZERO;
1197 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1198 if (!virt_addr)
1199 return 0;
1200
1201 paddr = virt_to_phys(virt_addr);
1202
1203 if (!iommu || !domain) {
1204 *dma_addr = (dma_addr_t)paddr;
1205 return virt_addr;
1206 }
1207
1208 if (!dma_mask)
1209 dma_mask = *dev->dma_mask;
1210
1211 spin_lock_irqsave(&domain->lock, flags);
1212
1213 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1214 size, DMA_BIDIRECTIONAL, true, dma_mask);
1215
1216 if (*dma_addr == bad_dma_address) {
1217 free_pages((unsigned long)virt_addr, get_order(size));
1218 virt_addr = NULL;
1219 goto out;
1220 }
1221
1222 if (unlikely(iommu->need_sync))
1223 iommu_completion_wait(iommu);
1224
1225 out:
1226 spin_unlock_irqrestore(&domain->lock, flags);
1227
1228 return virt_addr;
1229 }
1230
1231 /*
1232 * The exported free_coherent function for dma_ops.
1233 */
1234 static void free_coherent(struct device *dev, size_t size,
1235 void *virt_addr, dma_addr_t dma_addr)
1236 {
1237 unsigned long flags;
1238 struct amd_iommu *iommu;
1239 struct protection_domain *domain;
1240 u16 devid;
1241
1242 if (!check_device(dev))
1243 return;
1244
1245 get_device_resources(dev, &iommu, &domain, &devid);
1246
1247 if (!iommu || !domain)
1248 goto free_mem;
1249
1250 spin_lock_irqsave(&domain->lock, flags);
1251
1252 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1253
1254 if (unlikely(iommu->need_sync))
1255 iommu_completion_wait(iommu);
1256
1257 spin_unlock_irqrestore(&domain->lock, flags);
1258
1259 free_mem:
1260 free_pages((unsigned long)virt_addr, get_order(size));
1261 }
1262
1263 /*
1264 * This function is called by the DMA layer to find out if we can handle a
1265 * particular device. It is part of the dma_ops.
1266 */
1267 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1268 {
1269 u16 bdf;
1270 struct pci_dev *pcidev;
1271
1272 /* No device or no PCI device */
1273 if (!dev || dev->bus != &pci_bus_type)
1274 return 0;
1275
1276 pcidev = to_pci_dev(dev);
1277
1278 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1279
1280 /* Out of our scope? */
1281 if (bdf > amd_iommu_last_bdf)
1282 return 0;
1283
1284 return 1;
1285 }
1286
1287 /*
1288 * The function for pre-allocating protection domains.
1289 *
1290 * If the driver core informs the DMA layer if a driver grabs a device
1291 * we don't need to preallocate the protection domains anymore.
1292 * For now we have to.
1293 */
1294 void prealloc_protection_domains(void)
1295 {
1296 struct pci_dev *dev = NULL;
1297 struct dma_ops_domain *dma_dom;
1298 struct amd_iommu *iommu;
1299 int order = amd_iommu_aperture_order;
1300 u16 devid;
1301
1302 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1303 devid = (dev->bus->number << 8) | dev->devfn;
1304 if (devid > amd_iommu_last_bdf)
1305 continue;
1306 devid = amd_iommu_alias_table[devid];
1307 if (domain_for_device(devid))
1308 continue;
1309 iommu = amd_iommu_rlookup_table[devid];
1310 if (!iommu)
1311 continue;
1312 dma_dom = dma_ops_domain_alloc(iommu, order);
1313 if (!dma_dom)
1314 continue;
1315 init_unity_mappings_for_device(dma_dom, devid);
1316 dma_dom->target_dev = devid;
1317
1318 list_add_tail(&dma_dom->list, &iommu_pd_list);
1319 }
1320 }
1321
1322 static struct dma_mapping_ops amd_iommu_dma_ops = {
1323 .alloc_coherent = alloc_coherent,
1324 .free_coherent = free_coherent,
1325 .map_single = map_single,
1326 .unmap_single = unmap_single,
1327 .map_sg = map_sg,
1328 .unmap_sg = unmap_sg,
1329 .dma_supported = amd_iommu_dma_supported,
1330 };
1331
1332 /*
1333 * The function which clues the AMD IOMMU driver into dma_ops.
1334 */
1335 int __init amd_iommu_init_dma_ops(void)
1336 {
1337 struct amd_iommu *iommu;
1338 int order = amd_iommu_aperture_order;
1339 int ret;
1340
1341 /*
1342 * first allocate a default protection domain for every IOMMU we
1343 * found in the system. Devices not assigned to any other
1344 * protection domain will be assigned to the default one.
1345 */
1346 list_for_each_entry(iommu, &amd_iommu_list, list) {
1347 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1348 if (iommu->default_dom == NULL)
1349 return -ENOMEM;
1350 ret = iommu_init_unity_mappings(iommu);
1351 if (ret)
1352 goto free_domains;
1353 }
1354
1355 /*
1356 * If device isolation is enabled, pre-allocate the protection
1357 * domains for each device.
1358 */
1359 if (amd_iommu_isolate)
1360 prealloc_protection_domains();
1361
1362 iommu_detected = 1;
1363 force_iommu = 1;
1364 bad_dma_address = 0;
1365 #ifdef CONFIG_GART_IOMMU
1366 gart_iommu_aperture_disabled = 1;
1367 gart_iommu_aperture = 0;
1368 #endif
1369
1370 /* Make the driver finally visible to the drivers */
1371 dma_ops = &amd_iommu_dma_ops;
1372
1373 return 0;
1374
1375 free_domains:
1376
1377 list_for_each_entry(iommu, &amd_iommu_list, list) {
1378 if (iommu->default_dom)
1379 dma_ops_domain_free(iommu->default_dom);
1380 }
1381
1382 return ret;
1383 }
Linux kernel - Deliverables
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