2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list
);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops
;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
56 struct unity_map_entry
*e
);
57 static struct dma_ops_domain
*find_protection_domain(u16 devid
);
58 static u64
* alloc_pte(struct protection_domain
*dom
,
59 unsigned long address
, u64
60 **pte_page
, gfp_t gfp
);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
62 unsigned long start_page
,
64 static u64
*fetch_pte(struct protection_domain
*domain
,
65 unsigned long address
);
67 #ifndef BUS_NOTIFY_UNBOUND_DRIVER
68 #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
71 #ifdef CONFIG_AMD_IOMMU_STATS
74 * Initialization code for statistics collection
77 DECLARE_STATS_COUNTER(compl_wait
);
78 DECLARE_STATS_COUNTER(cnt_map_single
);
79 DECLARE_STATS_COUNTER(cnt_unmap_single
);
80 DECLARE_STATS_COUNTER(cnt_map_sg
);
81 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
82 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
83 DECLARE_STATS_COUNTER(cnt_free_coherent
);
84 DECLARE_STATS_COUNTER(cross_page
);
85 DECLARE_STATS_COUNTER(domain_flush_single
);
86 DECLARE_STATS_COUNTER(domain_flush_all
);
87 DECLARE_STATS_COUNTER(alloced_io_mem
);
88 DECLARE_STATS_COUNTER(total_map_requests
);
90 static struct dentry
*stats_dir
;
91 static struct dentry
*de_isolate
;
92 static struct dentry
*de_fflush
;
94 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
96 if (stats_dir
== NULL
)
99 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
103 static void amd_iommu_stats_init(void)
105 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
106 if (stats_dir
== NULL
)
109 de_isolate
= debugfs_create_bool("isolation", 0444, stats_dir
,
110 (u32
*)&amd_iommu_isolate
);
112 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
113 (u32
*)&amd_iommu_unmap_flush
);
115 amd_iommu_stats_add(&compl_wait
);
116 amd_iommu_stats_add(&cnt_map_single
);
117 amd_iommu_stats_add(&cnt_unmap_single
);
118 amd_iommu_stats_add(&cnt_map_sg
);
119 amd_iommu_stats_add(&cnt_unmap_sg
);
120 amd_iommu_stats_add(&cnt_alloc_coherent
);
121 amd_iommu_stats_add(&cnt_free_coherent
);
122 amd_iommu_stats_add(&cross_page
);
123 amd_iommu_stats_add(&domain_flush_single
);
124 amd_iommu_stats_add(&domain_flush_all
);
125 amd_iommu_stats_add(&alloced_io_mem
);
126 amd_iommu_stats_add(&total_map_requests
);
131 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
132 static int iommu_has_npcache(struct amd_iommu
*iommu
)
134 return iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
);
137 /****************************************************************************
139 * Interrupt handling functions
141 ****************************************************************************/
143 static void iommu_print_event(void *__evt
)
146 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
147 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
148 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
149 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
150 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
152 printk(KERN_ERR
"AMD IOMMU: Event logged [");
155 case EVENT_TYPE_ILL_DEV
:
156 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
157 "address=0x%016llx flags=0x%04x]\n",
158 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
161 case EVENT_TYPE_IO_FAULT
:
162 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
163 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
164 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
165 domid
, address
, flags
);
167 case EVENT_TYPE_DEV_TAB_ERR
:
168 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
169 "address=0x%016llx flags=0x%04x]\n",
170 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
173 case EVENT_TYPE_PAGE_TAB_ERR
:
174 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
175 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
176 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
177 domid
, address
, flags
);
179 case EVENT_TYPE_ILL_CMD
:
180 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
182 case EVENT_TYPE_CMD_HARD_ERR
:
183 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
184 "flags=0x%04x]\n", address
, flags
);
186 case EVENT_TYPE_IOTLB_INV_TO
:
187 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
188 "address=0x%016llx]\n",
189 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
192 case EVENT_TYPE_INV_DEV_REQ
:
193 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
194 "address=0x%016llx flags=0x%04x]\n",
195 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
199 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
203 static void iommu_poll_events(struct amd_iommu
*iommu
)
208 spin_lock_irqsave(&iommu
->lock
, flags
);
210 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
211 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
213 while (head
!= tail
) {
214 iommu_print_event(iommu
->evt_buf
+ head
);
215 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
218 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
220 spin_unlock_irqrestore(&iommu
->lock
, flags
);
223 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
225 struct amd_iommu
*iommu
;
227 for_each_iommu(iommu
)
228 iommu_poll_events(iommu
);
233 /****************************************************************************
235 * IOMMU command queuing functions
237 ****************************************************************************/
240 * Writes the command to the IOMMUs command buffer and informs the
241 * hardware about the new command. Must be called with iommu->lock held.
243 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
248 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
249 target
= iommu
->cmd_buf
+ tail
;
250 memcpy_toio(target
, cmd
, sizeof(*cmd
));
251 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
252 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
255 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
261 * General queuing function for commands. Takes iommu->lock and calls
262 * __iommu_queue_command().
264 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
269 spin_lock_irqsave(&iommu
->lock
, flags
);
270 ret
= __iommu_queue_command(iommu
, cmd
);
272 iommu
->need_sync
= true;
273 spin_unlock_irqrestore(&iommu
->lock
, flags
);
279 * This function waits until an IOMMU has completed a completion
282 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
288 INC_STATS_COUNTER(compl_wait
);
290 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
292 /* wait for the bit to become one */
293 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
294 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
297 /* set bit back to zero */
298 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
299 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
301 if (unlikely(i
== EXIT_LOOP_COUNT
))
302 panic("AMD IOMMU: Completion wait loop failed\n");
306 * This function queues a completion wait command into the command
309 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
311 struct iommu_cmd cmd
;
313 memset(&cmd
, 0, sizeof(cmd
));
314 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
315 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
317 return __iommu_queue_command(iommu
, &cmd
);
321 * This function is called whenever we need to ensure that the IOMMU has
322 * completed execution of all commands we sent. It sends a
323 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
324 * us about that by writing a value to a physical address we pass with
327 static int iommu_completion_wait(struct amd_iommu
*iommu
)
332 spin_lock_irqsave(&iommu
->lock
, flags
);
334 if (!iommu
->need_sync
)
337 ret
= __iommu_completion_wait(iommu
);
339 iommu
->need_sync
= false;
344 __iommu_wait_for_completion(iommu
);
347 spin_unlock_irqrestore(&iommu
->lock
, flags
);
353 * Command send function for invalidating a device table entry
355 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
357 struct iommu_cmd cmd
;
360 BUG_ON(iommu
== NULL
);
362 memset(&cmd
, 0, sizeof(cmd
));
363 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
366 ret
= iommu_queue_command(iommu
, &cmd
);
371 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
372 u16 domid
, int pde
, int s
)
374 memset(cmd
, 0, sizeof(*cmd
));
375 address
&= PAGE_MASK
;
376 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
377 cmd
->data
[1] |= domid
;
378 cmd
->data
[2] = lower_32_bits(address
);
379 cmd
->data
[3] = upper_32_bits(address
);
380 if (s
) /* size bit - we flush more than one 4kb page */
381 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
382 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
383 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
387 * Generic command send function for invalidaing TLB entries
389 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
390 u64 address
, u16 domid
, int pde
, int s
)
392 struct iommu_cmd cmd
;
395 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
397 ret
= iommu_queue_command(iommu
, &cmd
);
403 * TLB invalidation function which is called from the mapping functions.
404 * It invalidates a single PTE if the range to flush is within a single
405 * page. Otherwise it flushes the whole TLB of the IOMMU.
407 static int iommu_flush_pages(struct amd_iommu
*iommu
, u16 domid
,
408 u64 address
, size_t size
)
411 unsigned pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
413 address
&= PAGE_MASK
;
417 * If we have to flush more than one page, flush all
418 * TLB entries for this domain
420 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
424 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, s
);
429 /* Flush the whole IO/TLB for a given protection domain */
430 static void iommu_flush_tlb(struct amd_iommu
*iommu
, u16 domid
)
432 u64 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
434 INC_STATS_COUNTER(domain_flush_single
);
436 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, 1);
439 /* Flush the whole IO/TLB for a given protection domain - including PDE */
440 static void iommu_flush_tlb_pde(struct amd_iommu
*iommu
, u16 domid
)
442 u64 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
444 INC_STATS_COUNTER(domain_flush_single
);
446 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 1, 1);
450 * This function is used to flush the IO/TLB for a given protection domain
451 * on every IOMMU in the system
453 static void iommu_flush_domain(u16 domid
)
456 struct amd_iommu
*iommu
;
457 struct iommu_cmd cmd
;
459 INC_STATS_COUNTER(domain_flush_all
);
461 __iommu_build_inv_iommu_pages(&cmd
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
464 for_each_iommu(iommu
) {
465 spin_lock_irqsave(&iommu
->lock
, flags
);
466 __iommu_queue_command(iommu
, &cmd
);
467 __iommu_completion_wait(iommu
);
468 __iommu_wait_for_completion(iommu
);
469 spin_unlock_irqrestore(&iommu
->lock
, flags
);
473 void amd_iommu_flush_all_domains(void)
477 for (i
= 1; i
< MAX_DOMAIN_ID
; ++i
) {
478 if (!test_bit(i
, amd_iommu_pd_alloc_bitmap
))
480 iommu_flush_domain(i
);
484 void amd_iommu_flush_all_devices(void)
486 struct amd_iommu
*iommu
;
489 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
) {
490 if (amd_iommu_pd_table
[i
] == NULL
)
493 iommu
= amd_iommu_rlookup_table
[i
];
497 iommu_queue_inv_dev_entry(iommu
, i
);
498 iommu_completion_wait(iommu
);
502 /****************************************************************************
504 * The functions below are used the create the page table mappings for
505 * unity mapped regions.
507 ****************************************************************************/
510 * Generic mapping functions. It maps a physical address into a DMA
511 * address space. It allocates the page table pages if necessary.
512 * In the future it can be extended to a generic mapping function
513 * supporting all features of AMD IOMMU page tables like level skipping
514 * and full 64 bit address spaces.
516 static int iommu_map_page(struct protection_domain
*dom
,
517 unsigned long bus_addr
,
518 unsigned long phys_addr
,
523 bus_addr
= PAGE_ALIGN(bus_addr
);
524 phys_addr
= PAGE_ALIGN(phys_addr
);
526 /* only support 512GB address spaces for now */
527 if (bus_addr
> IOMMU_MAP_SIZE_L3
|| !(prot
& IOMMU_PROT_MASK
))
530 pte
= alloc_pte(dom
, bus_addr
, NULL
, GFP_KERNEL
);
532 if (IOMMU_PTE_PRESENT(*pte
))
535 __pte
= phys_addr
| IOMMU_PTE_P
;
536 if (prot
& IOMMU_PROT_IR
)
537 __pte
|= IOMMU_PTE_IR
;
538 if (prot
& IOMMU_PROT_IW
)
539 __pte
|= IOMMU_PTE_IW
;
546 static void iommu_unmap_page(struct protection_domain
*dom
,
547 unsigned long bus_addr
)
549 u64
*pte
= fetch_pte(dom
, bus_addr
);
556 * This function checks if a specific unity mapping entry is needed for
557 * this specific IOMMU.
559 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
560 struct unity_map_entry
*entry
)
564 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
565 bdf
= amd_iommu_alias_table
[i
];
566 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
574 * Init the unity mappings for a specific IOMMU in the system
576 * Basically iterates over all unity mapping entries and applies them to
577 * the default domain DMA of that IOMMU if necessary.
579 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
581 struct unity_map_entry
*entry
;
584 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
585 if (!iommu_for_unity_map(iommu
, entry
))
587 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
596 * This function actually applies the mapping to the page table of the
599 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
600 struct unity_map_entry
*e
)
605 for (addr
= e
->address_start
; addr
< e
->address_end
;
607 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
);
611 * if unity mapping is in aperture range mark the page
612 * as allocated in the aperture
614 if (addr
< dma_dom
->aperture_size
)
615 __set_bit(addr
>> PAGE_SHIFT
,
616 dma_dom
->aperture
[0]->bitmap
);
623 * Inits the unity mappings required for a specific device
625 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
628 struct unity_map_entry
*e
;
631 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
632 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
634 ret
= dma_ops_unity_map(dma_dom
, e
);
642 /****************************************************************************
644 * The next functions belong to the address allocator for the dma_ops
645 * interface functions. They work like the allocators in the other IOMMU
646 * drivers. Its basically a bitmap which marks the allocated pages in
647 * the aperture. Maybe it could be enhanced in the future to a more
648 * efficient allocator.
650 ****************************************************************************/
653 * The address allocator core functions.
655 * called with domain->lock held
659 * This function checks if there is a PTE for a given dma address. If
660 * there is one, it returns the pointer to it.
662 static u64
*fetch_pte(struct protection_domain
*domain
,
663 unsigned long address
)
668 level
= domain
->mode
- 1;
669 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
672 if (!IOMMU_PTE_PRESENT(*pte
))
677 pte
= IOMMU_PTE_PAGE(*pte
);
678 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
685 * This function is used to add a new aperture range to an existing
686 * aperture in case of dma_ops domain allocation or address allocation
689 static int alloc_new_range(struct amd_iommu
*iommu
,
690 struct dma_ops_domain
*dma_dom
,
691 bool populate
, gfp_t gfp
)
693 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
696 #ifdef CONFIG_IOMMU_STRESS
700 if (index
>= APERTURE_MAX_RANGES
)
703 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
704 if (!dma_dom
->aperture
[index
])
707 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
708 if (!dma_dom
->aperture
[index
]->bitmap
)
711 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
714 unsigned long address
= dma_dom
->aperture_size
;
715 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
718 for (i
= 0; i
< num_ptes
; ++i
) {
719 pte
= alloc_pte(&dma_dom
->domain
, address
,
724 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
726 address
+= APERTURE_RANGE_SIZE
/ 64;
730 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
732 /* Intialize the exclusion range if necessary */
733 if (iommu
->exclusion_start
&&
734 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
&&
735 iommu
->exclusion_start
< dma_dom
->aperture_size
) {
736 unsigned long startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
737 int pages
= iommu_num_pages(iommu
->exclusion_start
,
738 iommu
->exclusion_length
,
740 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
744 * Check for areas already mapped as present in the new aperture
745 * range and mark those pages as reserved in the allocator. Such
746 * mappings may already exist as a result of requested unity
747 * mappings for devices.
749 for (i
= dma_dom
->aperture
[index
]->offset
;
750 i
< dma_dom
->aperture_size
;
752 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
);
753 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
756 dma_ops_reserve_addresses(dma_dom
, i
<< PAGE_SHIFT
, 1);
762 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
764 kfree(dma_dom
->aperture
[index
]);
765 dma_dom
->aperture
[index
] = NULL
;
770 static unsigned long dma_ops_area_alloc(struct device
*dev
,
771 struct dma_ops_domain
*dom
,
773 unsigned long align_mask
,
777 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
778 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
779 int i
= start
>> APERTURE_RANGE_SHIFT
;
780 unsigned long boundary_size
;
781 unsigned long address
= -1;
784 next_bit
>>= PAGE_SHIFT
;
786 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
787 PAGE_SIZE
) >> PAGE_SHIFT
;
789 for (;i
< max_index
; ++i
) {
790 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
792 if (dom
->aperture
[i
]->offset
>= dma_mask
)
795 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
796 dma_mask
>> PAGE_SHIFT
);
798 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
799 limit
, next_bit
, pages
, 0,
800 boundary_size
, align_mask
);
802 address
= dom
->aperture
[i
]->offset
+
803 (address
<< PAGE_SHIFT
);
804 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
814 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
815 struct dma_ops_domain
*dom
,
817 unsigned long align_mask
,
820 unsigned long address
;
822 #ifdef CONFIG_IOMMU_STRESS
823 dom
->next_address
= 0;
824 dom
->need_flush
= true;
827 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
828 dma_mask
, dom
->next_address
);
831 dom
->next_address
= 0;
832 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
834 dom
->need_flush
= true;
837 if (unlikely(address
== -1))
838 address
= bad_dma_address
;
840 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
846 * The address free function.
848 * called with domain->lock held
850 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
851 unsigned long address
,
854 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
855 struct aperture_range
*range
= dom
->aperture
[i
];
857 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
859 #ifdef CONFIG_IOMMU_STRESS
864 if (address
>= dom
->next_address
)
865 dom
->need_flush
= true;
867 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
869 iommu_area_free(range
->bitmap
, address
, pages
);
873 /****************************************************************************
875 * The next functions belong to the domain allocation. A domain is
876 * allocated for every IOMMU as the default domain. If device isolation
877 * is enabled, every device get its own domain. The most important thing
878 * about domains is the page table mapping the DMA address space they
881 ****************************************************************************/
883 static u16
domain_id_alloc(void)
888 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
889 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
891 if (id
> 0 && id
< MAX_DOMAIN_ID
)
892 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
895 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
900 static void domain_id_free(int id
)
904 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
905 if (id
> 0 && id
< MAX_DOMAIN_ID
)
906 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
907 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
911 * Used to reserve address ranges in the aperture (e.g. for exclusion
914 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
915 unsigned long start_page
,
918 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
920 if (start_page
+ pages
> last_page
)
921 pages
= last_page
- start_page
;
923 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
924 int index
= i
/ APERTURE_RANGE_PAGES
;
925 int page
= i
% APERTURE_RANGE_PAGES
;
926 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
930 static void free_pagetable(struct protection_domain
*domain
)
935 p1
= domain
->pt_root
;
940 for (i
= 0; i
< 512; ++i
) {
941 if (!IOMMU_PTE_PRESENT(p1
[i
]))
944 p2
= IOMMU_PTE_PAGE(p1
[i
]);
945 for (j
= 0; j
< 512; ++j
) {
946 if (!IOMMU_PTE_PRESENT(p2
[j
]))
948 p3
= IOMMU_PTE_PAGE(p2
[j
]);
949 free_page((unsigned long)p3
);
952 free_page((unsigned long)p2
);
955 free_page((unsigned long)p1
);
957 domain
->pt_root
= NULL
;
961 * Free a domain, only used if something went wrong in the
962 * allocation path and we need to free an already allocated page table
964 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
971 free_pagetable(&dom
->domain
);
973 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
974 if (!dom
->aperture
[i
])
976 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
977 kfree(dom
->aperture
[i
]);
984 * Allocates a new protection domain usable for the dma_ops functions.
985 * It also intializes the page table and the address allocator data
986 * structures required for the dma_ops interface
988 static struct dma_ops_domain
*dma_ops_domain_alloc(struct amd_iommu
*iommu
)
990 struct dma_ops_domain
*dma_dom
;
992 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
996 spin_lock_init(&dma_dom
->domain
.lock
);
998 dma_dom
->domain
.id
= domain_id_alloc();
999 if (dma_dom
->domain
.id
== 0)
1001 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
1002 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1003 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1004 dma_dom
->domain
.priv
= dma_dom
;
1005 if (!dma_dom
->domain
.pt_root
)
1008 dma_dom
->need_flush
= false;
1009 dma_dom
->target_dev
= 0xffff;
1011 if (alloc_new_range(iommu
, dma_dom
, true, GFP_KERNEL
))
1015 * mark the first page as allocated so we never return 0 as
1016 * a valid dma-address. So we can use 0 as error value
1018 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1019 dma_dom
->next_address
= 0;
1025 dma_ops_domain_free(dma_dom
);
1031 * little helper function to check whether a given protection domain is a
1034 static bool dma_ops_domain(struct protection_domain
*domain
)
1036 return domain
->flags
& PD_DMA_OPS_MASK
;
1040 * Find out the protection domain structure for a given PCI device. This
1041 * will give us the pointer to the page table root for example.
1043 static struct protection_domain
*domain_for_device(u16 devid
)
1045 struct protection_domain
*dom
;
1046 unsigned long flags
;
1048 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1049 dom
= amd_iommu_pd_table
[devid
];
1050 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1056 * If a device is not yet associated with a domain, this function does
1057 * assigns it visible for the hardware
1059 static void attach_device(struct amd_iommu
*iommu
,
1060 struct protection_domain
*domain
,
1063 unsigned long flags
;
1064 u64 pte_root
= virt_to_phys(domain
->pt_root
);
1066 domain
->dev_cnt
+= 1;
1068 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1069 << DEV_ENTRY_MODE_SHIFT
;
1070 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1072 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1073 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
1074 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
1075 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
1077 amd_iommu_pd_table
[devid
] = domain
;
1078 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1081 * We might boot into a crash-kernel here. The crashed kernel
1082 * left the caches in the IOMMU dirty. So we have to flush
1083 * here to evict all dirty stuff.
1085 iommu_queue_inv_dev_entry(iommu
, devid
);
1086 iommu_flush_tlb_pde(iommu
, domain
->id
);
1090 * Removes a device from a protection domain (unlocked)
1092 static void __detach_device(struct protection_domain
*domain
, u16 devid
)
1096 spin_lock(&domain
->lock
);
1098 /* remove domain from the lookup table */
1099 amd_iommu_pd_table
[devid
] = NULL
;
1101 /* remove entry from the device table seen by the hardware */
1102 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1103 amd_iommu_dev_table
[devid
].data
[1] = 0;
1104 amd_iommu_dev_table
[devid
].data
[2] = 0;
1106 /* decrease reference counter */
1107 domain
->dev_cnt
-= 1;
1110 spin_unlock(&domain
->lock
);
1114 * Removes a device from a protection domain (with devtable_lock held)
1116 static void detach_device(struct protection_domain
*domain
, u16 devid
)
1118 unsigned long flags
;
1120 /* lock device table */
1121 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1122 __detach_device(domain
, devid
);
1123 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1126 static int device_change_notifier(struct notifier_block
*nb
,
1127 unsigned long action
, void *data
)
1129 struct device
*dev
= data
;
1130 struct pci_dev
*pdev
= to_pci_dev(dev
);
1131 u16 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
1132 struct protection_domain
*domain
;
1133 struct dma_ops_domain
*dma_domain
;
1134 struct amd_iommu
*iommu
;
1135 unsigned long flags
;
1137 if (devid
> amd_iommu_last_bdf
)
1140 devid
= amd_iommu_alias_table
[devid
];
1142 iommu
= amd_iommu_rlookup_table
[devid
];
1146 domain
= domain_for_device(devid
);
1148 if (domain
&& !dma_ops_domain(domain
))
1149 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1150 "to a non-dma-ops domain\n", dev_name(dev
));
1153 case BUS_NOTIFY_UNBOUND_DRIVER
:
1156 detach_device(domain
, devid
);
1158 case BUS_NOTIFY_ADD_DEVICE
:
1159 /* allocate a protection domain if a device is added */
1160 dma_domain
= find_protection_domain(devid
);
1163 dma_domain
= dma_ops_domain_alloc(iommu
);
1166 dma_domain
->target_dev
= devid
;
1168 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1169 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1170 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1177 iommu_queue_inv_dev_entry(iommu
, devid
);
1178 iommu_completion_wait(iommu
);
1184 static struct notifier_block device_nb
= {
1185 .notifier_call
= device_change_notifier
,
1188 /*****************************************************************************
1190 * The next functions belong to the dma_ops mapping/unmapping code.
1192 *****************************************************************************/
1195 * This function checks if the driver got a valid device from the caller to
1196 * avoid dereferencing invalid pointers.
1198 static bool check_device(struct device
*dev
)
1200 if (!dev
|| !dev
->dma_mask
)
1207 * In this function the list of preallocated protection domains is traversed to
1208 * find the domain for a specific device
1210 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
1212 struct dma_ops_domain
*entry
, *ret
= NULL
;
1213 unsigned long flags
;
1215 if (list_empty(&iommu_pd_list
))
1218 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1220 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
1221 if (entry
->target_dev
== devid
) {
1227 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1233 * In the dma_ops path we only have the struct device. This function
1234 * finds the corresponding IOMMU, the protection domain and the
1235 * requestor id for a given device.
1236 * If the device is not yet associated with a domain this is also done
1239 static int get_device_resources(struct device
*dev
,
1240 struct amd_iommu
**iommu
,
1241 struct protection_domain
**domain
,
1244 struct dma_ops_domain
*dma_dom
;
1245 struct pci_dev
*pcidev
;
1252 if (dev
->bus
!= &pci_bus_type
)
1255 pcidev
= to_pci_dev(dev
);
1256 _bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
1258 /* device not translated by any IOMMU in the system? */
1259 if (_bdf
> amd_iommu_last_bdf
)
1262 *bdf
= amd_iommu_alias_table
[_bdf
];
1264 *iommu
= amd_iommu_rlookup_table
[*bdf
];
1267 *domain
= domain_for_device(*bdf
);
1268 if (*domain
== NULL
) {
1269 dma_dom
= find_protection_domain(*bdf
);
1271 dma_dom
= (*iommu
)->default_dom
;
1272 *domain
= &dma_dom
->domain
;
1273 attach_device(*iommu
, *domain
, *bdf
);
1274 DUMP_printk("Using protection domain %d for device %s\n",
1275 (*domain
)->id
, dev_name(dev
));
1278 if (domain_for_device(_bdf
) == NULL
)
1279 attach_device(*iommu
, *domain
, _bdf
);
1285 * If the pte_page is not yet allocated this function is called
1287 static u64
* alloc_pte(struct protection_domain
*dom
,
1288 unsigned long address
, u64
**pte_page
, gfp_t gfp
)
1292 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(address
)];
1294 if (!IOMMU_PTE_PRESENT(*pte
)) {
1295 page
= (u64
*)get_zeroed_page(gfp
);
1298 *pte
= IOMMU_L2_PDE(virt_to_phys(page
));
1301 pte
= IOMMU_PTE_PAGE(*pte
);
1302 pte
= &pte
[IOMMU_PTE_L1_INDEX(address
)];
1304 if (!IOMMU_PTE_PRESENT(*pte
)) {
1305 page
= (u64
*)get_zeroed_page(gfp
);
1308 *pte
= IOMMU_L1_PDE(virt_to_phys(page
));
1311 pte
= IOMMU_PTE_PAGE(*pte
);
1316 pte
= &pte
[IOMMU_PTE_L0_INDEX(address
)];
1322 * This function fetches the PTE for a given address in the aperture
1324 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
1325 unsigned long address
)
1327 struct aperture_range
*aperture
;
1328 u64
*pte
, *pte_page
;
1330 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1334 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1336 pte
= alloc_pte(&dom
->domain
, address
, &pte_page
, GFP_ATOMIC
);
1337 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
1339 pte
+= IOMMU_PTE_L0_INDEX(address
);
1345 * This is the generic map function. It maps one 4kb page at paddr to
1346 * the given address in the DMA address space for the domain.
1348 static dma_addr_t
dma_ops_domain_map(struct amd_iommu
*iommu
,
1349 struct dma_ops_domain
*dom
,
1350 unsigned long address
,
1356 WARN_ON(address
> dom
->aperture_size
);
1360 pte
= dma_ops_get_pte(dom
, address
);
1362 return bad_dma_address
;
1364 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1366 if (direction
== DMA_TO_DEVICE
)
1367 __pte
|= IOMMU_PTE_IR
;
1368 else if (direction
== DMA_FROM_DEVICE
)
1369 __pte
|= IOMMU_PTE_IW
;
1370 else if (direction
== DMA_BIDIRECTIONAL
)
1371 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1377 return (dma_addr_t
)address
;
1381 * The generic unmapping function for on page in the DMA address space.
1383 static void dma_ops_domain_unmap(struct amd_iommu
*iommu
,
1384 struct dma_ops_domain
*dom
,
1385 unsigned long address
)
1387 struct aperture_range
*aperture
;
1390 if (address
>= dom
->aperture_size
)
1393 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1397 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1401 pte
+= IOMMU_PTE_L0_INDEX(address
);
1409 * This function contains common code for mapping of a physically
1410 * contiguous memory region into DMA address space. It is used by all
1411 * mapping functions provided with this IOMMU driver.
1412 * Must be called with the domain lock held.
1414 static dma_addr_t
__map_single(struct device
*dev
,
1415 struct amd_iommu
*iommu
,
1416 struct dma_ops_domain
*dma_dom
,
1423 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1424 dma_addr_t address
, start
, ret
;
1426 unsigned long align_mask
= 0;
1429 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1432 INC_STATS_COUNTER(total_map_requests
);
1435 INC_STATS_COUNTER(cross_page
);
1438 align_mask
= (1UL << get_order(size
)) - 1;
1441 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1443 if (unlikely(address
== bad_dma_address
)) {
1445 * setting next_address here will let the address
1446 * allocator only scan the new allocated range in the
1447 * first run. This is a small optimization.
1449 dma_dom
->next_address
= dma_dom
->aperture_size
;
1451 if (alloc_new_range(iommu
, dma_dom
, false, GFP_ATOMIC
))
1455 * aperture was sucessfully enlarged by 128 MB, try
1462 for (i
= 0; i
< pages
; ++i
) {
1463 ret
= dma_ops_domain_map(iommu
, dma_dom
, start
, paddr
, dir
);
1464 if (ret
== bad_dma_address
)
1472 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1474 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1475 iommu_flush_tlb(iommu
, dma_dom
->domain
.id
);
1476 dma_dom
->need_flush
= false;
1477 } else if (unlikely(iommu_has_npcache(iommu
)))
1478 iommu_flush_pages(iommu
, dma_dom
->domain
.id
, address
, size
);
1485 for (--i
; i
>= 0; --i
) {
1487 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
1490 dma_ops_free_addresses(dma_dom
, address
, pages
);
1492 return bad_dma_address
;
1496 * Does the reverse of the __map_single function. Must be called with
1497 * the domain lock held too
1499 static void __unmap_single(struct amd_iommu
*iommu
,
1500 struct dma_ops_domain
*dma_dom
,
1501 dma_addr_t dma_addr
,
1505 dma_addr_t i
, start
;
1508 if ((dma_addr
== bad_dma_address
) ||
1509 (dma_addr
+ size
> dma_dom
->aperture_size
))
1512 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1513 dma_addr
&= PAGE_MASK
;
1516 for (i
= 0; i
< pages
; ++i
) {
1517 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
1521 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1523 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1525 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
1526 iommu_flush_pages(iommu
, dma_dom
->domain
.id
, dma_addr
, size
);
1527 dma_dom
->need_flush
= false;
1532 * The exported map_single function for dma_ops.
1534 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
1535 unsigned long offset
, size_t size
,
1536 enum dma_data_direction dir
,
1537 struct dma_attrs
*attrs
)
1539 unsigned long flags
;
1540 struct amd_iommu
*iommu
;
1541 struct protection_domain
*domain
;
1545 phys_addr_t paddr
= page_to_phys(page
) + offset
;
1547 INC_STATS_COUNTER(cnt_map_single
);
1549 if (!check_device(dev
))
1550 return bad_dma_address
;
1552 dma_mask
= *dev
->dma_mask
;
1554 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1556 if (iommu
== NULL
|| domain
== NULL
)
1557 /* device not handled by any AMD IOMMU */
1558 return (dma_addr_t
)paddr
;
1560 if (!dma_ops_domain(domain
))
1561 return bad_dma_address
;
1563 spin_lock_irqsave(&domain
->lock
, flags
);
1564 addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
, size
, dir
, false,
1566 if (addr
== bad_dma_address
)
1569 iommu_completion_wait(iommu
);
1572 spin_unlock_irqrestore(&domain
->lock
, flags
);
1578 * The exported unmap_single function for dma_ops.
1580 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
1581 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
1583 unsigned long flags
;
1584 struct amd_iommu
*iommu
;
1585 struct protection_domain
*domain
;
1588 INC_STATS_COUNTER(cnt_unmap_single
);
1590 if (!check_device(dev
) ||
1591 !get_device_resources(dev
, &iommu
, &domain
, &devid
))
1592 /* device not handled by any AMD IOMMU */
1595 if (!dma_ops_domain(domain
))
1598 spin_lock_irqsave(&domain
->lock
, flags
);
1600 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, dir
);
1602 iommu_completion_wait(iommu
);
1604 spin_unlock_irqrestore(&domain
->lock
, flags
);
1608 * This is a special map_sg function which is used if we should map a
1609 * device which is not handled by an AMD IOMMU in the system.
1611 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
1612 int nelems
, int dir
)
1614 struct scatterlist
*s
;
1617 for_each_sg(sglist
, s
, nelems
, i
) {
1618 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
1619 s
->dma_length
= s
->length
;
1626 * The exported map_sg function for dma_ops (handles scatter-gather
1629 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
1630 int nelems
, enum dma_data_direction dir
,
1631 struct dma_attrs
*attrs
)
1633 unsigned long flags
;
1634 struct amd_iommu
*iommu
;
1635 struct protection_domain
*domain
;
1638 struct scatterlist
*s
;
1640 int mapped_elems
= 0;
1643 INC_STATS_COUNTER(cnt_map_sg
);
1645 if (!check_device(dev
))
1648 dma_mask
= *dev
->dma_mask
;
1650 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1652 if (!iommu
|| !domain
)
1653 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
1655 if (!dma_ops_domain(domain
))
1658 spin_lock_irqsave(&domain
->lock
, flags
);
1660 for_each_sg(sglist
, s
, nelems
, i
) {
1663 s
->dma_address
= __map_single(dev
, iommu
, domain
->priv
,
1664 paddr
, s
->length
, dir
, false,
1667 if (s
->dma_address
) {
1668 s
->dma_length
= s
->length
;
1674 iommu_completion_wait(iommu
);
1677 spin_unlock_irqrestore(&domain
->lock
, flags
);
1679 return mapped_elems
;
1681 for_each_sg(sglist
, s
, mapped_elems
, i
) {
1683 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
1684 s
->dma_length
, dir
);
1685 s
->dma_address
= s
->dma_length
= 0;
1694 * The exported map_sg function for dma_ops (handles scatter-gather
1697 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
1698 int nelems
, enum dma_data_direction dir
,
1699 struct dma_attrs
*attrs
)
1701 unsigned long flags
;
1702 struct amd_iommu
*iommu
;
1703 struct protection_domain
*domain
;
1704 struct scatterlist
*s
;
1708 INC_STATS_COUNTER(cnt_unmap_sg
);
1710 if (!check_device(dev
) ||
1711 !get_device_resources(dev
, &iommu
, &domain
, &devid
))
1714 if (!dma_ops_domain(domain
))
1717 spin_lock_irqsave(&domain
->lock
, flags
);
1719 for_each_sg(sglist
, s
, nelems
, i
) {
1720 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
1721 s
->dma_length
, dir
);
1722 s
->dma_address
= s
->dma_length
= 0;
1725 iommu_completion_wait(iommu
);
1727 spin_unlock_irqrestore(&domain
->lock
, flags
);
1731 * The exported alloc_coherent function for dma_ops.
1733 static void *alloc_coherent(struct device
*dev
, size_t size
,
1734 dma_addr_t
*dma_addr
, gfp_t flag
)
1736 unsigned long flags
;
1738 struct amd_iommu
*iommu
;
1739 struct protection_domain
*domain
;
1742 u64 dma_mask
= dev
->coherent_dma_mask
;
1744 INC_STATS_COUNTER(cnt_alloc_coherent
);
1746 if (!check_device(dev
))
1749 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
1750 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
1753 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
1757 paddr
= virt_to_phys(virt_addr
);
1759 if (!iommu
|| !domain
) {
1760 *dma_addr
= (dma_addr_t
)paddr
;
1764 if (!dma_ops_domain(domain
))
1768 dma_mask
= *dev
->dma_mask
;
1770 spin_lock_irqsave(&domain
->lock
, flags
);
1772 *dma_addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
,
1773 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
1775 if (*dma_addr
== bad_dma_address
) {
1776 spin_unlock_irqrestore(&domain
->lock
, flags
);
1780 iommu_completion_wait(iommu
);
1782 spin_unlock_irqrestore(&domain
->lock
, flags
);
1788 free_pages((unsigned long)virt_addr
, get_order(size
));
1794 * The exported free_coherent function for dma_ops.
1796 static void free_coherent(struct device
*dev
, size_t size
,
1797 void *virt_addr
, dma_addr_t dma_addr
)
1799 unsigned long flags
;
1800 struct amd_iommu
*iommu
;
1801 struct protection_domain
*domain
;
1804 INC_STATS_COUNTER(cnt_free_coherent
);
1806 if (!check_device(dev
))
1809 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1811 if (!iommu
|| !domain
)
1814 if (!dma_ops_domain(domain
))
1817 spin_lock_irqsave(&domain
->lock
, flags
);
1819 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
1821 iommu_completion_wait(iommu
);
1823 spin_unlock_irqrestore(&domain
->lock
, flags
);
1826 free_pages((unsigned long)virt_addr
, get_order(size
));
1830 * This function is called by the DMA layer to find out if we can handle a
1831 * particular device. It is part of the dma_ops.
1833 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
1836 struct pci_dev
*pcidev
;
1838 /* No device or no PCI device */
1839 if (!dev
|| dev
->bus
!= &pci_bus_type
)
1842 pcidev
= to_pci_dev(dev
);
1844 bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
1846 /* Out of our scope? */
1847 if (bdf
> amd_iommu_last_bdf
)
1854 * The function for pre-allocating protection domains.
1856 * If the driver core informs the DMA layer if a driver grabs a device
1857 * we don't need to preallocate the protection domains anymore.
1858 * For now we have to.
1860 static void prealloc_protection_domains(void)
1862 struct pci_dev
*dev
= NULL
;
1863 struct dma_ops_domain
*dma_dom
;
1864 struct amd_iommu
*iommu
;
1867 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1868 devid
= calc_devid(dev
->bus
->number
, dev
->devfn
);
1869 if (devid
> amd_iommu_last_bdf
)
1871 devid
= amd_iommu_alias_table
[devid
];
1872 if (domain_for_device(devid
))
1874 iommu
= amd_iommu_rlookup_table
[devid
];
1877 dma_dom
= dma_ops_domain_alloc(iommu
);
1880 init_unity_mappings_for_device(dma_dom
, devid
);
1881 dma_dom
->target_dev
= devid
;
1883 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
1887 static struct dma_map_ops amd_iommu_dma_ops
= {
1888 .alloc_coherent
= alloc_coherent
,
1889 .free_coherent
= free_coherent
,
1890 .map_page
= map_page
,
1891 .unmap_page
= unmap_page
,
1893 .unmap_sg
= unmap_sg
,
1894 .dma_supported
= amd_iommu_dma_supported
,
1898 * The function which clues the AMD IOMMU driver into dma_ops.
1900 int __init
amd_iommu_init_dma_ops(void)
1902 struct amd_iommu
*iommu
;
1906 * first allocate a default protection domain for every IOMMU we
1907 * found in the system. Devices not assigned to any other
1908 * protection domain will be assigned to the default one.
1910 for_each_iommu(iommu
) {
1911 iommu
->default_dom
= dma_ops_domain_alloc(iommu
);
1912 if (iommu
->default_dom
== NULL
)
1914 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
1915 ret
= iommu_init_unity_mappings(iommu
);
1921 * If device isolation is enabled, pre-allocate the protection
1922 * domains for each device.
1924 if (amd_iommu_isolate
)
1925 prealloc_protection_domains();
1929 bad_dma_address
= 0;
1930 #ifdef CONFIG_GART_IOMMU
1931 gart_iommu_aperture_disabled
= 1;
1932 gart_iommu_aperture
= 0;
1935 /* Make the driver finally visible to the drivers */
1936 dma_ops
= &amd_iommu_dma_ops
;
1938 register_iommu(&amd_iommu_ops
);
1940 bus_register_notifier(&pci_bus_type
, &device_nb
);
1942 amd_iommu_stats_init();
1948 for_each_iommu(iommu
) {
1949 if (iommu
->default_dom
)
1950 dma_ops_domain_free(iommu
->default_dom
);
1956 /*****************************************************************************
1958 * The following functions belong to the exported interface of AMD IOMMU
1960 * This interface allows access to lower level functions of the IOMMU
1961 * like protection domain handling and assignement of devices to domains
1962 * which is not possible with the dma_ops interface.
1964 *****************************************************************************/
1966 static void cleanup_domain(struct protection_domain
*domain
)
1968 unsigned long flags
;
1971 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1973 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
)
1974 if (amd_iommu_pd_table
[devid
] == domain
)
1975 __detach_device(domain
, devid
);
1977 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1980 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
1982 struct protection_domain
*domain
;
1984 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
1988 spin_lock_init(&domain
->lock
);
1989 domain
->mode
= PAGE_MODE_3_LEVEL
;
1990 domain
->id
= domain_id_alloc();
1993 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1994 if (!domain
->pt_root
)
2007 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
2009 struct protection_domain
*domain
= dom
->priv
;
2014 if (domain
->dev_cnt
> 0)
2015 cleanup_domain(domain
);
2017 BUG_ON(domain
->dev_cnt
!= 0);
2019 free_pagetable(domain
);
2021 domain_id_free(domain
->id
);
2028 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
2031 struct protection_domain
*domain
= dom
->priv
;
2032 struct amd_iommu
*iommu
;
2033 struct pci_dev
*pdev
;
2036 if (dev
->bus
!= &pci_bus_type
)
2039 pdev
= to_pci_dev(dev
);
2041 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
2044 detach_device(domain
, devid
);
2046 iommu
= amd_iommu_rlookup_table
[devid
];
2050 iommu_queue_inv_dev_entry(iommu
, devid
);
2051 iommu_completion_wait(iommu
);
2054 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
2057 struct protection_domain
*domain
= dom
->priv
;
2058 struct protection_domain
*old_domain
;
2059 struct amd_iommu
*iommu
;
2060 struct pci_dev
*pdev
;
2063 if (dev
->bus
!= &pci_bus_type
)
2066 pdev
= to_pci_dev(dev
);
2068 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
2070 if (devid
>= amd_iommu_last_bdf
||
2071 devid
!= amd_iommu_alias_table
[devid
])
2074 iommu
= amd_iommu_rlookup_table
[devid
];
2078 old_domain
= domain_for_device(devid
);
2080 detach_device(old_domain
, devid
);
2082 attach_device(iommu
, domain
, devid
);
2084 iommu_completion_wait(iommu
);
2089 static int amd_iommu_map_range(struct iommu_domain
*dom
,
2090 unsigned long iova
, phys_addr_t paddr
,
2091 size_t size
, int iommu_prot
)
2093 struct protection_domain
*domain
= dom
->priv
;
2094 unsigned long i
, npages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2098 if (iommu_prot
& IOMMU_READ
)
2099 prot
|= IOMMU_PROT_IR
;
2100 if (iommu_prot
& IOMMU_WRITE
)
2101 prot
|= IOMMU_PROT_IW
;
2106 for (i
= 0; i
< npages
; ++i
) {
2107 ret
= iommu_map_page(domain
, iova
, paddr
, prot
);
2118 static void amd_iommu_unmap_range(struct iommu_domain
*dom
,
2119 unsigned long iova
, size_t size
)
2122 struct protection_domain
*domain
= dom
->priv
;
2123 unsigned long i
, npages
= iommu_num_pages(iova
, size
, PAGE_SIZE
);
2127 for (i
= 0; i
< npages
; ++i
) {
2128 iommu_unmap_page(domain
, iova
);
2132 iommu_flush_domain(domain
->id
);
2135 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
2138 struct protection_domain
*domain
= dom
->priv
;
2139 unsigned long offset
= iova
& ~PAGE_MASK
;
2143 pte
= &domain
->pt_root
[IOMMU_PTE_L2_INDEX(iova
)];
2145 if (!IOMMU_PTE_PRESENT(*pte
))
2148 pte
= IOMMU_PTE_PAGE(*pte
);
2149 pte
= &pte
[IOMMU_PTE_L1_INDEX(iova
)];
2151 if (!IOMMU_PTE_PRESENT(*pte
))
2154 pte
= IOMMU_PTE_PAGE(*pte
);
2155 pte
= &pte
[IOMMU_PTE_L0_INDEX(iova
)];
2157 if (!IOMMU_PTE_PRESENT(*pte
))
2160 paddr
= *pte
& IOMMU_PAGE_MASK
;
2166 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
2172 static struct iommu_ops amd_iommu_ops
= {
2173 .domain_init
= amd_iommu_domain_init
,
2174 .domain_destroy
= amd_iommu_domain_destroy
,
2175 .attach_dev
= amd_iommu_attach_device
,
2176 .detach_dev
= amd_iommu_detach_device
,
2177 .map
= amd_iommu_map_range
,
2178 .unmap
= amd_iommu_unmap_range
,
2179 .iova_to_phys
= amd_iommu_iova_to_phys
,
2180 .domain_has_cap
= amd_iommu_domain_has_cap
,