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Merge branches 'dma-debug/next', 'amd-iommu/command-cleanups', 'amd-iommu/ats' and...
[deliverable/linux.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/pci-ats.h>
22 #include <linux/bitmap.h>
23 #include <linux/slab.h>
24 #include <linux/debugfs.h>
25 #include <linux/scatterlist.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/iommu-helper.h>
28 #include <linux/iommu.h>
29 #include <linux/delay.h>
30 #include <asm/proto.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/amd_iommu_proto.h>
34 #include <asm/amd_iommu_types.h>
35 #include <asm/amd_iommu.h>
36
37 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
38
39 #define LOOP_TIMEOUT 100000
40
41 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
42
43 /* A list of preallocated protection domains */
44 static LIST_HEAD(iommu_pd_list);
45 static DEFINE_SPINLOCK(iommu_pd_list_lock);
46
47 /*
48 * Domain for untranslated devices - only allocated
49 * if iommu=pt passed on kernel cmd line.
50 */
51 static struct protection_domain *pt_domain;
52
53 static struct iommu_ops amd_iommu_ops;
54
55 /*
56 * general struct to manage commands send to an IOMMU
57 */
58 struct iommu_cmd {
59 u32 data[4];
60 };
61
62 static void update_domain(struct protection_domain *domain);
63
64 /****************************************************************************
65 *
66 * Helper functions
67 *
68 ****************************************************************************/
69
70 static inline u16 get_device_id(struct device *dev)
71 {
72 struct pci_dev *pdev = to_pci_dev(dev);
73
74 return calc_devid(pdev->bus->number, pdev->devfn);
75 }
76
77 static struct iommu_dev_data *get_dev_data(struct device *dev)
78 {
79 return dev->archdata.iommu;
80 }
81
82 /*
83 * In this function the list of preallocated protection domains is traversed to
84 * find the domain for a specific device
85 */
86 static struct dma_ops_domain *find_protection_domain(u16 devid)
87 {
88 struct dma_ops_domain *entry, *ret = NULL;
89 unsigned long flags;
90 u16 alias = amd_iommu_alias_table[devid];
91
92 if (list_empty(&iommu_pd_list))
93 return NULL;
94
95 spin_lock_irqsave(&iommu_pd_list_lock, flags);
96
97 list_for_each_entry(entry, &iommu_pd_list, list) {
98 if (entry->target_dev == devid ||
99 entry->target_dev == alias) {
100 ret = entry;
101 break;
102 }
103 }
104
105 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
106
107 return ret;
108 }
109
110 /*
111 * This function checks if the driver got a valid device from the caller to
112 * avoid dereferencing invalid pointers.
113 */
114 static bool check_device(struct device *dev)
115 {
116 u16 devid;
117
118 if (!dev || !dev->dma_mask)
119 return false;
120
121 /* No device or no PCI device */
122 if (dev->bus != &pci_bus_type)
123 return false;
124
125 devid = get_device_id(dev);
126
127 /* Out of our scope? */
128 if (devid > amd_iommu_last_bdf)
129 return false;
130
131 if (amd_iommu_rlookup_table[devid] == NULL)
132 return false;
133
134 return true;
135 }
136
137 static int iommu_init_device(struct device *dev)
138 {
139 struct iommu_dev_data *dev_data;
140 struct pci_dev *pdev;
141 u16 devid, alias;
142
143 if (dev->archdata.iommu)
144 return 0;
145
146 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
147 if (!dev_data)
148 return -ENOMEM;
149
150 dev_data->dev = dev;
151
152 devid = get_device_id(dev);
153 alias = amd_iommu_alias_table[devid];
154 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
155 if (pdev)
156 dev_data->alias = &pdev->dev;
157
158 atomic_set(&dev_data->bind, 0);
159
160 dev->archdata.iommu = dev_data;
161
162
163 return 0;
164 }
165
166 static void iommu_uninit_device(struct device *dev)
167 {
168 kfree(dev->archdata.iommu);
169 }
170
171 void __init amd_iommu_uninit_devices(void)
172 {
173 struct pci_dev *pdev = NULL;
174
175 for_each_pci_dev(pdev) {
176
177 if (!check_device(&pdev->dev))
178 continue;
179
180 iommu_uninit_device(&pdev->dev);
181 }
182 }
183
184 int __init amd_iommu_init_devices(void)
185 {
186 struct pci_dev *pdev = NULL;
187 int ret = 0;
188
189 for_each_pci_dev(pdev) {
190
191 if (!check_device(&pdev->dev))
192 continue;
193
194 ret = iommu_init_device(&pdev->dev);
195 if (ret)
196 goto out_free;
197 }
198
199 return 0;
200
201 out_free:
202
203 amd_iommu_uninit_devices();
204
205 return ret;
206 }
207 #ifdef CONFIG_AMD_IOMMU_STATS
208
209 /*
210 * Initialization code for statistics collection
211 */
212
213 DECLARE_STATS_COUNTER(compl_wait);
214 DECLARE_STATS_COUNTER(cnt_map_single);
215 DECLARE_STATS_COUNTER(cnt_unmap_single);
216 DECLARE_STATS_COUNTER(cnt_map_sg);
217 DECLARE_STATS_COUNTER(cnt_unmap_sg);
218 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
219 DECLARE_STATS_COUNTER(cnt_free_coherent);
220 DECLARE_STATS_COUNTER(cross_page);
221 DECLARE_STATS_COUNTER(domain_flush_single);
222 DECLARE_STATS_COUNTER(domain_flush_all);
223 DECLARE_STATS_COUNTER(alloced_io_mem);
224 DECLARE_STATS_COUNTER(total_map_requests);
225
226 static struct dentry *stats_dir;
227 static struct dentry *de_fflush;
228
229 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
230 {
231 if (stats_dir == NULL)
232 return;
233
234 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
235 &cnt->value);
236 }
237
238 static void amd_iommu_stats_init(void)
239 {
240 stats_dir = debugfs_create_dir("amd-iommu", NULL);
241 if (stats_dir == NULL)
242 return;
243
244 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
245 (u32 *)&amd_iommu_unmap_flush);
246
247 amd_iommu_stats_add(&compl_wait);
248 amd_iommu_stats_add(&cnt_map_single);
249 amd_iommu_stats_add(&cnt_unmap_single);
250 amd_iommu_stats_add(&cnt_map_sg);
251 amd_iommu_stats_add(&cnt_unmap_sg);
252 amd_iommu_stats_add(&cnt_alloc_coherent);
253 amd_iommu_stats_add(&cnt_free_coherent);
254 amd_iommu_stats_add(&cross_page);
255 amd_iommu_stats_add(&domain_flush_single);
256 amd_iommu_stats_add(&domain_flush_all);
257 amd_iommu_stats_add(&alloced_io_mem);
258 amd_iommu_stats_add(&total_map_requests);
259 }
260
261 #endif
262
263 /****************************************************************************
264 *
265 * Interrupt handling functions
266 *
267 ****************************************************************************/
268
269 static void dump_dte_entry(u16 devid)
270 {
271 int i;
272
273 for (i = 0; i < 8; ++i)
274 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
275 amd_iommu_dev_table[devid].data[i]);
276 }
277
278 static void dump_command(unsigned long phys_addr)
279 {
280 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
281 int i;
282
283 for (i = 0; i < 4; ++i)
284 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
285 }
286
287 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
288 {
289 u32 *event = __evt;
290 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
291 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
292 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
293 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
294 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
295
296 printk(KERN_ERR "AMD-Vi: Event logged [");
297
298 switch (type) {
299 case EVENT_TYPE_ILL_DEV:
300 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
301 "address=0x%016llx flags=0x%04x]\n",
302 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
303 address, flags);
304 dump_dte_entry(devid);
305 break;
306 case EVENT_TYPE_IO_FAULT:
307 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
308 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
309 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
310 domid, address, flags);
311 break;
312 case EVENT_TYPE_DEV_TAB_ERR:
313 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
314 "address=0x%016llx flags=0x%04x]\n",
315 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
316 address, flags);
317 break;
318 case EVENT_TYPE_PAGE_TAB_ERR:
319 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
320 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
321 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
322 domid, address, flags);
323 break;
324 case EVENT_TYPE_ILL_CMD:
325 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
326 dump_command(address);
327 break;
328 case EVENT_TYPE_CMD_HARD_ERR:
329 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
330 "flags=0x%04x]\n", address, flags);
331 break;
332 case EVENT_TYPE_IOTLB_INV_TO:
333 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
334 "address=0x%016llx]\n",
335 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
336 address);
337 break;
338 case EVENT_TYPE_INV_DEV_REQ:
339 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
340 "address=0x%016llx flags=0x%04x]\n",
341 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
342 address, flags);
343 break;
344 default:
345 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
346 }
347 }
348
349 static void iommu_poll_events(struct amd_iommu *iommu)
350 {
351 u32 head, tail;
352 unsigned long flags;
353
354 spin_lock_irqsave(&iommu->lock, flags);
355
356 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
357 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
358
359 while (head != tail) {
360 iommu_print_event(iommu, iommu->evt_buf + head);
361 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
362 }
363
364 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
365
366 spin_unlock_irqrestore(&iommu->lock, flags);
367 }
368
369 irqreturn_t amd_iommu_int_handler(int irq, void *data)
370 {
371 struct amd_iommu *iommu;
372
373 for_each_iommu(iommu)
374 iommu_poll_events(iommu);
375
376 return IRQ_HANDLED;
377 }
378
379 /****************************************************************************
380 *
381 * IOMMU command queuing functions
382 *
383 ****************************************************************************/
384
385 static int wait_on_sem(volatile u64 *sem)
386 {
387 int i = 0;
388
389 while (*sem == 0 && i < LOOP_TIMEOUT) {
390 udelay(1);
391 i += 1;
392 }
393
394 if (i == LOOP_TIMEOUT) {
395 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
396 return -EIO;
397 }
398
399 return 0;
400 }
401
402 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
403 struct iommu_cmd *cmd,
404 u32 tail)
405 {
406 u8 *target;
407
408 target = iommu->cmd_buf + tail;
409 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
410
411 /* Copy command to buffer */
412 memcpy(target, cmd, sizeof(*cmd));
413
414 /* Tell the IOMMU about it */
415 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
416 }
417
418 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
419 {
420 WARN_ON(address & 0x7ULL);
421
422 memset(cmd, 0, sizeof(*cmd));
423 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
424 cmd->data[1] = upper_32_bits(__pa(address));
425 cmd->data[2] = 1;
426 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
427 }
428
429 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
430 {
431 memset(cmd, 0, sizeof(*cmd));
432 cmd->data[0] = devid;
433 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
434 }
435
436 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
437 size_t size, u16 domid, int pde)
438 {
439 u64 pages;
440 int s;
441
442 pages = iommu_num_pages(address, size, PAGE_SIZE);
443 s = 0;
444
445 if (pages > 1) {
446 /*
447 * If we have to flush more than one page, flush all
448 * TLB entries for this domain
449 */
450 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
451 s = 1;
452 }
453
454 address &= PAGE_MASK;
455
456 memset(cmd, 0, sizeof(*cmd));
457 cmd->data[1] |= domid;
458 cmd->data[2] = lower_32_bits(address);
459 cmd->data[3] = upper_32_bits(address);
460 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
461 if (s) /* size bit - we flush more than one 4kb page */
462 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
463 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
464 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
465 }
466
467 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
468 u64 address, size_t size)
469 {
470 u64 pages;
471 int s;
472
473 pages = iommu_num_pages(address, size, PAGE_SIZE);
474 s = 0;
475
476 if (pages > 1) {
477 /*
478 * If we have to flush more than one page, flush all
479 * TLB entries for this domain
480 */
481 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
482 s = 1;
483 }
484
485 address &= PAGE_MASK;
486
487 memset(cmd, 0, sizeof(*cmd));
488 cmd->data[0] = devid;
489 cmd->data[0] |= (qdep & 0xff) << 24;
490 cmd->data[1] = devid;
491 cmd->data[2] = lower_32_bits(address);
492 cmd->data[3] = upper_32_bits(address);
493 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
494 if (s)
495 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
496 }
497
498 static void build_inv_all(struct iommu_cmd *cmd)
499 {
500 memset(cmd, 0, sizeof(*cmd));
501 CMD_SET_TYPE(cmd, CMD_INV_ALL);
502 }
503
504 /*
505 * Writes the command to the IOMMUs command buffer and informs the
506 * hardware about the new command.
507 */
508 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
509 {
510 u32 left, tail, head, next_tail;
511 unsigned long flags;
512
513 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
514
515 again:
516 spin_lock_irqsave(&iommu->lock, flags);
517
518 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
519 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
520 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
521 left = (head - next_tail) % iommu->cmd_buf_size;
522
523 if (left <= 2) {
524 struct iommu_cmd sync_cmd;
525 volatile u64 sem = 0;
526 int ret;
527
528 build_completion_wait(&sync_cmd, (u64)&sem);
529 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
530
531 spin_unlock_irqrestore(&iommu->lock, flags);
532
533 if ((ret = wait_on_sem(&sem)) != 0)
534 return ret;
535
536 goto again;
537 }
538
539 copy_cmd_to_buffer(iommu, cmd, tail);
540
541 /* We need to sync now to make sure all commands are processed */
542 iommu->need_sync = true;
543
544 spin_unlock_irqrestore(&iommu->lock, flags);
545
546 return 0;
547 }
548
549 /*
550 * This function queues a completion wait command into the command
551 * buffer of an IOMMU
552 */
553 static int iommu_completion_wait(struct amd_iommu *iommu)
554 {
555 struct iommu_cmd cmd;
556 volatile u64 sem = 0;
557 int ret;
558
559 if (!iommu->need_sync)
560 return 0;
561
562 build_completion_wait(&cmd, (u64)&sem);
563
564 ret = iommu_queue_command(iommu, &cmd);
565 if (ret)
566 return ret;
567
568 return wait_on_sem(&sem);
569 }
570
571 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
572 {
573 struct iommu_cmd cmd;
574
575 build_inv_dte(&cmd, devid);
576
577 return iommu_queue_command(iommu, &cmd);
578 }
579
580 static void iommu_flush_dte_all(struct amd_iommu *iommu)
581 {
582 u32 devid;
583
584 for (devid = 0; devid <= 0xffff; ++devid)
585 iommu_flush_dte(iommu, devid);
586
587 iommu_completion_wait(iommu);
588 }
589
590 /*
591 * This function uses heavy locking and may disable irqs for some time. But
592 * this is no issue because it is only called during resume.
593 */
594 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
595 {
596 u32 dom_id;
597
598 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
599 struct iommu_cmd cmd;
600 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
601 dom_id, 1);
602 iommu_queue_command(iommu, &cmd);
603 }
604
605 iommu_completion_wait(iommu);
606 }
607
608 static void iommu_flush_all(struct amd_iommu *iommu)
609 {
610 struct iommu_cmd cmd;
611
612 build_inv_all(&cmd);
613
614 iommu_queue_command(iommu, &cmd);
615 iommu_completion_wait(iommu);
616 }
617
618 void iommu_flush_all_caches(struct amd_iommu *iommu)
619 {
620 if (iommu_feature(iommu, FEATURE_IA)) {
621 iommu_flush_all(iommu);
622 } else {
623 iommu_flush_dte_all(iommu);
624 iommu_flush_tlb_all(iommu);
625 }
626 }
627
628 /*
629 * Command send function for flushing on-device TLB
630 */
631 static int device_flush_iotlb(struct device *dev, u64 address, size_t size)
632 {
633 struct pci_dev *pdev = to_pci_dev(dev);
634 struct amd_iommu *iommu;
635 struct iommu_cmd cmd;
636 u16 devid;
637 int qdep;
638
639 qdep = pci_ats_queue_depth(pdev);
640 devid = get_device_id(dev);
641 iommu = amd_iommu_rlookup_table[devid];
642
643 build_inv_iotlb_pages(&cmd, devid, qdep, address, size);
644
645 return iommu_queue_command(iommu, &cmd);
646 }
647
648 /*
649 * Command send function for invalidating a device table entry
650 */
651 static int device_flush_dte(struct device *dev)
652 {
653 struct amd_iommu *iommu;
654 struct pci_dev *pdev;
655 u16 devid;
656 int ret;
657
658 pdev = to_pci_dev(dev);
659 devid = get_device_id(dev);
660 iommu = amd_iommu_rlookup_table[devid];
661
662 ret = iommu_flush_dte(iommu, devid);
663 if (ret)
664 return ret;
665
666 if (pci_ats_enabled(pdev))
667 ret = device_flush_iotlb(dev, 0, ~0UL);
668
669 return ret;
670 }
671
672 /*
673 * TLB invalidation function which is called from the mapping functions.
674 * It invalidates a single PTE if the range to flush is within a single
675 * page. Otherwise it flushes the whole TLB of the IOMMU.
676 */
677 static void __domain_flush_pages(struct protection_domain *domain,
678 u64 address, size_t size, int pde)
679 {
680 struct iommu_dev_data *dev_data;
681 struct iommu_cmd cmd;
682 int ret = 0, i;
683
684 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
685
686 for (i = 0; i < amd_iommus_present; ++i) {
687 if (!domain->dev_iommu[i])
688 continue;
689
690 /*
691 * Devices of this domain are behind this IOMMU
692 * We need a TLB flush
693 */
694 ret |= iommu_queue_command(amd_iommus[i], &cmd);
695 }
696
697 list_for_each_entry(dev_data, &domain->dev_list, list) {
698 struct pci_dev *pdev = to_pci_dev(dev_data->dev);
699
700 if (!pci_ats_enabled(pdev))
701 continue;
702
703 ret |= device_flush_iotlb(dev_data->dev, address, size);
704 }
705
706 WARN_ON(ret);
707 }
708
709 static void domain_flush_pages(struct protection_domain *domain,
710 u64 address, size_t size)
711 {
712 __domain_flush_pages(domain, address, size, 0);
713 }
714
715 /* Flush the whole IO/TLB for a given protection domain */
716 static void domain_flush_tlb(struct protection_domain *domain)
717 {
718 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
719 }
720
721 /* Flush the whole IO/TLB for a given protection domain - including PDE */
722 static void domain_flush_tlb_pde(struct protection_domain *domain)
723 {
724 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
725 }
726
727 static void domain_flush_complete(struct protection_domain *domain)
728 {
729 int i;
730
731 for (i = 0; i < amd_iommus_present; ++i) {
732 if (!domain->dev_iommu[i])
733 continue;
734
735 /*
736 * Devices of this domain are behind this IOMMU
737 * We need to wait for completion of all commands.
738 */
739 iommu_completion_wait(amd_iommus[i]);
740 }
741 }
742
743
744 /*
745 * This function flushes the DTEs for all devices in domain
746 */
747 static void domain_flush_devices(struct protection_domain *domain)
748 {
749 struct iommu_dev_data *dev_data;
750 unsigned long flags;
751
752 spin_lock_irqsave(&domain->lock, flags);
753
754 list_for_each_entry(dev_data, &domain->dev_list, list)
755 device_flush_dte(dev_data->dev);
756
757 spin_unlock_irqrestore(&domain->lock, flags);
758 }
759
760 /****************************************************************************
761 *
762 * The functions below are used the create the page table mappings for
763 * unity mapped regions.
764 *
765 ****************************************************************************/
766
767 /*
768 * This function is used to add another level to an IO page table. Adding
769 * another level increases the size of the address space by 9 bits to a size up
770 * to 64 bits.
771 */
772 static bool increase_address_space(struct protection_domain *domain,
773 gfp_t gfp)
774 {
775 u64 *pte;
776
777 if (domain->mode == PAGE_MODE_6_LEVEL)
778 /* address space already 64 bit large */
779 return false;
780
781 pte = (void *)get_zeroed_page(gfp);
782 if (!pte)
783 return false;
784
785 *pte = PM_LEVEL_PDE(domain->mode,
786 virt_to_phys(domain->pt_root));
787 domain->pt_root = pte;
788 domain->mode += 1;
789 domain->updated = true;
790
791 return true;
792 }
793
794 static u64 *alloc_pte(struct protection_domain *domain,
795 unsigned long address,
796 unsigned long page_size,
797 u64 **pte_page,
798 gfp_t gfp)
799 {
800 int level, end_lvl;
801 u64 *pte, *page;
802
803 BUG_ON(!is_power_of_2(page_size));
804
805 while (address > PM_LEVEL_SIZE(domain->mode))
806 increase_address_space(domain, gfp);
807
808 level = domain->mode - 1;
809 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
810 address = PAGE_SIZE_ALIGN(address, page_size);
811 end_lvl = PAGE_SIZE_LEVEL(page_size);
812
813 while (level > end_lvl) {
814 if (!IOMMU_PTE_PRESENT(*pte)) {
815 page = (u64 *)get_zeroed_page(gfp);
816 if (!page)
817 return NULL;
818 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
819 }
820
821 /* No level skipping support yet */
822 if (PM_PTE_LEVEL(*pte) != level)
823 return NULL;
824
825 level -= 1;
826
827 pte = IOMMU_PTE_PAGE(*pte);
828
829 if (pte_page && level == end_lvl)
830 *pte_page = pte;
831
832 pte = &pte[PM_LEVEL_INDEX(level, address)];
833 }
834
835 return pte;
836 }
837
838 /*
839 * This function checks if there is a PTE for a given dma address. If
840 * there is one, it returns the pointer to it.
841 */
842 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
843 {
844 int level;
845 u64 *pte;
846
847 if (address > PM_LEVEL_SIZE(domain->mode))
848 return NULL;
849
850 level = domain->mode - 1;
851 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
852
853 while (level > 0) {
854
855 /* Not Present */
856 if (!IOMMU_PTE_PRESENT(*pte))
857 return NULL;
858
859 /* Large PTE */
860 if (PM_PTE_LEVEL(*pte) == 0x07) {
861 unsigned long pte_mask, __pte;
862
863 /*
864 * If we have a series of large PTEs, make
865 * sure to return a pointer to the first one.
866 */
867 pte_mask = PTE_PAGE_SIZE(*pte);
868 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
869 __pte = ((unsigned long)pte) & pte_mask;
870
871 return (u64 *)__pte;
872 }
873
874 /* No level skipping support yet */
875 if (PM_PTE_LEVEL(*pte) != level)
876 return NULL;
877
878 level -= 1;
879
880 /* Walk to the next level */
881 pte = IOMMU_PTE_PAGE(*pte);
882 pte = &pte[PM_LEVEL_INDEX(level, address)];
883 }
884
885 return pte;
886 }
887
888 /*
889 * Generic mapping functions. It maps a physical address into a DMA
890 * address space. It allocates the page table pages if necessary.
891 * In the future it can be extended to a generic mapping function
892 * supporting all features of AMD IOMMU page tables like level skipping
893 * and full 64 bit address spaces.
894 */
895 static int iommu_map_page(struct protection_domain *dom,
896 unsigned long bus_addr,
897 unsigned long phys_addr,
898 int prot,
899 unsigned long page_size)
900 {
901 u64 __pte, *pte;
902 int i, count;
903
904 if (!(prot & IOMMU_PROT_MASK))
905 return -EINVAL;
906
907 bus_addr = PAGE_ALIGN(bus_addr);
908 phys_addr = PAGE_ALIGN(phys_addr);
909 count = PAGE_SIZE_PTE_COUNT(page_size);
910 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
911
912 for (i = 0; i < count; ++i)
913 if (IOMMU_PTE_PRESENT(pte[i]))
914 return -EBUSY;
915
916 if (page_size > PAGE_SIZE) {
917 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
918 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
919 } else
920 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
921
922 if (prot & IOMMU_PROT_IR)
923 __pte |= IOMMU_PTE_IR;
924 if (prot & IOMMU_PROT_IW)
925 __pte |= IOMMU_PTE_IW;
926
927 for (i = 0; i < count; ++i)
928 pte[i] = __pte;
929
930 update_domain(dom);
931
932 return 0;
933 }
934
935 static unsigned long iommu_unmap_page(struct protection_domain *dom,
936 unsigned long bus_addr,
937 unsigned long page_size)
938 {
939 unsigned long long unmap_size, unmapped;
940 u64 *pte;
941
942 BUG_ON(!is_power_of_2(page_size));
943
944 unmapped = 0;
945
946 while (unmapped < page_size) {
947
948 pte = fetch_pte(dom, bus_addr);
949
950 if (!pte) {
951 /*
952 * No PTE for this address
953 * move forward in 4kb steps
954 */
955 unmap_size = PAGE_SIZE;
956 } else if (PM_PTE_LEVEL(*pte) == 0) {
957 /* 4kb PTE found for this address */
958 unmap_size = PAGE_SIZE;
959 *pte = 0ULL;
960 } else {
961 int count, i;
962
963 /* Large PTE found which maps this address */
964 unmap_size = PTE_PAGE_SIZE(*pte);
965 count = PAGE_SIZE_PTE_COUNT(unmap_size);
966 for (i = 0; i < count; i++)
967 pte[i] = 0ULL;
968 }
969
970 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
971 unmapped += unmap_size;
972 }
973
974 BUG_ON(!is_power_of_2(unmapped));
975
976 return unmapped;
977 }
978
979 /*
980 * This function checks if a specific unity mapping entry is needed for
981 * this specific IOMMU.
982 */
983 static int iommu_for_unity_map(struct amd_iommu *iommu,
984 struct unity_map_entry *entry)
985 {
986 u16 bdf, i;
987
988 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
989 bdf = amd_iommu_alias_table[i];
990 if (amd_iommu_rlookup_table[bdf] == iommu)
991 return 1;
992 }
993
994 return 0;
995 }
996
997 /*
998 * This function actually applies the mapping to the page table of the
999 * dma_ops domain.
1000 */
1001 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1002 struct unity_map_entry *e)
1003 {
1004 u64 addr;
1005 int ret;
1006
1007 for (addr = e->address_start; addr < e->address_end;
1008 addr += PAGE_SIZE) {
1009 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1010 PAGE_SIZE);
1011 if (ret)
1012 return ret;
1013 /*
1014 * if unity mapping is in aperture range mark the page
1015 * as allocated in the aperture
1016 */
1017 if (addr < dma_dom->aperture_size)
1018 __set_bit(addr >> PAGE_SHIFT,
1019 dma_dom->aperture[0]->bitmap);
1020 }
1021
1022 return 0;
1023 }
1024
1025 /*
1026 * Init the unity mappings for a specific IOMMU in the system
1027 *
1028 * Basically iterates over all unity mapping entries and applies them to
1029 * the default domain DMA of that IOMMU if necessary.
1030 */
1031 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1032 {
1033 struct unity_map_entry *entry;
1034 int ret;
1035
1036 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1037 if (!iommu_for_unity_map(iommu, entry))
1038 continue;
1039 ret = dma_ops_unity_map(iommu->default_dom, entry);
1040 if (ret)
1041 return ret;
1042 }
1043
1044 return 0;
1045 }
1046
1047 /*
1048 * Inits the unity mappings required for a specific device
1049 */
1050 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1051 u16 devid)
1052 {
1053 struct unity_map_entry *e;
1054 int ret;
1055
1056 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1057 if (!(devid >= e->devid_start && devid <= e->devid_end))
1058 continue;
1059 ret = dma_ops_unity_map(dma_dom, e);
1060 if (ret)
1061 return ret;
1062 }
1063
1064 return 0;
1065 }
1066
1067 /****************************************************************************
1068 *
1069 * The next functions belong to the address allocator for the dma_ops
1070 * interface functions. They work like the allocators in the other IOMMU
1071 * drivers. Its basically a bitmap which marks the allocated pages in
1072 * the aperture. Maybe it could be enhanced in the future to a more
1073 * efficient allocator.
1074 *
1075 ****************************************************************************/
1076
1077 /*
1078 * The address allocator core functions.
1079 *
1080 * called with domain->lock held
1081 */
1082
1083 /*
1084 * Used to reserve address ranges in the aperture (e.g. for exclusion
1085 * ranges.
1086 */
1087 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1088 unsigned long start_page,
1089 unsigned int pages)
1090 {
1091 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1092
1093 if (start_page + pages > last_page)
1094 pages = last_page - start_page;
1095
1096 for (i = start_page; i < start_page + pages; ++i) {
1097 int index = i / APERTURE_RANGE_PAGES;
1098 int page = i % APERTURE_RANGE_PAGES;
1099 __set_bit(page, dom->aperture[index]->bitmap);
1100 }
1101 }
1102
1103 /*
1104 * This function is used to add a new aperture range to an existing
1105 * aperture in case of dma_ops domain allocation or address allocation
1106 * failure.
1107 */
1108 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1109 bool populate, gfp_t gfp)
1110 {
1111 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1112 struct amd_iommu *iommu;
1113 unsigned long i;
1114
1115 #ifdef CONFIG_IOMMU_STRESS
1116 populate = false;
1117 #endif
1118
1119 if (index >= APERTURE_MAX_RANGES)
1120 return -ENOMEM;
1121
1122 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1123 if (!dma_dom->aperture[index])
1124 return -ENOMEM;
1125
1126 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1127 if (!dma_dom->aperture[index]->bitmap)
1128 goto out_free;
1129
1130 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1131
1132 if (populate) {
1133 unsigned long address = dma_dom->aperture_size;
1134 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1135 u64 *pte, *pte_page;
1136
1137 for (i = 0; i < num_ptes; ++i) {
1138 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1139 &pte_page, gfp);
1140 if (!pte)
1141 goto out_free;
1142
1143 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1144
1145 address += APERTURE_RANGE_SIZE / 64;
1146 }
1147 }
1148
1149 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1150
1151 /* Initialize the exclusion range if necessary */
1152 for_each_iommu(iommu) {
1153 if (iommu->exclusion_start &&
1154 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1155 && iommu->exclusion_start < dma_dom->aperture_size) {
1156 unsigned long startpage;
1157 int pages = iommu_num_pages(iommu->exclusion_start,
1158 iommu->exclusion_length,
1159 PAGE_SIZE);
1160 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1161 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1162 }
1163 }
1164
1165 /*
1166 * Check for areas already mapped as present in the new aperture
1167 * range and mark those pages as reserved in the allocator. Such
1168 * mappings may already exist as a result of requested unity
1169 * mappings for devices.
1170 */
1171 for (i = dma_dom->aperture[index]->offset;
1172 i < dma_dom->aperture_size;
1173 i += PAGE_SIZE) {
1174 u64 *pte = fetch_pte(&dma_dom->domain, i);
1175 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1176 continue;
1177
1178 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1179 }
1180
1181 update_domain(&dma_dom->domain);
1182
1183 return 0;
1184
1185 out_free:
1186 update_domain(&dma_dom->domain);
1187
1188 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1189
1190 kfree(dma_dom->aperture[index]);
1191 dma_dom->aperture[index] = NULL;
1192
1193 return -ENOMEM;
1194 }
1195
1196 static unsigned long dma_ops_area_alloc(struct device *dev,
1197 struct dma_ops_domain *dom,
1198 unsigned int pages,
1199 unsigned long align_mask,
1200 u64 dma_mask,
1201 unsigned long start)
1202 {
1203 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1204 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1205 int i = start >> APERTURE_RANGE_SHIFT;
1206 unsigned long boundary_size;
1207 unsigned long address = -1;
1208 unsigned long limit;
1209
1210 next_bit >>= PAGE_SHIFT;
1211
1212 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1213 PAGE_SIZE) >> PAGE_SHIFT;
1214
1215 for (;i < max_index; ++i) {
1216 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1217
1218 if (dom->aperture[i]->offset >= dma_mask)
1219 break;
1220
1221 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1222 dma_mask >> PAGE_SHIFT);
1223
1224 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1225 limit, next_bit, pages, 0,
1226 boundary_size, align_mask);
1227 if (address != -1) {
1228 address = dom->aperture[i]->offset +
1229 (address << PAGE_SHIFT);
1230 dom->next_address = address + (pages << PAGE_SHIFT);
1231 break;
1232 }
1233
1234 next_bit = 0;
1235 }
1236
1237 return address;
1238 }
1239
1240 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1241 struct dma_ops_domain *dom,
1242 unsigned int pages,
1243 unsigned long align_mask,
1244 u64 dma_mask)
1245 {
1246 unsigned long address;
1247
1248 #ifdef CONFIG_IOMMU_STRESS
1249 dom->next_address = 0;
1250 dom->need_flush = true;
1251 #endif
1252
1253 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1254 dma_mask, dom->next_address);
1255
1256 if (address == -1) {
1257 dom->next_address = 0;
1258 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1259 dma_mask, 0);
1260 dom->need_flush = true;
1261 }
1262
1263 if (unlikely(address == -1))
1264 address = DMA_ERROR_CODE;
1265
1266 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1267
1268 return address;
1269 }
1270
1271 /*
1272 * The address free function.
1273 *
1274 * called with domain->lock held
1275 */
1276 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1277 unsigned long address,
1278 unsigned int pages)
1279 {
1280 unsigned i = address >> APERTURE_RANGE_SHIFT;
1281 struct aperture_range *range = dom->aperture[i];
1282
1283 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1284
1285 #ifdef CONFIG_IOMMU_STRESS
1286 if (i < 4)
1287 return;
1288 #endif
1289
1290 if (address >= dom->next_address)
1291 dom->need_flush = true;
1292
1293 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1294
1295 bitmap_clear(range->bitmap, address, pages);
1296
1297 }
1298
1299 /****************************************************************************
1300 *
1301 * The next functions belong to the domain allocation. A domain is
1302 * allocated for every IOMMU as the default domain. If device isolation
1303 * is enabled, every device get its own domain. The most important thing
1304 * about domains is the page table mapping the DMA address space they
1305 * contain.
1306 *
1307 ****************************************************************************/
1308
1309 /*
1310 * This function adds a protection domain to the global protection domain list
1311 */
1312 static void add_domain_to_list(struct protection_domain *domain)
1313 {
1314 unsigned long flags;
1315
1316 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1317 list_add(&domain->list, &amd_iommu_pd_list);
1318 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1319 }
1320
1321 /*
1322 * This function removes a protection domain to the global
1323 * protection domain list
1324 */
1325 static void del_domain_from_list(struct protection_domain *domain)
1326 {
1327 unsigned long flags;
1328
1329 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1330 list_del(&domain->list);
1331 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1332 }
1333
1334 static u16 domain_id_alloc(void)
1335 {
1336 unsigned long flags;
1337 int id;
1338
1339 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1340 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1341 BUG_ON(id == 0);
1342 if (id > 0 && id < MAX_DOMAIN_ID)
1343 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1344 else
1345 id = 0;
1346 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1347
1348 return id;
1349 }
1350
1351 static void domain_id_free(int id)
1352 {
1353 unsigned long flags;
1354
1355 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1356 if (id > 0 && id < MAX_DOMAIN_ID)
1357 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1358 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1359 }
1360
1361 static void free_pagetable(struct protection_domain *domain)
1362 {
1363 int i, j;
1364 u64 *p1, *p2, *p3;
1365
1366 p1 = domain->pt_root;
1367
1368 if (!p1)
1369 return;
1370
1371 for (i = 0; i < 512; ++i) {
1372 if (!IOMMU_PTE_PRESENT(p1[i]))
1373 continue;
1374
1375 p2 = IOMMU_PTE_PAGE(p1[i]);
1376 for (j = 0; j < 512; ++j) {
1377 if (!IOMMU_PTE_PRESENT(p2[j]))
1378 continue;
1379 p3 = IOMMU_PTE_PAGE(p2[j]);
1380 free_page((unsigned long)p3);
1381 }
1382
1383 free_page((unsigned long)p2);
1384 }
1385
1386 free_page((unsigned long)p1);
1387
1388 domain->pt_root = NULL;
1389 }
1390
1391 /*
1392 * Free a domain, only used if something went wrong in the
1393 * allocation path and we need to free an already allocated page table
1394 */
1395 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1396 {
1397 int i;
1398
1399 if (!dom)
1400 return;
1401
1402 del_domain_from_list(&dom->domain);
1403
1404 free_pagetable(&dom->domain);
1405
1406 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1407 if (!dom->aperture[i])
1408 continue;
1409 free_page((unsigned long)dom->aperture[i]->bitmap);
1410 kfree(dom->aperture[i]);
1411 }
1412
1413 kfree(dom);
1414 }
1415
1416 /*
1417 * Allocates a new protection domain usable for the dma_ops functions.
1418 * It also initializes the page table and the address allocator data
1419 * structures required for the dma_ops interface
1420 */
1421 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1422 {
1423 struct dma_ops_domain *dma_dom;
1424
1425 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1426 if (!dma_dom)
1427 return NULL;
1428
1429 spin_lock_init(&dma_dom->domain.lock);
1430
1431 dma_dom->domain.id = domain_id_alloc();
1432 if (dma_dom->domain.id == 0)
1433 goto free_dma_dom;
1434 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1435 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1436 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1437 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1438 dma_dom->domain.priv = dma_dom;
1439 if (!dma_dom->domain.pt_root)
1440 goto free_dma_dom;
1441
1442 dma_dom->need_flush = false;
1443 dma_dom->target_dev = 0xffff;
1444
1445 add_domain_to_list(&dma_dom->domain);
1446
1447 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1448 goto free_dma_dom;
1449
1450 /*
1451 * mark the first page as allocated so we never return 0 as
1452 * a valid dma-address. So we can use 0 as error value
1453 */
1454 dma_dom->aperture[0]->bitmap[0] = 1;
1455 dma_dom->next_address = 0;
1456
1457
1458 return dma_dom;
1459
1460 free_dma_dom:
1461 dma_ops_domain_free(dma_dom);
1462
1463 return NULL;
1464 }
1465
1466 /*
1467 * little helper function to check whether a given protection domain is a
1468 * dma_ops domain
1469 */
1470 static bool dma_ops_domain(struct protection_domain *domain)
1471 {
1472 return domain->flags & PD_DMA_OPS_MASK;
1473 }
1474
1475 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1476 {
1477 u64 pte_root = virt_to_phys(domain->pt_root);
1478 u32 flags = 0;
1479
1480 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1481 << DEV_ENTRY_MODE_SHIFT;
1482 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1483
1484 if (ats)
1485 flags |= DTE_FLAG_IOTLB;
1486
1487 amd_iommu_dev_table[devid].data[3] |= flags;
1488 amd_iommu_dev_table[devid].data[2] = domain->id;
1489 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1490 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1491 }
1492
1493 static void clear_dte_entry(u16 devid)
1494 {
1495 /* remove entry from the device table seen by the hardware */
1496 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1497 amd_iommu_dev_table[devid].data[1] = 0;
1498 amd_iommu_dev_table[devid].data[2] = 0;
1499
1500 amd_iommu_apply_erratum_63(devid);
1501 }
1502
1503 static void do_attach(struct device *dev, struct protection_domain *domain)
1504 {
1505 struct iommu_dev_data *dev_data;
1506 struct amd_iommu *iommu;
1507 struct pci_dev *pdev;
1508 bool ats = false;
1509 u16 devid;
1510
1511 devid = get_device_id(dev);
1512 iommu = amd_iommu_rlookup_table[devid];
1513 dev_data = get_dev_data(dev);
1514 pdev = to_pci_dev(dev);
1515
1516 if (amd_iommu_iotlb_sup)
1517 ats = pci_ats_enabled(pdev);
1518
1519 /* Update data structures */
1520 dev_data->domain = domain;
1521 list_add(&dev_data->list, &domain->dev_list);
1522 set_dte_entry(devid, domain, ats);
1523
1524 /* Do reference counting */
1525 domain->dev_iommu[iommu->index] += 1;
1526 domain->dev_cnt += 1;
1527
1528 /* Flush the DTE entry */
1529 device_flush_dte(dev);
1530 }
1531
1532 static void do_detach(struct device *dev)
1533 {
1534 struct iommu_dev_data *dev_data;
1535 struct amd_iommu *iommu;
1536 struct pci_dev *pdev;
1537 u16 devid;
1538
1539 devid = get_device_id(dev);
1540 iommu = amd_iommu_rlookup_table[devid];
1541 dev_data = get_dev_data(dev);
1542 pdev = to_pci_dev(dev);
1543
1544 /* decrease reference counters */
1545 dev_data->domain->dev_iommu[iommu->index] -= 1;
1546 dev_data->domain->dev_cnt -= 1;
1547
1548 /* Update data structures */
1549 dev_data->domain = NULL;
1550 list_del(&dev_data->list);
1551 clear_dte_entry(devid);
1552
1553 /* Flush the DTE entry */
1554 device_flush_dte(dev);
1555 }
1556
1557 /*
1558 * If a device is not yet associated with a domain, this function does
1559 * assigns it visible for the hardware
1560 */
1561 static int __attach_device(struct device *dev,
1562 struct protection_domain *domain)
1563 {
1564 struct iommu_dev_data *dev_data, *alias_data;
1565 int ret;
1566
1567 dev_data = get_dev_data(dev);
1568 alias_data = get_dev_data(dev_data->alias);
1569
1570 if (!alias_data)
1571 return -EINVAL;
1572
1573 /* lock domain */
1574 spin_lock(&domain->lock);
1575
1576 /* Some sanity checks */
1577 ret = -EBUSY;
1578 if (alias_data->domain != NULL &&
1579 alias_data->domain != domain)
1580 goto out_unlock;
1581
1582 if (dev_data->domain != NULL &&
1583 dev_data->domain != domain)
1584 goto out_unlock;
1585
1586 /* Do real assignment */
1587 if (dev_data->alias != dev) {
1588 alias_data = get_dev_data(dev_data->alias);
1589 if (alias_data->domain == NULL)
1590 do_attach(dev_data->alias, domain);
1591
1592 atomic_inc(&alias_data->bind);
1593 }
1594
1595 if (dev_data->domain == NULL)
1596 do_attach(dev, domain);
1597
1598 atomic_inc(&dev_data->bind);
1599
1600 ret = 0;
1601
1602 out_unlock:
1603
1604 /* ready */
1605 spin_unlock(&domain->lock);
1606
1607 return ret;
1608 }
1609
1610 /*
1611 * If a device is not yet associated with a domain, this function does
1612 * assigns it visible for the hardware
1613 */
1614 static int attach_device(struct device *dev,
1615 struct protection_domain *domain)
1616 {
1617 struct pci_dev *pdev = to_pci_dev(dev);
1618 unsigned long flags;
1619 int ret;
1620
1621 if (amd_iommu_iotlb_sup)
1622 pci_enable_ats(pdev, PAGE_SHIFT);
1623
1624 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1625 ret = __attach_device(dev, domain);
1626 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1627
1628 /*
1629 * We might boot into a crash-kernel here. The crashed kernel
1630 * left the caches in the IOMMU dirty. So we have to flush
1631 * here to evict all dirty stuff.
1632 */
1633 domain_flush_tlb_pde(domain);
1634
1635 return ret;
1636 }
1637
1638 /*
1639 * Removes a device from a protection domain (unlocked)
1640 */
1641 static void __detach_device(struct device *dev)
1642 {
1643 struct iommu_dev_data *dev_data = get_dev_data(dev);
1644 struct iommu_dev_data *alias_data;
1645 struct protection_domain *domain;
1646 unsigned long flags;
1647
1648 BUG_ON(!dev_data->domain);
1649
1650 domain = dev_data->domain;
1651
1652 spin_lock_irqsave(&domain->lock, flags);
1653
1654 if (dev_data->alias != dev) {
1655 alias_data = get_dev_data(dev_data->alias);
1656 if (atomic_dec_and_test(&alias_data->bind))
1657 do_detach(dev_data->alias);
1658 }
1659
1660 if (atomic_dec_and_test(&dev_data->bind))
1661 do_detach(dev);
1662
1663 spin_unlock_irqrestore(&domain->lock, flags);
1664
1665 /*
1666 * If we run in passthrough mode the device must be assigned to the
1667 * passthrough domain if it is detached from any other domain.
1668 * Make sure we can deassign from the pt_domain itself.
1669 */
1670 if (iommu_pass_through &&
1671 (dev_data->domain == NULL && domain != pt_domain))
1672 __attach_device(dev, pt_domain);
1673 }
1674
1675 /*
1676 * Removes a device from a protection domain (with devtable_lock held)
1677 */
1678 static void detach_device(struct device *dev)
1679 {
1680 struct pci_dev *pdev = to_pci_dev(dev);
1681 unsigned long flags;
1682
1683 /* lock device table */
1684 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1685 __detach_device(dev);
1686 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1687
1688 if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev))
1689 pci_disable_ats(pdev);
1690 }
1691
1692 /*
1693 * Find out the protection domain structure for a given PCI device. This
1694 * will give us the pointer to the page table root for example.
1695 */
1696 static struct protection_domain *domain_for_device(struct device *dev)
1697 {
1698 struct protection_domain *dom;
1699 struct iommu_dev_data *dev_data, *alias_data;
1700 unsigned long flags;
1701 u16 devid, alias;
1702
1703 devid = get_device_id(dev);
1704 alias = amd_iommu_alias_table[devid];
1705 dev_data = get_dev_data(dev);
1706 alias_data = get_dev_data(dev_data->alias);
1707 if (!alias_data)
1708 return NULL;
1709
1710 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1711 dom = dev_data->domain;
1712 if (dom == NULL &&
1713 alias_data->domain != NULL) {
1714 __attach_device(dev, alias_data->domain);
1715 dom = alias_data->domain;
1716 }
1717
1718 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1719
1720 return dom;
1721 }
1722
1723 static int device_change_notifier(struct notifier_block *nb,
1724 unsigned long action, void *data)
1725 {
1726 struct device *dev = data;
1727 u16 devid;
1728 struct protection_domain *domain;
1729 struct dma_ops_domain *dma_domain;
1730 struct amd_iommu *iommu;
1731 unsigned long flags;
1732
1733 if (!check_device(dev))
1734 return 0;
1735
1736 devid = get_device_id(dev);
1737 iommu = amd_iommu_rlookup_table[devid];
1738
1739 switch (action) {
1740 case BUS_NOTIFY_UNBOUND_DRIVER:
1741
1742 domain = domain_for_device(dev);
1743
1744 if (!domain)
1745 goto out;
1746 if (iommu_pass_through)
1747 break;
1748 detach_device(dev);
1749 break;
1750 case BUS_NOTIFY_ADD_DEVICE:
1751
1752 iommu_init_device(dev);
1753
1754 domain = domain_for_device(dev);
1755
1756 /* allocate a protection domain if a device is added */
1757 dma_domain = find_protection_domain(devid);
1758 if (dma_domain)
1759 goto out;
1760 dma_domain = dma_ops_domain_alloc();
1761 if (!dma_domain)
1762 goto out;
1763 dma_domain->target_dev = devid;
1764
1765 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1766 list_add_tail(&dma_domain->list, &iommu_pd_list);
1767 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1768
1769 break;
1770 case BUS_NOTIFY_DEL_DEVICE:
1771
1772 iommu_uninit_device(dev);
1773
1774 default:
1775 goto out;
1776 }
1777
1778 device_flush_dte(dev);
1779 iommu_completion_wait(iommu);
1780
1781 out:
1782 return 0;
1783 }
1784
1785 static struct notifier_block device_nb = {
1786 .notifier_call = device_change_notifier,
1787 };
1788
1789 void amd_iommu_init_notifier(void)
1790 {
1791 bus_register_notifier(&pci_bus_type, &device_nb);
1792 }
1793
1794 /*****************************************************************************
1795 *
1796 * The next functions belong to the dma_ops mapping/unmapping code.
1797 *
1798 *****************************************************************************/
1799
1800 /*
1801 * In the dma_ops path we only have the struct device. This function
1802 * finds the corresponding IOMMU, the protection domain and the
1803 * requestor id for a given device.
1804 * If the device is not yet associated with a domain this is also done
1805 * in this function.
1806 */
1807 static struct protection_domain *get_domain(struct device *dev)
1808 {
1809 struct protection_domain *domain;
1810 struct dma_ops_domain *dma_dom;
1811 u16 devid = get_device_id(dev);
1812
1813 if (!check_device(dev))
1814 return ERR_PTR(-EINVAL);
1815
1816 domain = domain_for_device(dev);
1817 if (domain != NULL && !dma_ops_domain(domain))
1818 return ERR_PTR(-EBUSY);
1819
1820 if (domain != NULL)
1821 return domain;
1822
1823 /* Device not bount yet - bind it */
1824 dma_dom = find_protection_domain(devid);
1825 if (!dma_dom)
1826 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1827 attach_device(dev, &dma_dom->domain);
1828 DUMP_printk("Using protection domain %d for device %s\n",
1829 dma_dom->domain.id, dev_name(dev));
1830
1831 return &dma_dom->domain;
1832 }
1833
1834 static void update_device_table(struct protection_domain *domain)
1835 {
1836 struct iommu_dev_data *dev_data;
1837
1838 list_for_each_entry(dev_data, &domain->dev_list, list) {
1839 struct pci_dev *pdev = to_pci_dev(dev_data->dev);
1840 u16 devid = get_device_id(dev_data->dev);
1841 set_dte_entry(devid, domain, pci_ats_enabled(pdev));
1842 }
1843 }
1844
1845 static void update_domain(struct protection_domain *domain)
1846 {
1847 if (!domain->updated)
1848 return;
1849
1850 update_device_table(domain);
1851
1852 domain_flush_devices(domain);
1853 domain_flush_tlb_pde(domain);
1854
1855 domain->updated = false;
1856 }
1857
1858 /*
1859 * This function fetches the PTE for a given address in the aperture
1860 */
1861 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1862 unsigned long address)
1863 {
1864 struct aperture_range *aperture;
1865 u64 *pte, *pte_page;
1866
1867 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1868 if (!aperture)
1869 return NULL;
1870
1871 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1872 if (!pte) {
1873 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1874 GFP_ATOMIC);
1875 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1876 } else
1877 pte += PM_LEVEL_INDEX(0, address);
1878
1879 update_domain(&dom->domain);
1880
1881 return pte;
1882 }
1883
1884 /*
1885 * This is the generic map function. It maps one 4kb page at paddr to
1886 * the given address in the DMA address space for the domain.
1887 */
1888 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1889 unsigned long address,
1890 phys_addr_t paddr,
1891 int direction)
1892 {
1893 u64 *pte, __pte;
1894
1895 WARN_ON(address > dom->aperture_size);
1896
1897 paddr &= PAGE_MASK;
1898
1899 pte = dma_ops_get_pte(dom, address);
1900 if (!pte)
1901 return DMA_ERROR_CODE;
1902
1903 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1904
1905 if (direction == DMA_TO_DEVICE)
1906 __pte |= IOMMU_PTE_IR;
1907 else if (direction == DMA_FROM_DEVICE)
1908 __pte |= IOMMU_PTE_IW;
1909 else if (direction == DMA_BIDIRECTIONAL)
1910 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1911
1912 WARN_ON(*pte);
1913
1914 *pte = __pte;
1915
1916 return (dma_addr_t)address;
1917 }
1918
1919 /*
1920 * The generic unmapping function for on page in the DMA address space.
1921 */
1922 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1923 unsigned long address)
1924 {
1925 struct aperture_range *aperture;
1926 u64 *pte;
1927
1928 if (address >= dom->aperture_size)
1929 return;
1930
1931 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1932 if (!aperture)
1933 return;
1934
1935 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1936 if (!pte)
1937 return;
1938
1939 pte += PM_LEVEL_INDEX(0, address);
1940
1941 WARN_ON(!*pte);
1942
1943 *pte = 0ULL;
1944 }
1945
1946 /*
1947 * This function contains common code for mapping of a physically
1948 * contiguous memory region into DMA address space. It is used by all
1949 * mapping functions provided with this IOMMU driver.
1950 * Must be called with the domain lock held.
1951 */
1952 static dma_addr_t __map_single(struct device *dev,
1953 struct dma_ops_domain *dma_dom,
1954 phys_addr_t paddr,
1955 size_t size,
1956 int dir,
1957 bool align,
1958 u64 dma_mask)
1959 {
1960 dma_addr_t offset = paddr & ~PAGE_MASK;
1961 dma_addr_t address, start, ret;
1962 unsigned int pages;
1963 unsigned long align_mask = 0;
1964 int i;
1965
1966 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1967 paddr &= PAGE_MASK;
1968
1969 INC_STATS_COUNTER(total_map_requests);
1970
1971 if (pages > 1)
1972 INC_STATS_COUNTER(cross_page);
1973
1974 if (align)
1975 align_mask = (1UL << get_order(size)) - 1;
1976
1977 retry:
1978 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1979 dma_mask);
1980 if (unlikely(address == DMA_ERROR_CODE)) {
1981 /*
1982 * setting next_address here will let the address
1983 * allocator only scan the new allocated range in the
1984 * first run. This is a small optimization.
1985 */
1986 dma_dom->next_address = dma_dom->aperture_size;
1987
1988 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1989 goto out;
1990
1991 /*
1992 * aperture was successfully enlarged by 128 MB, try
1993 * allocation again
1994 */
1995 goto retry;
1996 }
1997
1998 start = address;
1999 for (i = 0; i < pages; ++i) {
2000 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2001 if (ret == DMA_ERROR_CODE)
2002 goto out_unmap;
2003
2004 paddr += PAGE_SIZE;
2005 start += PAGE_SIZE;
2006 }
2007 address += offset;
2008
2009 ADD_STATS_COUNTER(alloced_io_mem, size);
2010
2011 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2012 domain_flush_tlb(&dma_dom->domain);
2013 dma_dom->need_flush = false;
2014 } else if (unlikely(amd_iommu_np_cache))
2015 domain_flush_pages(&dma_dom->domain, address, size);
2016
2017 out:
2018 return address;
2019
2020 out_unmap:
2021
2022 for (--i; i >= 0; --i) {
2023 start -= PAGE_SIZE;
2024 dma_ops_domain_unmap(dma_dom, start);
2025 }
2026
2027 dma_ops_free_addresses(dma_dom, address, pages);
2028
2029 return DMA_ERROR_CODE;
2030 }
2031
2032 /*
2033 * Does the reverse of the __map_single function. Must be called with
2034 * the domain lock held too
2035 */
2036 static void __unmap_single(struct dma_ops_domain *dma_dom,
2037 dma_addr_t dma_addr,
2038 size_t size,
2039 int dir)
2040 {
2041 dma_addr_t flush_addr;
2042 dma_addr_t i, start;
2043 unsigned int pages;
2044
2045 if ((dma_addr == DMA_ERROR_CODE) ||
2046 (dma_addr + size > dma_dom->aperture_size))
2047 return;
2048
2049 flush_addr = dma_addr;
2050 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2051 dma_addr &= PAGE_MASK;
2052 start = dma_addr;
2053
2054 for (i = 0; i < pages; ++i) {
2055 dma_ops_domain_unmap(dma_dom, start);
2056 start += PAGE_SIZE;
2057 }
2058
2059 SUB_STATS_COUNTER(alloced_io_mem, size);
2060
2061 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2062
2063 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2064 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2065 dma_dom->need_flush = false;
2066 }
2067 }
2068
2069 /*
2070 * The exported map_single function for dma_ops.
2071 */
2072 static dma_addr_t map_page(struct device *dev, struct page *page,
2073 unsigned long offset, size_t size,
2074 enum dma_data_direction dir,
2075 struct dma_attrs *attrs)
2076 {
2077 unsigned long flags;
2078 struct protection_domain *domain;
2079 dma_addr_t addr;
2080 u64 dma_mask;
2081 phys_addr_t paddr = page_to_phys(page) + offset;
2082
2083 INC_STATS_COUNTER(cnt_map_single);
2084
2085 domain = get_domain(dev);
2086 if (PTR_ERR(domain) == -EINVAL)
2087 return (dma_addr_t)paddr;
2088 else if (IS_ERR(domain))
2089 return DMA_ERROR_CODE;
2090
2091 dma_mask = *dev->dma_mask;
2092
2093 spin_lock_irqsave(&domain->lock, flags);
2094
2095 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2096 dma_mask);
2097 if (addr == DMA_ERROR_CODE)
2098 goto out;
2099
2100 domain_flush_complete(domain);
2101
2102 out:
2103 spin_unlock_irqrestore(&domain->lock, flags);
2104
2105 return addr;
2106 }
2107
2108 /*
2109 * The exported unmap_single function for dma_ops.
2110 */
2111 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2112 enum dma_data_direction dir, struct dma_attrs *attrs)
2113 {
2114 unsigned long flags;
2115 struct protection_domain *domain;
2116
2117 INC_STATS_COUNTER(cnt_unmap_single);
2118
2119 domain = get_domain(dev);
2120 if (IS_ERR(domain))
2121 return;
2122
2123 spin_lock_irqsave(&domain->lock, flags);
2124
2125 __unmap_single(domain->priv, dma_addr, size, dir);
2126
2127 domain_flush_complete(domain);
2128
2129 spin_unlock_irqrestore(&domain->lock, flags);
2130 }
2131
2132 /*
2133 * This is a special map_sg function which is used if we should map a
2134 * device which is not handled by an AMD IOMMU in the system.
2135 */
2136 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2137 int nelems, int dir)
2138 {
2139 struct scatterlist *s;
2140 int i;
2141
2142 for_each_sg(sglist, s, nelems, i) {
2143 s->dma_address = (dma_addr_t)sg_phys(s);
2144 s->dma_length = s->length;
2145 }
2146
2147 return nelems;
2148 }
2149
2150 /*
2151 * The exported map_sg function for dma_ops (handles scatter-gather
2152 * lists).
2153 */
2154 static int map_sg(struct device *dev, struct scatterlist *sglist,
2155 int nelems, enum dma_data_direction dir,
2156 struct dma_attrs *attrs)
2157 {
2158 unsigned long flags;
2159 struct protection_domain *domain;
2160 int i;
2161 struct scatterlist *s;
2162 phys_addr_t paddr;
2163 int mapped_elems = 0;
2164 u64 dma_mask;
2165
2166 INC_STATS_COUNTER(cnt_map_sg);
2167
2168 domain = get_domain(dev);
2169 if (PTR_ERR(domain) == -EINVAL)
2170 return map_sg_no_iommu(dev, sglist, nelems, dir);
2171 else if (IS_ERR(domain))
2172 return 0;
2173
2174 dma_mask = *dev->dma_mask;
2175
2176 spin_lock_irqsave(&domain->lock, flags);
2177
2178 for_each_sg(sglist, s, nelems, i) {
2179 paddr = sg_phys(s);
2180
2181 s->dma_address = __map_single(dev, domain->priv,
2182 paddr, s->length, dir, false,
2183 dma_mask);
2184
2185 if (s->dma_address) {
2186 s->dma_length = s->length;
2187 mapped_elems++;
2188 } else
2189 goto unmap;
2190 }
2191
2192 domain_flush_complete(domain);
2193
2194 out:
2195 spin_unlock_irqrestore(&domain->lock, flags);
2196
2197 return mapped_elems;
2198 unmap:
2199 for_each_sg(sglist, s, mapped_elems, i) {
2200 if (s->dma_address)
2201 __unmap_single(domain->priv, s->dma_address,
2202 s->dma_length, dir);
2203 s->dma_address = s->dma_length = 0;
2204 }
2205
2206 mapped_elems = 0;
2207
2208 goto out;
2209 }
2210
2211 /*
2212 * The exported map_sg function for dma_ops (handles scatter-gather
2213 * lists).
2214 */
2215 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2216 int nelems, enum dma_data_direction dir,
2217 struct dma_attrs *attrs)
2218 {
2219 unsigned long flags;
2220 struct protection_domain *domain;
2221 struct scatterlist *s;
2222 int i;
2223
2224 INC_STATS_COUNTER(cnt_unmap_sg);
2225
2226 domain = get_domain(dev);
2227 if (IS_ERR(domain))
2228 return;
2229
2230 spin_lock_irqsave(&domain->lock, flags);
2231
2232 for_each_sg(sglist, s, nelems, i) {
2233 __unmap_single(domain->priv, s->dma_address,
2234 s->dma_length, dir);
2235 s->dma_address = s->dma_length = 0;
2236 }
2237
2238 domain_flush_complete(domain);
2239
2240 spin_unlock_irqrestore(&domain->lock, flags);
2241 }
2242
2243 /*
2244 * The exported alloc_coherent function for dma_ops.
2245 */
2246 static void *alloc_coherent(struct device *dev, size_t size,
2247 dma_addr_t *dma_addr, gfp_t flag)
2248 {
2249 unsigned long flags;
2250 void *virt_addr;
2251 struct protection_domain *domain;
2252 phys_addr_t paddr;
2253 u64 dma_mask = dev->coherent_dma_mask;
2254
2255 INC_STATS_COUNTER(cnt_alloc_coherent);
2256
2257 domain = get_domain(dev);
2258 if (PTR_ERR(domain) == -EINVAL) {
2259 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2260 *dma_addr = __pa(virt_addr);
2261 return virt_addr;
2262 } else if (IS_ERR(domain))
2263 return NULL;
2264
2265 dma_mask = dev->coherent_dma_mask;
2266 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2267 flag |= __GFP_ZERO;
2268
2269 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2270 if (!virt_addr)
2271 return NULL;
2272
2273 paddr = virt_to_phys(virt_addr);
2274
2275 if (!dma_mask)
2276 dma_mask = *dev->dma_mask;
2277
2278 spin_lock_irqsave(&domain->lock, flags);
2279
2280 *dma_addr = __map_single(dev, domain->priv, paddr,
2281 size, DMA_BIDIRECTIONAL, true, dma_mask);
2282
2283 if (*dma_addr == DMA_ERROR_CODE) {
2284 spin_unlock_irqrestore(&domain->lock, flags);
2285 goto out_free;
2286 }
2287
2288 domain_flush_complete(domain);
2289
2290 spin_unlock_irqrestore(&domain->lock, flags);
2291
2292 return virt_addr;
2293
2294 out_free:
2295
2296 free_pages((unsigned long)virt_addr, get_order(size));
2297
2298 return NULL;
2299 }
2300
2301 /*
2302 * The exported free_coherent function for dma_ops.
2303 */
2304 static void free_coherent(struct device *dev, size_t size,
2305 void *virt_addr, dma_addr_t dma_addr)
2306 {
2307 unsigned long flags;
2308 struct protection_domain *domain;
2309
2310 INC_STATS_COUNTER(cnt_free_coherent);
2311
2312 domain = get_domain(dev);
2313 if (IS_ERR(domain))
2314 goto free_mem;
2315
2316 spin_lock_irqsave(&domain->lock, flags);
2317
2318 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2319
2320 domain_flush_complete(domain);
2321
2322 spin_unlock_irqrestore(&domain->lock, flags);
2323
2324 free_mem:
2325 free_pages((unsigned long)virt_addr, get_order(size));
2326 }
2327
2328 /*
2329 * This function is called by the DMA layer to find out if we can handle a
2330 * particular device. It is part of the dma_ops.
2331 */
2332 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2333 {
2334 return check_device(dev);
2335 }
2336
2337 /*
2338 * The function for pre-allocating protection domains.
2339 *
2340 * If the driver core informs the DMA layer if a driver grabs a device
2341 * we don't need to preallocate the protection domains anymore.
2342 * For now we have to.
2343 */
2344 static void prealloc_protection_domains(void)
2345 {
2346 struct pci_dev *dev = NULL;
2347 struct dma_ops_domain *dma_dom;
2348 u16 devid;
2349
2350 for_each_pci_dev(dev) {
2351
2352 /* Do we handle this device? */
2353 if (!check_device(&dev->dev))
2354 continue;
2355
2356 /* Is there already any domain for it? */
2357 if (domain_for_device(&dev->dev))
2358 continue;
2359
2360 devid = get_device_id(&dev->dev);
2361
2362 dma_dom = dma_ops_domain_alloc();
2363 if (!dma_dom)
2364 continue;
2365 init_unity_mappings_for_device(dma_dom, devid);
2366 dma_dom->target_dev = devid;
2367
2368 attach_device(&dev->dev, &dma_dom->domain);
2369
2370 list_add_tail(&dma_dom->list, &iommu_pd_list);
2371 }
2372 }
2373
2374 static struct dma_map_ops amd_iommu_dma_ops = {
2375 .alloc_coherent = alloc_coherent,
2376 .free_coherent = free_coherent,
2377 .map_page = map_page,
2378 .unmap_page = unmap_page,
2379 .map_sg = map_sg,
2380 .unmap_sg = unmap_sg,
2381 .dma_supported = amd_iommu_dma_supported,
2382 };
2383
2384 /*
2385 * The function which clues the AMD IOMMU driver into dma_ops.
2386 */
2387
2388 void __init amd_iommu_init_api(void)
2389 {
2390 register_iommu(&amd_iommu_ops);
2391 }
2392
2393 int __init amd_iommu_init_dma_ops(void)
2394 {
2395 struct amd_iommu *iommu;
2396 int ret;
2397
2398 /*
2399 * first allocate a default protection domain for every IOMMU we
2400 * found in the system. Devices not assigned to any other
2401 * protection domain will be assigned to the default one.
2402 */
2403 for_each_iommu(iommu) {
2404 iommu->default_dom = dma_ops_domain_alloc();
2405 if (iommu->default_dom == NULL)
2406 return -ENOMEM;
2407 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2408 ret = iommu_init_unity_mappings(iommu);
2409 if (ret)
2410 goto free_domains;
2411 }
2412
2413 /*
2414 * Pre-allocate the protection domains for each device.
2415 */
2416 prealloc_protection_domains();
2417
2418 iommu_detected = 1;
2419 swiotlb = 0;
2420
2421 /* Make the driver finally visible to the drivers */
2422 dma_ops = &amd_iommu_dma_ops;
2423
2424 amd_iommu_stats_init();
2425
2426 return 0;
2427
2428 free_domains:
2429
2430 for_each_iommu(iommu) {
2431 if (iommu->default_dom)
2432 dma_ops_domain_free(iommu->default_dom);
2433 }
2434
2435 return ret;
2436 }
2437
2438 /*****************************************************************************
2439 *
2440 * The following functions belong to the exported interface of AMD IOMMU
2441 *
2442 * This interface allows access to lower level functions of the IOMMU
2443 * like protection domain handling and assignement of devices to domains
2444 * which is not possible with the dma_ops interface.
2445 *
2446 *****************************************************************************/
2447
2448 static void cleanup_domain(struct protection_domain *domain)
2449 {
2450 struct iommu_dev_data *dev_data, *next;
2451 unsigned long flags;
2452
2453 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2454
2455 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2456 struct device *dev = dev_data->dev;
2457
2458 __detach_device(dev);
2459 atomic_set(&dev_data->bind, 0);
2460 }
2461
2462 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2463 }
2464
2465 static void protection_domain_free(struct protection_domain *domain)
2466 {
2467 if (!domain)
2468 return;
2469
2470 del_domain_from_list(domain);
2471
2472 if (domain->id)
2473 domain_id_free(domain->id);
2474
2475 kfree(domain);
2476 }
2477
2478 static struct protection_domain *protection_domain_alloc(void)
2479 {
2480 struct protection_domain *domain;
2481
2482 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2483 if (!domain)
2484 return NULL;
2485
2486 spin_lock_init(&domain->lock);
2487 mutex_init(&domain->api_lock);
2488 domain->id = domain_id_alloc();
2489 if (!domain->id)
2490 goto out_err;
2491 INIT_LIST_HEAD(&domain->dev_list);
2492
2493 add_domain_to_list(domain);
2494
2495 return domain;
2496
2497 out_err:
2498 kfree(domain);
2499
2500 return NULL;
2501 }
2502
2503 static int amd_iommu_domain_init(struct iommu_domain *dom)
2504 {
2505 struct protection_domain *domain;
2506
2507 domain = protection_domain_alloc();
2508 if (!domain)
2509 goto out_free;
2510
2511 domain->mode = PAGE_MODE_3_LEVEL;
2512 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2513 if (!domain->pt_root)
2514 goto out_free;
2515
2516 dom->priv = domain;
2517
2518 return 0;
2519
2520 out_free:
2521 protection_domain_free(domain);
2522
2523 return -ENOMEM;
2524 }
2525
2526 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2527 {
2528 struct protection_domain *domain = dom->priv;
2529
2530 if (!domain)
2531 return;
2532
2533 if (domain->dev_cnt > 0)
2534 cleanup_domain(domain);
2535
2536 BUG_ON(domain->dev_cnt != 0);
2537
2538 free_pagetable(domain);
2539
2540 protection_domain_free(domain);
2541
2542 dom->priv = NULL;
2543 }
2544
2545 static void amd_iommu_detach_device(struct iommu_domain *dom,
2546 struct device *dev)
2547 {
2548 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2549 struct amd_iommu *iommu;
2550 u16 devid;
2551
2552 if (!check_device(dev))
2553 return;
2554
2555 devid = get_device_id(dev);
2556
2557 if (dev_data->domain != NULL)
2558 detach_device(dev);
2559
2560 iommu = amd_iommu_rlookup_table[devid];
2561 if (!iommu)
2562 return;
2563
2564 device_flush_dte(dev);
2565 iommu_completion_wait(iommu);
2566 }
2567
2568 static int amd_iommu_attach_device(struct iommu_domain *dom,
2569 struct device *dev)
2570 {
2571 struct protection_domain *domain = dom->priv;
2572 struct iommu_dev_data *dev_data;
2573 struct amd_iommu *iommu;
2574 int ret;
2575 u16 devid;
2576
2577 if (!check_device(dev))
2578 return -EINVAL;
2579
2580 dev_data = dev->archdata.iommu;
2581
2582 devid = get_device_id(dev);
2583
2584 iommu = amd_iommu_rlookup_table[devid];
2585 if (!iommu)
2586 return -EINVAL;
2587
2588 if (dev_data->domain)
2589 detach_device(dev);
2590
2591 ret = attach_device(dev, domain);
2592
2593 iommu_completion_wait(iommu);
2594
2595 return ret;
2596 }
2597
2598 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2599 phys_addr_t paddr, int gfp_order, int iommu_prot)
2600 {
2601 unsigned long page_size = 0x1000UL << gfp_order;
2602 struct protection_domain *domain = dom->priv;
2603 int prot = 0;
2604 int ret;
2605
2606 if (iommu_prot & IOMMU_READ)
2607 prot |= IOMMU_PROT_IR;
2608 if (iommu_prot & IOMMU_WRITE)
2609 prot |= IOMMU_PROT_IW;
2610
2611 mutex_lock(&domain->api_lock);
2612 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2613 mutex_unlock(&domain->api_lock);
2614
2615 return ret;
2616 }
2617
2618 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2619 int gfp_order)
2620 {
2621 struct protection_domain *domain = dom->priv;
2622 unsigned long page_size, unmap_size;
2623
2624 page_size = 0x1000UL << gfp_order;
2625
2626 mutex_lock(&domain->api_lock);
2627 unmap_size = iommu_unmap_page(domain, iova, page_size);
2628 mutex_unlock(&domain->api_lock);
2629
2630 domain_flush_tlb_pde(domain);
2631
2632 return get_order(unmap_size);
2633 }
2634
2635 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2636 unsigned long iova)
2637 {
2638 struct protection_domain *domain = dom->priv;
2639 unsigned long offset_mask;
2640 phys_addr_t paddr;
2641 u64 *pte, __pte;
2642
2643 pte = fetch_pte(domain, iova);
2644
2645 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2646 return 0;
2647
2648 if (PM_PTE_LEVEL(*pte) == 0)
2649 offset_mask = PAGE_SIZE - 1;
2650 else
2651 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2652
2653 __pte = *pte & PM_ADDR_MASK;
2654 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2655
2656 return paddr;
2657 }
2658
2659 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2660 unsigned long cap)
2661 {
2662 switch (cap) {
2663 case IOMMU_CAP_CACHE_COHERENCY:
2664 return 1;
2665 }
2666
2667 return 0;
2668 }
2669
2670 static struct iommu_ops amd_iommu_ops = {
2671 .domain_init = amd_iommu_domain_init,
2672 .domain_destroy = amd_iommu_domain_destroy,
2673 .attach_dev = amd_iommu_attach_device,
2674 .detach_dev = amd_iommu_detach_device,
2675 .map = amd_iommu_map,
2676 .unmap = amd_iommu_unmap,
2677 .iova_to_phys = amd_iommu_iova_to_phys,
2678 .domain_has_cap = amd_iommu_domain_has_cap,
2679 };
2680
2681 /*****************************************************************************
2682 *
2683 * The next functions do a basic initialization of IOMMU for pass through
2684 * mode
2685 *
2686 * In passthrough mode the IOMMU is initialized and enabled but not used for
2687 * DMA-API translation.
2688 *
2689 *****************************************************************************/
2690
2691 int __init amd_iommu_init_passthrough(void)
2692 {
2693 struct amd_iommu *iommu;
2694 struct pci_dev *dev = NULL;
2695 u16 devid;
2696
2697 /* allocate passthrough domain */
2698 pt_domain = protection_domain_alloc();
2699 if (!pt_domain)
2700 return -ENOMEM;
2701
2702 pt_domain->mode |= PAGE_MODE_NONE;
2703
2704 for_each_pci_dev(dev) {
2705 if (!check_device(&dev->dev))
2706 continue;
2707
2708 devid = get_device_id(&dev->dev);
2709
2710 iommu = amd_iommu_rlookup_table[devid];
2711 if (!iommu)
2712 continue;
2713
2714 attach_device(&dev->dev, pt_domain);
2715 }
2716
2717 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2718
2719 return 0;
2720 }
Linux kernel - Deliverables
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