2 * apb_timer.c: Driver for Langwell APB timers
4 * (C) Copyright 2009 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 * Langwell is the south complex of Intel Moorestown MID platform. There are
14 * eight external timers in total that can be used by the operating system.
15 * The timer information, such as frequency and addresses, is provided to the
17 * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
18 * individual redirection table entries (RTE).
19 * Unlike HPET, there is no master counter, therefore one of the timers are
20 * used as clocksource. The overall allocation looks like:
21 * - timer 0 - NR_CPUs for per cpu timer
22 * - one timer for clocksource
23 * - one timer for watchdog driver.
24 * It is also worth notice that APB timer does not support true one-shot mode,
25 * free-running mode will be used here to emulate one-shot mode.
26 * APB timer can also be used as broadcast timer along with per cpu local APIC
27 * timer, but by default APB timer has higher rating than local APIC timers.
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/delay.h>
33 #include <linux/errno.h>
34 #include <linux/init.h>
35 #include <linux/sysdev.h>
36 #include <linux/slab.h>
38 #include <linux/pci.h>
39 #include <linux/sfi.h>
40 #include <linux/interrupt.h>
41 #include <linux/cpu.h>
42 #include <linux/irq.h>
44 #include <asm/fixmap.h>
45 #include <asm/apb_timer.h>
48 #define APBT_MASK CLOCKSOURCE_MASK(32)
50 #define APBT_CLOCKEVENT_RATING 110
51 #define APBT_CLOCKSOURCE_RATING 250
52 #define APBT_MIN_DELTA_USEC 200
54 #define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
55 #define APBT_CLOCKEVENT0_NUM (0)
56 #define APBT_CLOCKEVENT1_NUM (1)
57 #define APBT_CLOCKSOURCE_NUM (2)
59 static unsigned long apbt_address
;
60 static int apb_timer_block_enabled
;
61 static void __iomem
*apbt_virt_address
;
62 static int phy_cs_timer_id
;
65 * Common DW APB timer info
67 static uint64_t apbt_freq
;
69 static void apbt_set_mode(enum clock_event_mode mode
,
70 struct clock_event_device
*evt
);
71 static int apbt_next_event(unsigned long delta
,
72 struct clock_event_device
*evt
);
73 static cycle_t
apbt_read_clocksource(struct clocksource
*cs
);
74 static void apbt_restart_clocksource(struct clocksource
*cs
);
77 struct clock_event_device evt
;
87 static DEFINE_PER_CPU(struct apbt_dev
, cpu_apbt_dev
);
90 static unsigned int apbt_num_timers_used
;
91 static struct apbt_dev
*apbt_devs
;
94 static inline unsigned long apbt_readl_reg(unsigned long a
)
96 return readl(apbt_virt_address
+ a
);
99 static inline void apbt_writel_reg(unsigned long d
, unsigned long a
)
101 writel(d
, apbt_virt_address
+ a
);
104 static inline unsigned long apbt_readl(int n
, unsigned long a
)
106 return readl(apbt_virt_address
+ a
+ n
* APBTMRS_REG_SIZE
);
109 static inline void apbt_writel(int n
, unsigned long d
, unsigned long a
)
111 writel(d
, apbt_virt_address
+ a
+ n
* APBTMRS_REG_SIZE
);
114 static inline void apbt_set_mapping(void)
116 struct sfi_timer_table_entry
*mtmr
;
118 if (apbt_virt_address
) {
119 pr_debug("APBT base already mapped\n");
122 mtmr
= sfi_get_mtmr(APBT_CLOCKEVENT0_NUM
);
124 printk(KERN_ERR
"Failed to get MTMR %d from SFI\n",
125 APBT_CLOCKEVENT0_NUM
);
128 apbt_address
= (unsigned long)mtmr
->phys_addr
;
130 printk(KERN_WARNING
"No timer base from SFI, use default\n");
131 apbt_address
= APBT_DEFAULT_BASE
;
133 apbt_virt_address
= ioremap_nocache(apbt_address
, APBT_MMAP_SIZE
);
134 if (apbt_virt_address
) {
135 pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\
136 (void *)apbt_address
, (void *)apbt_virt_address
);
138 pr_debug("Failed mapping APBT phy address at %p\n",\
139 (void *)apbt_address
);
142 apbt_freq
= mtmr
->freq_hz
/ USEC_PER_SEC
;
145 /* Now figure out the physical timer id for clocksource device */
146 mtmr
= sfi_get_mtmr(APBT_CLOCKSOURCE_NUM
);
150 /* Now figure out the physical timer id */
151 phy_cs_timer_id
= (unsigned int)(mtmr
->phys_addr
& 0xff)
153 pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id
);
157 panic("Failed to setup APB system timer\n");
161 static inline void apbt_clear_mapping(void)
163 iounmap(apbt_virt_address
);
164 apbt_virt_address
= NULL
;
168 * APBT timer interrupt enable / disable
170 static inline int is_apbt_capable(void)
172 return apbt_virt_address
? 1 : 0;
175 static struct clocksource clocksource_apbt
= {
177 .rating
= APBT_CLOCKSOURCE_RATING
,
178 .read
= apbt_read_clocksource
,
181 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
182 .resume
= apbt_restart_clocksource
,
185 /* boot APB clock event device */
186 static struct clock_event_device apbt_clockevent
= {
188 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
189 .set_mode
= apbt_set_mode
,
190 .set_next_event
= apbt_next_event
,
193 .rating
= APBT_CLOCKEVENT_RATING
,
197 * start count down from 0xffff_ffff. this is done by toggling the enable bit
198 * then load initial load count to ~0.
200 static void apbt_start_counter(int n
)
202 unsigned long ctrl
= apbt_readl(n
, APBTMR_N_CONTROL
);
204 ctrl
&= ~APBTMR_CONTROL_ENABLE
;
205 apbt_writel(n
, ctrl
, APBTMR_N_CONTROL
);
206 apbt_writel(n
, ~0, APBTMR_N_LOAD_COUNT
);
207 /* enable, mask interrupt */
208 ctrl
&= ~APBTMR_CONTROL_MODE_PERIODIC
;
209 ctrl
|= (APBTMR_CONTROL_ENABLE
| APBTMR_CONTROL_INT
);
210 apbt_writel(n
, ctrl
, APBTMR_N_CONTROL
);
211 /* read it once to get cached counter value initialized */
212 apbt_read_clocksource(&clocksource_apbt
);
215 static irqreturn_t
apbt_interrupt_handler(int irq
, void *data
)
217 struct apbt_dev
*dev
= (struct apbt_dev
*)data
;
218 struct clock_event_device
*aevt
= &dev
->evt
;
220 if (!aevt
->event_handler
) {
221 printk(KERN_INFO
"Spurious APBT timer interrupt on %d\n",
225 aevt
->event_handler(aevt
);
229 static void apbt_restart_clocksource(struct clocksource
*cs
)
231 apbt_start_counter(phy_cs_timer_id
);
234 static void apbt_enable_int(int n
)
236 unsigned long ctrl
= apbt_readl(n
, APBTMR_N_CONTROL
);
237 /* clear pending intr */
238 apbt_readl(n
, APBTMR_N_EOI
);
239 ctrl
&= ~APBTMR_CONTROL_INT
;
240 apbt_writel(n
, ctrl
, APBTMR_N_CONTROL
);
243 static void apbt_disable_int(int n
)
245 unsigned long ctrl
= apbt_readl(n
, APBTMR_N_CONTROL
);
247 ctrl
|= APBTMR_CONTROL_INT
;
248 apbt_writel(n
, ctrl
, APBTMR_N_CONTROL
);
252 static int __init
apbt_clockevent_register(void)
254 struct sfi_timer_table_entry
*mtmr
;
255 struct apbt_dev
*adev
= &__get_cpu_var(cpu_apbt_dev
);
257 mtmr
= sfi_get_mtmr(APBT_CLOCKEVENT0_NUM
);
259 printk(KERN_ERR
"Failed to get MTMR %d from SFI\n",
260 APBT_CLOCKEVENT0_NUM
);
265 * We need to calculate the scaled math multiplication factor for
266 * nanosecond to apbt tick conversion.
267 * mult = (nsec/cycle)*2^APBT_SHIFT
269 apbt_clockevent
.mult
= div_sc((unsigned long) mtmr
->freq_hz
270 , NSEC_PER_SEC
, APBT_SHIFT
);
272 /* Calculate the min / max delta */
273 apbt_clockevent
.max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF,
275 apbt_clockevent
.min_delta_ns
= clockevent_delta2ns(
276 APBT_MIN_DELTA_USEC
*apbt_freq
,
279 * Start apbt with the boot cpu mask and make it
280 * global if not used for per cpu timer.
282 apbt_clockevent
.cpumask
= cpumask_of(smp_processor_id());
283 adev
->num
= smp_processor_id();
284 memcpy(&adev
->evt
, &apbt_clockevent
, sizeof(struct clock_event_device
));
286 if (mrst_timer_options
== MRST_TIMER_LAPIC_APBT
) {
287 apbt_clockevent
.rating
= APBT_CLOCKEVENT_RATING
- 100;
288 global_clock_event
= &adev
->evt
;
289 printk(KERN_DEBUG
"%s clockevent registered as global\n",
290 global_clock_event
->name
);
293 if (request_irq(apbt_clockevent
.irq
, apbt_interrupt_handler
,
294 IRQF_TIMER
| IRQF_DISABLED
| IRQF_NOBALANCING
,
295 apbt_clockevent
.name
, adev
)) {
296 printk(KERN_ERR
"Failed request IRQ for APBT%d\n",
297 apbt_clockevent
.irq
);
300 clockevents_register_device(&adev
->evt
);
301 /* Start APBT 0 interrupts */
302 apbt_enable_int(APBT_CLOCKEVENT0_NUM
);
310 static void apbt_setup_irq(struct apbt_dev
*adev
)
312 /* timer0 irq has been setup early */
316 if (system_state
== SYSTEM_BOOTING
) {
317 irq_modify_status(adev
->irq
, 0, IRQ_MOVE_PCNTXT
);
318 irq_set_affinity(adev
->irq
, cpumask_of(adev
->cpu
));
319 /* APB timer irqs are set up as mp_irqs, timer is edge type */
320 __set_irq_handler(adev
->irq
, handle_edge_irq
, 0, "edge");
321 if (request_irq(adev
->irq
, apbt_interrupt_handler
,
322 IRQF_TIMER
| IRQF_DISABLED
| IRQF_NOBALANCING
,
324 printk(KERN_ERR
"Failed request IRQ for APBT%d\n",
328 enable_irq(adev
->irq
);
331 /* Should be called with per cpu */
332 void apbt_setup_secondary_clock(void)
334 struct apbt_dev
*adev
;
335 struct clock_event_device
*aevt
;
338 /* Don't register boot CPU clockevent */
339 cpu
= smp_processor_id();
343 * We need to calculate the scaled math multiplication factor for
344 * nanosecond to apbt tick conversion.
345 * mult = (nsec/cycle)*2^APBT_SHIFT
347 printk(KERN_INFO
"Init per CPU clockevent %d\n", cpu
);
348 adev
= &per_cpu(cpu_apbt_dev
, cpu
);
351 memcpy(aevt
, &apbt_clockevent
, sizeof(*aevt
));
352 aevt
->cpumask
= cpumask_of(cpu
);
353 aevt
->name
= adev
->name
;
354 aevt
->mode
= CLOCK_EVT_MODE_UNUSED
;
356 printk(KERN_INFO
"Registering CPU %d clockevent device %s, mask %08x\n",
357 cpu
, aevt
->name
, *(u32
*)aevt
->cpumask
);
359 apbt_setup_irq(adev
);
361 clockevents_register_device(aevt
);
363 apbt_enable_int(cpu
);
369 * this notify handler process CPU hotplug events. in case of S0i3, nonboot
370 * cpus are disabled/enabled frequently, for performance reasons, we keep the
371 * per cpu timer irq registered so that we do need to do free_irq/request_irq.
373 * TODO: it might be more reliable to directly disable percpu clockevent device
374 * without the notifier chain. currently, cpu 0 may get interrupts from other
375 * cpu timers during the offline process due to the ordering of notification.
376 * the extra interrupt is harmless.
378 static int apbt_cpuhp_notify(struct notifier_block
*n
,
379 unsigned long action
, void *hcpu
)
381 unsigned long cpu
= (unsigned long)hcpu
;
382 struct apbt_dev
*adev
= &per_cpu(cpu_apbt_dev
, cpu
);
384 switch (action
& 0xf) {
386 disable_irq(adev
->irq
);
387 apbt_disable_int(cpu
);
388 if (system_state
== SYSTEM_RUNNING
) {
389 pr_debug("skipping APBT CPU %lu offline\n", cpu
);
391 pr_debug("APBT clockevent for cpu %lu offline\n", cpu
);
392 free_irq(adev
->irq
, adev
);
396 pr_debug("APBT notified %lu, no action\n", action
);
401 static __init
int apbt_late_init(void)
403 if (mrst_timer_options
== MRST_TIMER_LAPIC_APBT
||
404 !apb_timer_block_enabled
)
406 /* This notifier should be called after workqueue is ready */
407 hotcpu_notifier(apbt_cpuhp_notify
, -20);
410 fs_initcall(apbt_late_init
);
413 void apbt_setup_secondary_clock(void) {}
415 #endif /* CONFIG_SMP */
417 static void apbt_set_mode(enum clock_event_mode mode
,
418 struct clock_event_device
*evt
)
423 struct apbt_dev
*adev
= EVT_TO_APBT_DEV(evt
);
425 BUG_ON(!apbt_virt_address
);
427 timer_num
= adev
->num
;
428 pr_debug("%s CPU %d timer %d mode=%d\n",
429 __func__
, first_cpu(*evt
->cpumask
), timer_num
, mode
);
432 case CLOCK_EVT_MODE_PERIODIC
:
433 delta
= ((uint64_t)(NSEC_PER_SEC
/HZ
)) * apbt_clockevent
.mult
;
434 delta
>>= apbt_clockevent
.shift
;
435 ctrl
= apbt_readl(timer_num
, APBTMR_N_CONTROL
);
436 ctrl
|= APBTMR_CONTROL_MODE_PERIODIC
;
437 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
439 * DW APB p. 46, have to disable timer before load counter,
440 * may cause sync problem.
442 ctrl
&= ~APBTMR_CONTROL_ENABLE
;
443 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
445 pr_debug("Setting clock period %d for HZ %d\n", (int)delta
, HZ
);
446 apbt_writel(timer_num
, delta
, APBTMR_N_LOAD_COUNT
);
447 ctrl
|= APBTMR_CONTROL_ENABLE
;
448 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
450 /* APB timer does not have one-shot mode, use free running mode */
451 case CLOCK_EVT_MODE_ONESHOT
:
452 ctrl
= apbt_readl(timer_num
, APBTMR_N_CONTROL
);
454 * set free running mode, this mode will let timer reload max
455 * timeout which will give time (3min on 25MHz clock) to rearm
456 * the next event, therefore emulate the one-shot mode.
458 ctrl
&= ~APBTMR_CONTROL_ENABLE
;
459 ctrl
&= ~APBTMR_CONTROL_MODE_PERIODIC
;
461 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
462 /* write again to set free running mode */
463 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
466 * DW APB p. 46, load counter with all 1s before starting free
469 apbt_writel(timer_num
, ~0, APBTMR_N_LOAD_COUNT
);
470 ctrl
&= ~APBTMR_CONTROL_INT
;
471 ctrl
|= APBTMR_CONTROL_ENABLE
;
472 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
475 case CLOCK_EVT_MODE_UNUSED
:
476 case CLOCK_EVT_MODE_SHUTDOWN
:
477 apbt_disable_int(timer_num
);
478 ctrl
= apbt_readl(timer_num
, APBTMR_N_CONTROL
);
479 ctrl
&= ~APBTMR_CONTROL_ENABLE
;
480 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
483 case CLOCK_EVT_MODE_RESUME
:
484 apbt_enable_int(timer_num
);
489 static int apbt_next_event(unsigned long delta
,
490 struct clock_event_device
*evt
)
495 struct apbt_dev
*adev
= EVT_TO_APBT_DEV(evt
);
497 timer_num
= adev
->num
;
499 ctrl
= apbt_readl(timer_num
, APBTMR_N_CONTROL
);
500 ctrl
&= ~APBTMR_CONTROL_ENABLE
;
501 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
502 /* write new count */
503 apbt_writel(timer_num
, delta
, APBTMR_N_LOAD_COUNT
);
504 ctrl
|= APBTMR_CONTROL_ENABLE
;
505 apbt_writel(timer_num
, ctrl
, APBTMR_N_CONTROL
);
510 * APB timer clock is not in sync with pclk on Langwell, which translates to
511 * unreliable read value caused by sampling error. the error does not add up
512 * overtime and only happens when sampling a 0 as a 1 by mistake. so the time
513 * would go backwards. the following code is trying to prevent time traveling
514 * backwards. little bit paranoid.
516 static cycle_t
apbt_read_clocksource(struct clocksource
*cs
)
518 unsigned long t0
, t1
, t2
;
519 static unsigned long last_read
;
522 t1
= apbt_readl(phy_cs_timer_id
,
523 APBTMR_N_CURRENT_VALUE
);
524 t2
= apbt_readl(phy_cs_timer_id
,
525 APBTMR_N_CURRENT_VALUE
);
526 if (unlikely(t1
< t2
)) {
527 pr_debug("APBT: read current count error %lx:%lx:%lx\n",
532 * check against cached last read, makes sure time does not go back.
533 * it could be a normal rollover but we will do tripple check anyway
535 if (unlikely(t2
> last_read
)) {
536 /* check if we have a normal rollover */
537 unsigned long raw_intr_status
=
538 apbt_readl_reg(APBTMRS_RAW_INT_STATUS
);
540 * cs timer interrupt is masked but raw intr bit is set if
541 * rollover occurs. then we read EOI reg to clear it.
543 if (raw_intr_status
& (1 << phy_cs_timer_id
)) {
544 apbt_readl(phy_cs_timer_id
, APBTMR_N_EOI
);
547 pr_debug("APB CS going back %lx:%lx:%lx ",
548 t2
, last_read
, t2
- last_read
);
550 pr_debug("triple check enforced\n");
551 t0
= apbt_readl(phy_cs_timer_id
,
552 APBTMR_N_CURRENT_VALUE
);
554 t1
= apbt_readl(phy_cs_timer_id
,
555 APBTMR_N_CURRENT_VALUE
);
557 t2
= apbt_readl(phy_cs_timer_id
,
558 APBTMR_N_CURRENT_VALUE
);
559 if ((t2
> t1
) || (t1
> t0
)) {
560 printk(KERN_ERR
"Error: APB CS tripple check failed\n");
569 static int apbt_clocksource_register(void)
574 /* Start the counter, use timer 2 as source, timer 0/1 for event */
575 apbt_start_counter(phy_cs_timer_id
);
577 /* Verify whether apbt counter works */
578 t1
= apbt_read_clocksource(&clocksource_apbt
);
582 * We don't know the TSC frequency yet, but waiting for
583 * 200000 TSC cycles is safe:
590 } while ((now
- start
) < 200000UL);
592 /* APBT is the only always on clocksource, it has to work! */
593 if (t1
== apbt_read_clocksource(&clocksource_apbt
))
594 panic("APBT counter not counting. APBT disabled\n");
597 * initialize and register APBT clocksource
598 * convert that to ns/clock cycle
599 * mult = (ns/c) * 2^APBT_SHIFT
601 clocksource_apbt
.mult
= div_sc(MSEC_PER_SEC
,
602 (unsigned long) apbt_freq
, APBT_SHIFT
);
603 clocksource_register(&clocksource_apbt
);
609 * Early setup the APBT timer, only use timer 0 for booting then switch to
610 * per CPU timer if possible.
611 * returns 1 if per cpu apbt is setup
612 * returns 0 if no per cpu apbt is chosen
613 * panic if set up failed, this is the only platform timer on Moorestown.
615 void __init
apbt_time_init(void)
619 struct sfi_timer_table_entry
*p_mtmr
;
620 unsigned int percpu_timer
;
621 struct apbt_dev
*adev
;
624 if (apb_timer_block_enabled
)
627 if (apbt_virt_address
) {
628 pr_debug("Found APBT version 0x%lx\n",\
629 apbt_readl_reg(APBTMRS_COMP_VERSION
));
633 * Read the frequency and check for a sane value, for ESL model
634 * we extend the possible clock range to allow time scaling.
637 if (apbt_freq
< APBT_MIN_FREQ
|| apbt_freq
> APBT_MAX_FREQ
) {
638 pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq
);
641 if (apbt_clocksource_register()) {
642 pr_debug("APBT has failed to register clocksource\n");
645 if (!apbt_clockevent_register())
646 apb_timer_block_enabled
= 1;
648 pr_debug("APBT has failed to register clockevent\n");
652 /* kernel cmdline disable apb timer, so we will use lapic timers */
653 if (mrst_timer_options
== MRST_TIMER_LAPIC_APBT
) {
654 printk(KERN_INFO
"apbt: disabled per cpu timer\n");
657 pr_debug("%s: %d CPUs online\n", __func__
, num_online_cpus());
658 if (num_possible_cpus() <= sfi_mtimer_num
) {
660 apbt_num_timers_used
= num_possible_cpus();
663 apbt_num_timers_used
= 1;
664 adev
= &per_cpu(cpu_apbt_dev
, 0);
665 adev
->flags
&= ~APBT_DEV_USED
;
667 pr_debug("%s: %d APB timers used\n", __func__
, apbt_num_timers_used
);
669 /* here we set up per CPU timer data structure */
670 apbt_devs
= kzalloc(sizeof(struct apbt_dev
) * apbt_num_timers_used
,
673 printk(KERN_ERR
"Failed to allocate APB timer devices\n");
676 for (i
= 0; i
< apbt_num_timers_used
; i
++) {
677 adev
= &per_cpu(cpu_apbt_dev
, i
);
680 p_mtmr
= sfi_get_mtmr(i
);
682 adev
->tick
= p_mtmr
->freq_hz
;
683 adev
->irq
= p_mtmr
->irq
;
685 printk(KERN_ERR
"Failed to get timer for cpu %d\n", i
);
687 sprintf(adev
->name
, "apbt%d", i
);
694 apbt_clear_mapping();
695 apb_timer_block_enabled
= 0;
696 panic("failed to enable APB timer\n");
699 static inline void apbt_disable(int n
)
701 if (is_apbt_capable()) {
702 unsigned long ctrl
= apbt_readl(n
, APBTMR_N_CONTROL
);
703 ctrl
&= ~APBTMR_CONTROL_ENABLE
;
704 apbt_writel(n
, ctrl
, APBTMR_N_CONTROL
);
708 /* called before apb_timer_enable, use early map */
709 unsigned long apbt_quick_calibrate()
714 unsigned long khz
= 0;
718 apbt_start_counter(phy_cs_timer_id
);
720 /* check if the timer can count down, otherwise return */
721 old
= apbt_read_clocksource(&clocksource_apbt
);
724 if (old
!= apbt_read_clocksource(&clocksource_apbt
))
731 loop
= (apbt_freq
* 1000) << 4;
733 /* restart the timer to ensure it won't get to 0 in the calibration */
734 apbt_start_counter(phy_cs_timer_id
);
736 old
= apbt_read_clocksource(&clocksource_apbt
);
739 t1
= __native_read_tsc();
742 new = apbt_read_clocksource(&clocksource_apbt
);
745 t2
= __native_read_tsc();
748 if (unlikely(loop
>> shift
== 0)) {
750 "APBT TSC calibration failed, not enough resolution\n");
753 scale
= (int)div_u64((t2
- t1
), loop
>> shift
);
754 khz
= (scale
* apbt_freq
* 1000) >> shift
;
755 printk(KERN_INFO
"TSC freq calculated by APB timer is %lu khz\n", khz
);