2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <linux/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
46 #include <asm/io_apic.h>
55 #include <asm/hypervisor.h>
57 unsigned int num_processors
;
59 unsigned disabled_cpus __cpuinitdata
;
61 /* Processor that is doing the boot up */
62 unsigned int boot_cpu_physical_apicid
= -1U;
65 * The highest APIC ID seen during enumeration.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
85 * On x86_32, the mapping between cpu and logical apicid may vary
86 * depending on apic in use. The following early percpu variable is
87 * used for the mapping. This is where the behaviors of x86_64 and 32
88 * actually diverge. Let's keep it ugly for now.
90 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
93 * Knob to control our willingness to enable the local APIC.
97 static int force_enable_local_apic __initdata
;
99 * APIC command line parameters
101 static int __init
parse_lapic(char *arg
)
103 force_enable_local_apic
= 1;
106 early_param("lapic", parse_lapic
);
107 /* Local APIC was disabled by the BIOS and enabled by the kernel */
108 static int enabled_via_apicbase
;
111 * Handle interrupt mode configuration register (IMCR).
112 * This register controls whether the interrupt signals
113 * that reach the BSP come from the master PIC or from the
114 * local APIC. Before entering Symmetric I/O Mode, either
115 * the BIOS or the operating system must switch out of
116 * PIC Mode by changing the IMCR.
118 static inline void imcr_pic_to_apic(void)
120 /* select IMCR register */
122 /* NMI and 8259 INTR go through APIC */
126 static inline void imcr_apic_to_pic(void)
128 /* select IMCR register */
130 /* NMI and 8259 INTR go directly to BSP */
136 static int apic_calibrate_pmtmr __initdata
;
137 static __init
int setup_apicpmtimer(char *s
)
139 apic_calibrate_pmtmr
= 1;
143 __setup("apicpmtimer", setup_apicpmtimer
);
147 #ifdef CONFIG_X86_X2APIC
148 /* x2apic enabled before OS handover */
149 int x2apic_preenabled
;
150 static int x2apic_disabled
;
152 static __init
int setup_nox2apic(char *str
)
154 if (x2apic_enabled()) {
155 int apicid
= native_apic_msr_read(APIC_ID
);
158 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
163 pr_warning("x2apic already enabled. will disable it\n");
165 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
171 early_param("nox2apic", setup_nox2apic
);
174 unsigned long mp_lapic_addr
;
176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
177 static int disable_apic_timer __initdata
;
178 /* Local APIC timer works in C2 */
179 int local_apic_timer_c2_ok
;
180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
182 int first_system_vector
= 0xfe;
185 * Debug level, exported for io_apic.c
187 unsigned int apic_verbosity
;
191 /* Have we found an MP table */
192 int smp_found_config
;
194 static struct resource lapic_resource
= {
195 .name
= "Local APIC",
196 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
199 unsigned int lapic_timer_frequency
= 0;
201 static void apic_pm_activate(void);
203 static unsigned long apic_phys
;
206 * Get the LAPIC version
208 static inline int lapic_get_version(void)
210 return GET_APIC_VERSION(apic_read(APIC_LVR
));
214 * Check, if the APIC is integrated or a separate chip
216 static inline int lapic_is_integrated(void)
221 return APIC_INTEGRATED(lapic_get_version());
226 * Check, whether this is a modern or a first generation APIC
228 static int modern_apic(void)
230 /* AMD systems use old APIC versions, so check the CPU */
231 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
232 boot_cpu_data
.x86
>= 0xf)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 static void __init
apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
253 u32
native_safe_apic_wait_icr_idle(void)
260 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
263 inc_irq_stat(icr_read_retry_count
);
265 } while (timeout
++ < 1000);
270 void native_apic_icr_write(u32 low
, u32 id
)
272 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
273 apic_write(APIC_ICR
, low
);
276 u64
native_apic_icr_read(void)
280 icr2
= apic_read(APIC_ICR2
);
281 icr1
= apic_read(APIC_ICR
);
283 return icr1
| ((u64
)icr2
<< 32);
288 * get_physical_broadcast - Get number of physical broadcast IDs
290 int get_physical_broadcast(void)
292 return modern_apic() ? 0xff : 0xf;
297 * lapic_get_maxlvt - get the maximum number of local vector table entries
299 int lapic_get_maxlvt(void)
303 v
= apic_read(APIC_LVR
);
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
308 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
316 #define APIC_DIVISOR 16
319 * This function sets up the local APIC timer, with a timeout of
320 * 'clocks' APIC bus clock. During calibration we actually call
321 * this function twice on the boot CPU, once with a bogus timeout
322 * value, second time for real. The other (noncalibrating) CPUs
323 * call this function only once, with the real, calibrated value.
325 * We do reads before writes even if unnecessary, to get around the
326 * P5 APIC double write bug.
328 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
330 unsigned int lvtt_value
, tmp_value
;
332 lvtt_value
= LOCAL_TIMER_VECTOR
;
334 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
335 if (!lapic_is_integrated())
336 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
339 lvtt_value
|= APIC_LVT_MASKED
;
341 apic_write(APIC_LVTT
, lvtt_value
);
346 tmp_value
= apic_read(APIC_TDCR
);
347 apic_write(APIC_TDCR
,
348 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
352 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
356 * Setup extended LVT, AMD specific
358 * Software should use the LVT offsets the BIOS provides. The offsets
359 * are determined by the subsystems using it like those for MCE
360 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
361 * are supported. Beginning with family 10h at least 4 offsets are
364 * Since the offsets must be consistent for all cores, we keep track
365 * of the LVT offsets in software and reserve the offset for the same
366 * vector also to be used on other cores. An offset is freed by
367 * setting the entry to APIC_EILVT_MASKED.
369 * If the BIOS is right, there should be no conflicts. Otherwise a
370 * "[Firmware Bug]: ..." error message is generated. However, if
371 * software does not properly determines the offsets, it is not
372 * necessarily a BIOS bug.
375 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
377 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
379 return (old
& APIC_EILVT_MASKED
)
380 || (new == APIC_EILVT_MASKED
)
381 || ((new & ~APIC_EILVT_MASKED
) == old
);
384 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
386 unsigned int rsvd
, vector
;
388 if (offset
>= APIC_EILVT_NR_MAX
)
391 rsvd
= atomic_read(&eilvt_offsets
[offset
]);
393 vector
= rsvd
& ~APIC_EILVT_MASKED
; /* 0: unassigned */
394 if (vector
&& !eilvt_entry_is_changeable(vector
, new))
395 /* may not change if vectors are different */
397 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
398 } while (rsvd
!= new);
400 rsvd
&= ~APIC_EILVT_MASKED
;
401 if (rsvd
&& rsvd
!= vector
)
402 pr_info("LVT offset %d assigned for vector 0x%02x\n",
409 * If mask=1, the LVT entry does not generate interrupts while mask=0
410 * enables the vector. See also the BKDGs. Must be called with
411 * preemption disabled.
414 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
416 unsigned long reg
= APIC_EILVTn(offset
);
417 unsigned int new, old
, reserved
;
419 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
420 old
= apic_read(reg
);
421 reserved
= reserve_eilvt_offset(offset
, new);
423 if (reserved
!= new) {
424 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
425 "vector 0x%x, but the register is already in use for "
426 "vector 0x%x on another cpu\n",
427 smp_processor_id(), reg
, offset
, new, reserved
);
431 if (!eilvt_entry_is_changeable(old
, new)) {
432 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
433 "vector 0x%x, but the register is already in use for "
434 "vector 0x%x on this cpu\n",
435 smp_processor_id(), reg
, offset
, new, old
);
439 apic_write(reg
, new);
443 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
446 * Program the next event, relative to now
448 static int lapic_next_event(unsigned long delta
,
449 struct clock_event_device
*evt
)
451 apic_write(APIC_TMICT
, delta
);
456 * Setup the lapic timer in periodic or oneshot mode
458 static void lapic_timer_setup(enum clock_event_mode mode
,
459 struct clock_event_device
*evt
)
464 /* Lapic used as dummy for broadcast ? */
465 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
468 local_irq_save(flags
);
471 case CLOCK_EVT_MODE_PERIODIC
:
472 case CLOCK_EVT_MODE_ONESHOT
:
473 __setup_APIC_LVTT(lapic_timer_frequency
,
474 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
476 case CLOCK_EVT_MODE_UNUSED
:
477 case CLOCK_EVT_MODE_SHUTDOWN
:
478 v
= apic_read(APIC_LVTT
);
479 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
480 apic_write(APIC_LVTT
, v
);
481 apic_write(APIC_TMICT
, 0);
483 case CLOCK_EVT_MODE_RESUME
:
484 /* Nothing to do here */
488 local_irq_restore(flags
);
492 * Local APIC timer broadcast function
494 static void lapic_timer_broadcast(const struct cpumask
*mask
)
497 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
503 * The local apic timer can be used for any function which is CPU local.
505 static struct clock_event_device lapic_clockevent
= {
507 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
508 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
510 .set_mode
= lapic_timer_setup
,
511 .set_next_event
= lapic_next_event
,
512 .broadcast
= lapic_timer_broadcast
,
516 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
519 * Setup the local APIC timer for this CPU. Copy the initialized values
520 * of the boot CPU and register the clock event in the framework.
522 static void __cpuinit
setup_APIC_timer(void)
524 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
526 if (this_cpu_has(X86_FEATURE_ARAT
)) {
527 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
528 /* Make LAPIC timer preferrable over percpu HPET */
529 lapic_clockevent
.rating
= 150;
532 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
533 levt
->cpumask
= cpumask_of(smp_processor_id());
535 clockevents_register_device(levt
);
539 * In this functions we calibrate APIC bus clocks to the external timer.
541 * We want to do the calibration only once since we want to have local timer
542 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
545 * This was previously done by reading the PIT/HPET and waiting for a wrap
546 * around to find out, that a tick has elapsed. I have a box, where the PIT
547 * readout is broken, so it never gets out of the wait loop again. This was
548 * also reported by others.
550 * Monitoring the jiffies value is inaccurate and the clockevents
551 * infrastructure allows us to do a simple substitution of the interrupt
554 * The calibration routine also uses the pm_timer when possible, as the PIT
555 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
556 * back to normal later in the boot process).
559 #define LAPIC_CAL_LOOPS (HZ/10)
561 static __initdata
int lapic_cal_loops
= -1;
562 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
563 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
564 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
565 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
568 * Temporary interrupt handler.
570 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
572 unsigned long long tsc
= 0;
573 long tapic
= apic_read(APIC_TMCCT
);
574 unsigned long pm
= acpi_pm_read_early();
579 switch (lapic_cal_loops
++) {
581 lapic_cal_t1
= tapic
;
582 lapic_cal_tsc1
= tsc
;
584 lapic_cal_j1
= jiffies
;
587 case LAPIC_CAL_LOOPS
:
588 lapic_cal_t2
= tapic
;
589 lapic_cal_tsc2
= tsc
;
590 if (pm
< lapic_cal_pm1
)
591 pm
+= ACPI_PM_OVRRUN
;
593 lapic_cal_j2
= jiffies
;
599 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
601 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
602 const long pm_thresh
= pm_100ms
/ 100;
606 #ifndef CONFIG_X86_PM_TIMER
610 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
612 /* Check, if the PM timer is available */
616 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
618 if (deltapm
> (pm_100ms
- pm_thresh
) &&
619 deltapm
< (pm_100ms
+ pm_thresh
)) {
620 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
624 res
= (((u64
)deltapm
) * mult
) >> 22;
625 do_div(res
, 1000000);
626 pr_warning("APIC calibration not consistent "
627 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
629 /* Correct the lapic counter value */
630 res
= (((u64
)(*delta
)) * pm_100ms
);
631 do_div(res
, deltapm
);
632 pr_info("APIC delta adjusted to PM-Timer: "
633 "%lu (%ld)\n", (unsigned long)res
, *delta
);
636 /* Correct the tsc counter value */
638 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
639 do_div(res
, deltapm
);
640 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
641 "PM-Timer: %lu (%ld)\n",
642 (unsigned long)res
, *deltatsc
);
643 *deltatsc
= (long)res
;
649 static int __init
calibrate_APIC_clock(void)
651 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
652 void (*real_handler
)(struct clock_event_device
*dev
);
653 unsigned long deltaj
;
654 long delta
, deltatsc
;
655 int pm_referenced
= 0;
658 * check if lapic timer has already been calibrated by platform
659 * specific routine, such as tsc calibration code. if so, we just fill
660 * in the clockevent structure and return.
663 if (lapic_timer_frequency
) {
664 apic_printk(APIC_VERBOSE
, "lapic timer already calibrated %d\n",
665 lapic_timer_frequency
);
666 lapic_clockevent
.mult
= div_sc(lapic_timer_frequency
/APIC_DIVISOR
,
667 TICK_NSEC
, lapic_clockevent
.shift
);
668 lapic_clockevent
.max_delta_ns
=
669 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
670 lapic_clockevent
.min_delta_ns
=
671 clockevent_delta2ns(0xF, &lapic_clockevent
);
672 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
678 /* Replace the global interrupt handler */
679 real_handler
= global_clock_event
->event_handler
;
680 global_clock_event
->event_handler
= lapic_cal_handler
;
683 * Setup the APIC counter to maximum. There is no way the lapic
684 * can underflow in the 100ms detection time frame
686 __setup_APIC_LVTT(0xffffffff, 0, 0);
688 /* Let the interrupts run */
691 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
696 /* Restore the real event handler */
697 global_clock_event
->event_handler
= real_handler
;
699 /* Build delta t1-t2 as apic timer counts down */
700 delta
= lapic_cal_t1
- lapic_cal_t2
;
701 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
703 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
705 /* we trust the PM based calibration if possible */
706 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
709 /* Calculate the scaled math multiplication factor */
710 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
711 lapic_clockevent
.shift
);
712 lapic_clockevent
.max_delta_ns
=
713 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
714 lapic_clockevent
.min_delta_ns
=
715 clockevent_delta2ns(0xF, &lapic_clockevent
);
717 lapic_timer_frequency
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
719 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
720 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
721 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
722 lapic_timer_frequency
);
725 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
727 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
728 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
731 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
733 lapic_timer_frequency
/ (1000000 / HZ
),
734 lapic_timer_frequency
% (1000000 / HZ
));
737 * Do a sanity check on the APIC calibration result
739 if (lapic_timer_frequency
< (1000000 / HZ
)) {
741 pr_warning("APIC frequency too slow, disabling apic timer\n");
745 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
748 * PM timer calibration failed or not turned on
749 * so lets try APIC timer based calibration
751 if (!pm_referenced
) {
752 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
755 * Setup the apic timer manually
757 levt
->event_handler
= lapic_cal_handler
;
758 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
759 lapic_cal_loops
= -1;
761 /* Let the interrupts run */
764 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
767 /* Stop the lapic timer */
768 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
771 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
772 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
774 /* Check, if the jiffies result is consistent */
775 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
776 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
778 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
782 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
783 pr_warning("APIC timer disabled due to verification failure\n");
791 * Setup the boot APIC
793 * Calibrate and verify the result.
795 void __init
setup_boot_APIC_clock(void)
798 * The local apic timer can be disabled via the kernel
799 * commandline or from the CPU detection code. Register the lapic
800 * timer as a dummy clock event source on SMP systems, so the
801 * broadcast mechanism is used. On UP systems simply ignore it.
803 if (disable_apic_timer
) {
804 pr_info("Disabling APIC timer\n");
805 /* No broadcast on UP ! */
806 if (num_possible_cpus() > 1) {
807 lapic_clockevent
.mult
= 1;
813 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
814 "calibrating APIC timer ...\n");
816 if (calibrate_APIC_clock()) {
817 /* No broadcast on UP ! */
818 if (num_possible_cpus() > 1)
824 * If nmi_watchdog is set to IO_APIC, we need the
825 * PIT/HPET going. Otherwise register lapic as a dummy
828 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
830 /* Setup the lapic or request the broadcast */
834 void __cpuinit
setup_secondary_APIC_clock(void)
840 * The guts of the apic timer interrupt
842 static void local_apic_timer_interrupt(void)
844 int cpu
= smp_processor_id();
845 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
848 * Normally we should not be here till LAPIC has been initialized but
849 * in some cases like kdump, its possible that there is a pending LAPIC
850 * timer interrupt from previous kernel's context and is delivered in
851 * new kernel the moment interrupts are enabled.
853 * Interrupts are enabled early and LAPIC is setup much later, hence
854 * its possible that when we get here evt->event_handler is NULL.
855 * Check for event_handler being NULL and discard the interrupt as
858 if (!evt
->event_handler
) {
859 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
861 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
866 * the NMI deadlock-detector uses this.
868 inc_irq_stat(apic_timer_irqs
);
870 evt
->event_handler(evt
);
874 * Local APIC timer interrupt. This is the most natural way for doing
875 * local interrupts, but local timer interrupts can be emulated by
876 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
878 * [ if a single-CPU system runs an SMP kernel then we call the local
879 * interrupt as well. Thus we cannot inline the local irq ... ]
881 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
883 struct pt_regs
*old_regs
= set_irq_regs(regs
);
886 * NOTE! We'd better ACK the irq immediately,
887 * because timer handling can be slow.
891 * update_process_times() expects us to have done irq_enter().
892 * Besides, if we don't timer interrupts ignore the global
893 * interrupt lock, which is the WrongThing (tm) to do.
897 local_apic_timer_interrupt();
900 set_irq_regs(old_regs
);
903 int setup_profiling_timer(unsigned int multiplier
)
909 * Local APIC start and shutdown
913 * clear_local_APIC - shutdown the local APIC
915 * This is called, when a CPU is disabled and before rebooting, so the state of
916 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
917 * leftovers during boot.
919 void clear_local_APIC(void)
924 /* APIC hasn't been mapped yet */
925 if (!x2apic_mode
&& !apic_phys
)
928 maxlvt
= lapic_get_maxlvt();
930 * Masking an LVT entry can trigger a local APIC error
931 * if the vector is zero. Mask LVTERR first to prevent this.
934 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
935 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
938 * Careful: we have to set masks only first to deassert
939 * any level-triggered sources.
941 v
= apic_read(APIC_LVTT
);
942 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
943 v
= apic_read(APIC_LVT0
);
944 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
945 v
= apic_read(APIC_LVT1
);
946 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
948 v
= apic_read(APIC_LVTPC
);
949 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
952 /* lets not touch this if we didn't frob it */
953 #ifdef CONFIG_X86_THERMAL_VECTOR
955 v
= apic_read(APIC_LVTTHMR
);
956 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
959 #ifdef CONFIG_X86_MCE_INTEL
961 v
= apic_read(APIC_LVTCMCI
);
962 if (!(v
& APIC_LVT_MASKED
))
963 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
968 * Clean APIC state for other OSs:
970 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
971 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
972 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
974 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
976 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
978 /* Integrated APIC (!82489DX) ? */
979 if (lapic_is_integrated()) {
981 /* Clear ESR due to Pentium errata 3AP and 11AP */
982 apic_write(APIC_ESR
, 0);
988 * disable_local_APIC - clear and disable the local APIC
990 void disable_local_APIC(void)
994 /* APIC hasn't been mapped yet */
995 if (!x2apic_mode
&& !apic_phys
)
1001 * Disable APIC (implies clearing of registers
1004 value
= apic_read(APIC_SPIV
);
1005 value
&= ~APIC_SPIV_APIC_ENABLED
;
1006 apic_write(APIC_SPIV
, value
);
1008 #ifdef CONFIG_X86_32
1010 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1011 * restore the disabled state.
1013 if (enabled_via_apicbase
) {
1016 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1017 l
&= ~MSR_IA32_APICBASE_ENABLE
;
1018 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1024 * If Linux enabled the LAPIC against the BIOS default disable it down before
1025 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1026 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1027 * for the case where Linux didn't enable the LAPIC.
1029 void lapic_shutdown(void)
1031 unsigned long flags
;
1033 if (!cpu_has_apic
&& !apic_from_smp_config())
1036 local_irq_save(flags
);
1038 #ifdef CONFIG_X86_32
1039 if (!enabled_via_apicbase
)
1043 disable_local_APIC();
1046 local_irq_restore(flags
);
1050 * This is to verify that we're looking at a real local APIC.
1051 * Check these against your board if the CPUs aren't getting
1052 * started for no apparent reason.
1054 int __init
verify_local_APIC(void)
1056 unsigned int reg0
, reg1
;
1059 * The version register is read-only in a real APIC.
1061 reg0
= apic_read(APIC_LVR
);
1062 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1063 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1064 reg1
= apic_read(APIC_LVR
);
1065 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1068 * The two version reads above should print the same
1069 * numbers. If the second one is different, then we
1070 * poke at a non-APIC.
1076 * Check if the version looks reasonably.
1078 reg1
= GET_APIC_VERSION(reg0
);
1079 if (reg1
== 0x00 || reg1
== 0xff)
1081 reg1
= lapic_get_maxlvt();
1082 if (reg1
< 0x02 || reg1
== 0xff)
1086 * The ID register is read/write in a real APIC.
1088 reg0
= apic_read(APIC_ID
);
1089 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1090 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1091 reg1
= apic_read(APIC_ID
);
1092 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1093 apic_write(APIC_ID
, reg0
);
1094 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1098 * The next two are just to see if we have sane values.
1099 * They're only really relevant if we're in Virtual Wire
1100 * compatibility mode, but most boxes are anymore.
1102 reg0
= apic_read(APIC_LVT0
);
1103 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1104 reg1
= apic_read(APIC_LVT1
);
1105 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1111 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1113 void __init
sync_Arb_IDs(void)
1116 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1119 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1125 apic_wait_icr_idle();
1127 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1128 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1129 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1133 * An initial setup of the virtual wire mode.
1135 void __init
init_bsp_APIC(void)
1140 * Don't do the setup now if we have a SMP BIOS as the
1141 * through-I/O-APIC virtual wire mode might be active.
1143 if (smp_found_config
|| !cpu_has_apic
)
1147 * Do not trust the local APIC being empty at bootup.
1154 value
= apic_read(APIC_SPIV
);
1155 value
&= ~APIC_VECTOR_MASK
;
1156 value
|= APIC_SPIV_APIC_ENABLED
;
1158 #ifdef CONFIG_X86_32
1159 /* This bit is reserved on P4/Xeon and should be cleared */
1160 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1161 (boot_cpu_data
.x86
== 15))
1162 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1165 value
|= APIC_SPIV_FOCUS_DISABLED
;
1166 value
|= SPURIOUS_APIC_VECTOR
;
1167 apic_write(APIC_SPIV
, value
);
1170 * Set up the virtual wire mode.
1172 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1173 value
= APIC_DM_NMI
;
1174 if (!lapic_is_integrated()) /* 82489DX */
1175 value
|= APIC_LVT_LEVEL_TRIGGER
;
1176 apic_write(APIC_LVT1
, value
);
1179 static void __cpuinit
lapic_setup_esr(void)
1181 unsigned int oldvalue
, value
, maxlvt
;
1183 if (!lapic_is_integrated()) {
1184 pr_info("No ESR for 82489DX.\n");
1188 if (apic
->disable_esr
) {
1190 * Something untraceable is creating bad interrupts on
1191 * secondary quads ... for the moment, just leave the
1192 * ESR disabled - we can't do anything useful with the
1193 * errors anyway - mbligh
1195 pr_info("Leaving ESR disabled.\n");
1199 maxlvt
= lapic_get_maxlvt();
1200 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1201 apic_write(APIC_ESR
, 0);
1202 oldvalue
= apic_read(APIC_ESR
);
1204 /* enables sending errors */
1205 value
= ERROR_APIC_VECTOR
;
1206 apic_write(APIC_LVTERR
, value
);
1209 * spec says clear errors after enabling vector.
1212 apic_write(APIC_ESR
, 0);
1213 value
= apic_read(APIC_ESR
);
1214 if (value
!= oldvalue
)
1215 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1216 "vector: 0x%08x after: 0x%08x\n",
1221 * setup_local_APIC - setup the local APIC
1223 * Used to setup local APIC while initializing BSP or bringin up APs.
1224 * Always called with preemption disabled.
1226 void __cpuinit
setup_local_APIC(void)
1228 int cpu
= smp_processor_id();
1229 unsigned int value
, queued
;
1230 int i
, j
, acked
= 0;
1231 unsigned long long tsc
= 0, ntsc
;
1232 long long max_loops
= cpu_khz
;
1238 disable_ioapic_support();
1242 #ifdef CONFIG_X86_32
1243 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1244 if (lapic_is_integrated() && apic
->disable_esr
) {
1245 apic_write(APIC_ESR
, 0);
1246 apic_write(APIC_ESR
, 0);
1247 apic_write(APIC_ESR
, 0);
1248 apic_write(APIC_ESR
, 0);
1251 perf_events_lapic_init();
1254 * Double-check whether this APIC is really registered.
1255 * This is meaningless in clustered apic mode, so we skip it.
1257 BUG_ON(!apic
->apic_id_registered());
1260 * Intel recommends to set DFR, LDR and TPR before enabling
1261 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1262 * document number 292116). So here it goes...
1264 apic
->init_apic_ldr();
1266 #ifdef CONFIG_X86_32
1268 * APIC LDR is initialized. If logical_apicid mapping was
1269 * initialized during get_smp_config(), make sure it matches the
1272 i
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1273 WARN_ON(i
!= BAD_APICID
&& i
!= logical_smp_processor_id());
1274 /* always use the value from LDR */
1275 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1276 logical_smp_processor_id();
1279 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1280 * node mapping during NUMA init. Now that logical apicid is
1281 * guaranteed to be known, give it another chance. This is already
1282 * a bit too late - percpu allocation has already happened without
1283 * proper NUMA affinity.
1285 if (apic
->x86_32_numa_cpu_node
)
1286 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid
, cpu
),
1287 apic
->x86_32_numa_cpu_node(cpu
));
1291 * Set Task Priority to 'accept all'. We never change this
1294 value
= apic_read(APIC_TASKPRI
);
1295 value
&= ~APIC_TPRI_MASK
;
1296 apic_write(APIC_TASKPRI
, value
);
1299 * After a crash, we no longer service the interrupts and a pending
1300 * interrupt from previous kernel might still have ISR bit set.
1302 * Most probably by now CPU has serviced that pending interrupt and
1303 * it might not have done the ack_APIC_irq() because it thought,
1304 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1305 * does not clear the ISR bit and cpu thinks it has already serivced
1306 * the interrupt. Hence a vector might get locked. It was noticed
1307 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1311 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1312 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1314 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1315 value
= apic_read(APIC_ISR
+ i
*0x10);
1316 for (j
= 31; j
>= 0; j
--) {
1317 if (value
& (1<<j
)) {
1324 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1330 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1333 } while (queued
&& max_loops
> 0);
1334 WARN_ON(max_loops
<= 0);
1337 * Now that we are all set up, enable the APIC
1339 value
= apic_read(APIC_SPIV
);
1340 value
&= ~APIC_VECTOR_MASK
;
1344 value
|= APIC_SPIV_APIC_ENABLED
;
1346 #ifdef CONFIG_X86_32
1348 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1349 * certain networking cards. If high frequency interrupts are
1350 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1351 * entry is masked/unmasked at a high rate as well then sooner or
1352 * later IOAPIC line gets 'stuck', no more interrupts are received
1353 * from the device. If focus CPU is disabled then the hang goes
1356 * [ This bug can be reproduced easily with a level-triggered
1357 * PCI Ne2000 networking cards and PII/PIII processors, dual
1361 * Actually disabling the focus CPU check just makes the hang less
1362 * frequent as it makes the interrupt distributon model be more
1363 * like LRU than MRU (the short-term load is more even across CPUs).
1364 * See also the comment in end_level_ioapic_irq(). --macro
1368 * - enable focus processor (bit==0)
1369 * - 64bit mode always use processor focus
1370 * so no need to set it
1372 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1376 * Set spurious IRQ vector
1378 value
|= SPURIOUS_APIC_VECTOR
;
1379 apic_write(APIC_SPIV
, value
);
1382 * Set up LVT0, LVT1:
1384 * set up through-local-APIC on the BP's LINT0. This is not
1385 * strictly necessary in pure symmetric-IO mode, but sometimes
1386 * we delegate interrupts to the 8259A.
1389 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1391 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1392 if (!cpu
&& (pic_mode
|| !value
)) {
1393 value
= APIC_DM_EXTINT
;
1394 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1396 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1397 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1399 apic_write(APIC_LVT0
, value
);
1402 * only the BP should see the LINT1 NMI signal, obviously.
1405 value
= APIC_DM_NMI
;
1407 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1408 if (!lapic_is_integrated()) /* 82489DX */
1409 value
|= APIC_LVT_LEVEL_TRIGGER
;
1410 apic_write(APIC_LVT1
, value
);
1412 #ifdef CONFIG_X86_MCE_INTEL
1413 /* Recheck CMCI information after local APIC is up on CPU #0 */
1419 void __cpuinit
end_local_APIC_setup(void)
1423 #ifdef CONFIG_X86_32
1426 /* Disable the local apic timer */
1427 value
= apic_read(APIC_LVTT
);
1428 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1429 apic_write(APIC_LVTT
, value
);
1436 void __init
bsp_end_local_APIC_setup(void)
1438 end_local_APIC_setup();
1441 * Now that local APIC setup is completed for BP, configure the fault
1442 * handling for interrupt remapping.
1444 if (intr_remapping_enabled
)
1445 enable_drhd_fault_handling();
1449 #ifdef CONFIG_X86_X2APIC
1451 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1453 static inline void __disable_x2apic(u64 msr
)
1455 wrmsrl(MSR_IA32_APICBASE
,
1456 msr
& ~(X2APIC_ENABLE
| XAPIC_ENABLE
));
1457 wrmsrl(MSR_IA32_APICBASE
, msr
& ~X2APIC_ENABLE
);
1460 static __init
void disable_x2apic(void)
1464 if (!cpu_has_x2apic
)
1467 rdmsrl(MSR_IA32_APICBASE
, msr
);
1468 if (msr
& X2APIC_ENABLE
) {
1469 u32 x2apic_id
= read_apic_id();
1471 if (x2apic_id
>= 255)
1472 panic("Cannot disable x2apic, id: %08x\n", x2apic_id
);
1474 pr_info("Disabling x2apic\n");
1475 __disable_x2apic(msr
);
1478 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC
);
1479 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
1482 x2apic_disabled
= 1;
1485 register_lapic_address(mp_lapic_addr
);
1489 void check_x2apic(void)
1491 if (x2apic_enabled()) {
1492 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1493 x2apic_preenabled
= x2apic_mode
= 1;
1497 void enable_x2apic(void)
1501 rdmsrl(MSR_IA32_APICBASE
, msr
);
1502 if (x2apic_disabled
) {
1503 __disable_x2apic(msr
);
1510 if (!(msr
& X2APIC_ENABLE
)) {
1511 printk_once(KERN_INFO
"Enabling x2apic\n");
1512 wrmsrl(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
);
1515 #endif /* CONFIG_X86_X2APIC */
1517 int __init
enable_IR(void)
1519 #ifdef CONFIG_IRQ_REMAP
1520 if (!intr_remapping_supported()) {
1521 pr_debug("intr-remapping not supported\n");
1525 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1526 pr_info("Skipped enabling intr-remap because of skipping "
1531 return enable_intr_remapping();
1536 void __init
enable_IR_x2apic(void)
1538 unsigned long flags
;
1539 int ret
, x2apic_enabled
= 0;
1540 int dmar_table_init_ret
;
1542 dmar_table_init_ret
= dmar_table_init();
1543 if (dmar_table_init_ret
&& !x2apic_supported())
1546 ret
= save_ioapic_entries();
1548 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1552 local_irq_save(flags
);
1553 legacy_pic
->mask_all();
1554 mask_ioapic_entries();
1556 if (x2apic_preenabled
&& nox2apic
)
1559 if (dmar_table_init_ret
)
1564 if (!x2apic_supported())
1568 /* IR is required if there is APIC ID > 255 even when running
1571 if (max_physical_apicid
> 255 ||
1572 !hypervisor_x2apic_available()) {
1573 if (x2apic_preenabled
)
1578 * without IR all CPUs can be addressed by IOAPIC/MSI
1579 * only in physical mode
1581 x2apic_force_phys();
1584 if (ret
== IRQ_REMAP_XAPIC_MODE
) {
1585 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1591 if (x2apic_supported() && !x2apic_mode
) {
1594 pr_info("Enabled x2apic\n");
1598 if (ret
< 0) /* IR enabling failed */
1599 restore_ioapic_entries();
1600 legacy_pic
->restore_mask();
1601 local_irq_restore(flags
);
1604 #ifdef CONFIG_X86_64
1606 * Detect and enable local APICs on non-SMP boards.
1607 * Original code written by Keir Fraser.
1608 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1609 * not correctly set up (usually the APIC timer won't work etc.)
1611 static int __init
detect_init_APIC(void)
1613 if (!cpu_has_apic
) {
1614 pr_info("No local APIC present\n");
1618 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1623 static int __init
apic_verify(void)
1628 * The APIC feature bit should now be enabled
1631 features
= cpuid_edx(1);
1632 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1633 pr_warning("Could not enable APIC!\n");
1636 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1637 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1639 /* The BIOS may have set up the APIC at some other address */
1640 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1641 if (l
& MSR_IA32_APICBASE_ENABLE
)
1642 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1644 pr_info("Found and enabled local APIC!\n");
1648 int __init
apic_force_enable(unsigned long addr
)
1656 * Some BIOSes disable the local APIC in the APIC_BASE
1657 * MSR. This can only be done in software for Intel P6 or later
1658 * and AMD K7 (Model > 1) or later.
1660 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1661 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1662 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1663 l
&= ~MSR_IA32_APICBASE_BASE
;
1664 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1665 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1666 enabled_via_apicbase
= 1;
1668 return apic_verify();
1672 * Detect and initialize APIC
1674 static int __init
detect_init_APIC(void)
1676 /* Disabled by kernel option? */
1680 switch (boot_cpu_data
.x86_vendor
) {
1681 case X86_VENDOR_AMD
:
1682 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1683 (boot_cpu_data
.x86
>= 15))
1686 case X86_VENDOR_INTEL
:
1687 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1688 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1695 if (!cpu_has_apic
) {
1697 * Over-ride BIOS and try to enable the local APIC only if
1698 * "lapic" specified.
1700 if (!force_enable_local_apic
) {
1701 pr_info("Local APIC disabled by BIOS -- "
1702 "you can enable it with \"lapic\"\n");
1705 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
1717 pr_info("No local APIC present or hardware disabled\n");
1723 * init_apic_mappings - initialize APIC mappings
1725 void __init
init_apic_mappings(void)
1727 unsigned int new_apicid
;
1730 boot_cpu_physical_apicid
= read_apic_id();
1734 /* If no local APIC can be found return early */
1735 if (!smp_found_config
&& detect_init_APIC()) {
1736 /* lets NOP'ify apic operations */
1737 pr_info("APIC: disable apic facility\n");
1740 apic_phys
= mp_lapic_addr
;
1743 * acpi lapic path already maps that address in
1744 * acpi_register_lapic_address()
1746 if (!acpi_lapic
&& !smp_found_config
)
1747 register_lapic_address(apic_phys
);
1751 * Fetch the APIC ID of the BSP in case we have a
1752 * default configuration (or the MP table is broken).
1754 new_apicid
= read_apic_id();
1755 if (boot_cpu_physical_apicid
!= new_apicid
) {
1756 boot_cpu_physical_apicid
= new_apicid
;
1758 * yeah -- we lie about apic_version
1759 * in case if apic was disabled via boot option
1760 * but it's not a problem for SMP compiled kernel
1761 * since smp_sanity_check is prepared for such a case
1762 * and disable smp mode
1764 apic_version
[new_apicid
] =
1765 GET_APIC_VERSION(apic_read(APIC_LVR
));
1769 void __init
register_lapic_address(unsigned long address
)
1771 mp_lapic_addr
= address
;
1774 set_fixmap_nocache(FIX_APIC_BASE
, address
);
1775 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1776 APIC_BASE
, mp_lapic_addr
);
1778 if (boot_cpu_physical_apicid
== -1U) {
1779 boot_cpu_physical_apicid
= read_apic_id();
1780 apic_version
[boot_cpu_physical_apicid
] =
1781 GET_APIC_VERSION(apic_read(APIC_LVR
));
1786 * This initializes the IO-APIC and APIC hardware if this is
1789 int apic_version
[MAX_LOCAL_APIC
];
1791 int __init
APIC_init_uniprocessor(void)
1794 pr_info("Apic disabled\n");
1797 #ifdef CONFIG_X86_64
1798 if (!cpu_has_apic
) {
1800 pr_info("Apic disabled by BIOS\n");
1804 if (!smp_found_config
&& !cpu_has_apic
)
1808 * Complain if the BIOS pretends there is one.
1810 if (!cpu_has_apic
&&
1811 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1812 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1813 boot_cpu_physical_apicid
);
1818 default_setup_apic_routing();
1820 verify_local_APIC();
1823 #ifdef CONFIG_X86_64
1824 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1827 * Hack: In case of kdump, after a crash, kernel might be booting
1828 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1829 * might be zero if read from MP tables. Get it from LAPIC.
1831 # ifdef CONFIG_CRASH_DUMP
1832 boot_cpu_physical_apicid
= read_apic_id();
1835 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1838 #ifdef CONFIG_X86_IO_APIC
1840 * Now enable IO-APICs, actually call clear_IO_APIC
1841 * We need clear_IO_APIC before enabling error vector
1843 if (!skip_ioapic_setup
&& nr_ioapics
)
1847 bsp_end_local_APIC_setup();
1849 #ifdef CONFIG_X86_IO_APIC
1850 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1857 x86_init
.timers
.setup_percpu_clockev();
1862 * Local APIC interrupts
1866 * This interrupt should _never_ happen with our APIC/SMP architecture
1868 void smp_spurious_interrupt(struct pt_regs
*regs
)
1875 * Check if this really is a spurious interrupt and ACK it
1876 * if it is a vectored one. Just in case...
1877 * Spurious interrupts should not be ACKed.
1879 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1880 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1883 inc_irq_stat(irq_spurious_count
);
1885 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1886 pr_info("spurious APIC interrupt on CPU#%d, "
1887 "should never happen.\n", smp_processor_id());
1892 * This interrupt should never happen with our APIC/SMP architecture
1894 void smp_error_interrupt(struct pt_regs
*regs
)
1898 static const char * const error_interrupt_reason
[] = {
1899 "Send CS error", /* APIC Error Bit 0 */
1900 "Receive CS error", /* APIC Error Bit 1 */
1901 "Send accept error", /* APIC Error Bit 2 */
1902 "Receive accept error", /* APIC Error Bit 3 */
1903 "Redirectable IPI", /* APIC Error Bit 4 */
1904 "Send illegal vector", /* APIC Error Bit 5 */
1905 "Received illegal vector", /* APIC Error Bit 6 */
1906 "Illegal register address", /* APIC Error Bit 7 */
1911 /* First tickle the hardware, only then report what went on. -- REW */
1912 v0
= apic_read(APIC_ESR
);
1913 apic_write(APIC_ESR
, 0);
1914 v1
= apic_read(APIC_ESR
);
1916 atomic_inc(&irq_err_count
);
1918 apic_printk(APIC_DEBUG
, KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)",
1919 smp_processor_id(), v0
, v1
);
1924 apic_printk(APIC_DEBUG
, KERN_CONT
" : %s", error_interrupt_reason
[i
]);
1929 apic_printk(APIC_DEBUG
, KERN_CONT
"\n");
1935 * connect_bsp_APIC - attach the APIC to the interrupt system
1937 void __init
connect_bsp_APIC(void)
1939 #ifdef CONFIG_X86_32
1942 * Do not trust the local APIC being empty at bootup.
1946 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1947 * local APIC to INT and NMI lines.
1949 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1950 "enabling APIC mode.\n");
1954 if (apic
->enable_apic_mode
)
1955 apic
->enable_apic_mode();
1959 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1960 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1962 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1965 void disconnect_bsp_APIC(int virt_wire_setup
)
1969 #ifdef CONFIG_X86_32
1972 * Put the board back into PIC mode (has an effect only on
1973 * certain older boards). Note that APIC interrupts, including
1974 * IPIs, won't work beyond this point! The only exception are
1977 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1978 "entering PIC mode.\n");
1984 /* Go back to Virtual Wire compatibility mode */
1986 /* For the spurious interrupt use vector F, and enable it */
1987 value
= apic_read(APIC_SPIV
);
1988 value
&= ~APIC_VECTOR_MASK
;
1989 value
|= APIC_SPIV_APIC_ENABLED
;
1991 apic_write(APIC_SPIV
, value
);
1993 if (!virt_wire_setup
) {
1995 * For LVT0 make it edge triggered, active high,
1996 * external and enabled
1998 value
= apic_read(APIC_LVT0
);
1999 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2000 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2001 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2002 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2003 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
2004 apic_write(APIC_LVT0
, value
);
2007 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
2011 * For LVT1 make it edge triggered, active high,
2014 value
= apic_read(APIC_LVT1
);
2015 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2016 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2017 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2018 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2019 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
2020 apic_write(APIC_LVT1
, value
);
2023 void __cpuinit
generic_processor_info(int apicid
, int version
)
2025 int cpu
, max
= nr_cpu_ids
;
2026 bool boot_cpu_detected
= physid_isset(boot_cpu_physical_apicid
,
2027 phys_cpu_present_map
);
2030 * If boot cpu has not been detected yet, then only allow upto
2031 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2033 if (!boot_cpu_detected
&& num_processors
>= nr_cpu_ids
- 1 &&
2034 apicid
!= boot_cpu_physical_apicid
) {
2035 int thiscpu
= max
+ disabled_cpus
- 1;
2038 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2039 " reached. Keeping one slot for boot cpu."
2040 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2046 if (num_processors
>= nr_cpu_ids
) {
2047 int thiscpu
= max
+ disabled_cpus
;
2050 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2051 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2058 if (apicid
== boot_cpu_physical_apicid
) {
2060 * x86_bios_cpu_apicid is required to have processors listed
2061 * in same order as logical cpu numbers. Hence the first
2062 * entry is BSP, and so on.
2063 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2068 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
2073 if (version
== 0x0) {
2074 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2078 apic_version
[apicid
] = version
;
2080 if (version
!= apic_version
[boot_cpu_physical_apicid
]) {
2081 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2082 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
2085 physid_set(apicid
, phys_cpu_present_map
);
2086 if (apicid
> max_physical_apicid
)
2087 max_physical_apicid
= apicid
;
2089 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2090 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
2091 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
2093 #ifdef CONFIG_X86_32
2094 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
2095 apic
->x86_32_early_logical_apicid(cpu
);
2097 set_cpu_possible(cpu
, true);
2098 set_cpu_present(cpu
, true);
2101 int hard_smp_processor_id(void)
2103 return read_apic_id();
2106 void default_init_apic_ldr(void)
2110 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
2111 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
2112 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2113 apic_write(APIC_LDR
, val
);
2123 * 'active' is true if the local APIC was enabled by us and
2124 * not the BIOS; this signifies that we are also responsible
2125 * for disabling it before entering apm/acpi suspend
2128 /* r/w apic fields */
2129 unsigned int apic_id
;
2130 unsigned int apic_taskpri
;
2131 unsigned int apic_ldr
;
2132 unsigned int apic_dfr
;
2133 unsigned int apic_spiv
;
2134 unsigned int apic_lvtt
;
2135 unsigned int apic_lvtpc
;
2136 unsigned int apic_lvt0
;
2137 unsigned int apic_lvt1
;
2138 unsigned int apic_lvterr
;
2139 unsigned int apic_tmict
;
2140 unsigned int apic_tdcr
;
2141 unsigned int apic_thmr
;
2144 static int lapic_suspend(void)
2146 unsigned long flags
;
2149 if (!apic_pm_state
.active
)
2152 maxlvt
= lapic_get_maxlvt();
2154 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2155 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2156 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2157 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2158 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2159 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2161 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2162 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2163 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2164 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2165 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2166 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2167 #ifdef CONFIG_X86_THERMAL_VECTOR
2169 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2172 local_irq_save(flags
);
2173 disable_local_APIC();
2175 if (intr_remapping_enabled
)
2176 disable_intr_remapping();
2178 local_irq_restore(flags
);
2182 static void lapic_resume(void)
2185 unsigned long flags
;
2188 if (!apic_pm_state
.active
)
2191 local_irq_save(flags
);
2192 if (intr_remapping_enabled
) {
2194 * IO-APIC and PIC have their own resume routines.
2195 * We just mask them here to make sure the interrupt
2196 * subsystem is completely quiet while we enable x2apic
2197 * and interrupt-remapping.
2199 mask_ioapic_entries();
2200 legacy_pic
->mask_all();
2207 * Make sure the APICBASE points to the right address
2209 * FIXME! This will be wrong if we ever support suspend on
2210 * SMP! We'll need to do this as part of the CPU restore!
2212 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2213 l
&= ~MSR_IA32_APICBASE_BASE
;
2214 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2215 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2218 maxlvt
= lapic_get_maxlvt();
2219 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2220 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2221 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2222 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2223 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2224 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2225 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2226 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2227 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2229 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2232 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2233 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2234 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2235 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2236 apic_write(APIC_ESR
, 0);
2237 apic_read(APIC_ESR
);
2238 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2239 apic_write(APIC_ESR
, 0);
2240 apic_read(APIC_ESR
);
2242 if (intr_remapping_enabled
)
2243 reenable_intr_remapping(x2apic_mode
);
2245 local_irq_restore(flags
);
2249 * This device has no shutdown method - fully functioning local APICs
2250 * are needed on every CPU up until machine_halt/restart/poweroff.
2253 static struct syscore_ops lapic_syscore_ops
= {
2254 .resume
= lapic_resume
,
2255 .suspend
= lapic_suspend
,
2258 static void __cpuinit
apic_pm_activate(void)
2260 apic_pm_state
.active
= 1;
2263 static int __init
init_lapic_sysfs(void)
2265 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2267 register_syscore_ops(&lapic_syscore_ops
);
2272 /* local apic needs to resume before other devices access its registers. */
2273 core_initcall(init_lapic_sysfs
);
2275 #else /* CONFIG_PM */
2277 static void apic_pm_activate(void) { }
2279 #endif /* CONFIG_PM */
2281 #ifdef CONFIG_X86_64
2283 static int __cpuinit
apic_cluster_num(void)
2285 int i
, clusters
, zeros
;
2287 u16
*bios_cpu_apicid
;
2288 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2290 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2291 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2293 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2294 /* are we being called early in kernel startup? */
2295 if (bios_cpu_apicid
) {
2296 id
= bios_cpu_apicid
[i
];
2297 } else if (i
< nr_cpu_ids
) {
2299 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2305 if (id
!= BAD_APICID
)
2306 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2309 /* Problem: Partially populated chassis may not have CPUs in some of
2310 * the APIC clusters they have been allocated. Only present CPUs have
2311 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2312 * Since clusters are allocated sequentially, count zeros only if
2313 * they are bounded by ones.
2317 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2318 if (test_bit(i
, clustermap
)) {
2319 clusters
+= 1 + zeros
;
2328 static int __cpuinitdata multi_checked
;
2329 static int __cpuinitdata multi
;
2331 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2335 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2340 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2342 .callback
= set_multi
,
2343 .ident
= "IBM System Summit2",
2345 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2346 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2352 static void __cpuinit
dmi_check_multi(void)
2357 dmi_check_system(multi_dmi_table
);
2362 * apic_is_clustered_box() -- Check if we can expect good TSC
2364 * Thus far, the major user of this is IBM's Summit2 series:
2365 * Clustered boxes may have unsynced TSC problems if they are
2367 * Use DMI to check them
2369 __cpuinit
int apic_is_clustered_box(void)
2379 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2380 * not guaranteed to be synced between boards
2382 if (apic_cluster_num() > 1)
2390 * APIC command line parameters
2392 static int __init
setup_disableapic(char *arg
)
2395 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2398 early_param("disableapic", setup_disableapic
);
2400 /* same as disableapic, for compatibility */
2401 static int __init
setup_nolapic(char *arg
)
2403 return setup_disableapic(arg
);
2405 early_param("nolapic", setup_nolapic
);
2407 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2409 local_apic_timer_c2_ok
= 1;
2412 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2414 static int __init
parse_disable_apic_timer(char *arg
)
2416 disable_apic_timer
= 1;
2419 early_param("noapictimer", parse_disable_apic_timer
);
2421 static int __init
parse_nolapic_timer(char *arg
)
2423 disable_apic_timer
= 1;
2426 early_param("nolapic_timer", parse_nolapic_timer
);
2428 static int __init
apic_set_verbosity(char *arg
)
2431 #ifdef CONFIG_X86_64
2432 skip_ioapic_setup
= 0;
2438 if (strcmp("debug", arg
) == 0)
2439 apic_verbosity
= APIC_DEBUG
;
2440 else if (strcmp("verbose", arg
) == 0)
2441 apic_verbosity
= APIC_VERBOSE
;
2443 pr_warning("APIC Verbosity level %s not recognised"
2444 " use apic=verbose or apic=debug\n", arg
);
2450 early_param("apic", apic_set_verbosity
);
2452 static int __init
lapic_insert_resource(void)
2457 /* Put local APIC into the resource map. */
2458 lapic_resource
.start
= apic_phys
;
2459 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2460 insert_resource(&iomem_resource
, &lapic_resource
);
2466 * need call insert after e820_reserve_resources()
2467 * that is using request_resource
2469 late_initcall(lapic_insert_resource
);