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x86, trace: Add irq vector tracepoints
[deliverable/linux.git] / arch / x86 / kernel / apic / apic.c
1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
37
38 #include <asm/irq_remapping.h>
39 #include <asm/perf_event.h>
40 #include <asm/x86_init.h>
41 #include <asm/pgalloc.h>
42 #include <linux/atomic.h>
43 #include <asm/mpspec.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
46 #include <asm/apic.h>
47 #include <asm/io_apic.h>
48 #include <asm/desc.h>
49 #include <asm/hpet.h>
50 #include <asm/idle.h>
51 #include <asm/mtrr.h>
52 #include <asm/time.h>
53 #include <asm/smp.h>
54 #include <asm/mce.h>
55 #include <asm/tsc.h>
56 #include <asm/hypervisor.h>
57
58 #define CREATE_TRACE_POINTS
59 #include <asm/trace/irq_vectors.h>
60
61 unsigned int num_processors;
62
63 unsigned disabled_cpus __cpuinitdata;
64
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_physical_apicid = -1U;
67
68 /*
69 * The highest APIC ID seen during enumeration.
70 */
71 unsigned int max_physical_apicid;
72
73 /*
74 * Bitmask of physically existing CPUs:
75 */
76 physid_mask_t phys_cpu_present_map;
77
78 /*
79 * Map cpu index to physical APIC ID
80 */
81 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
82 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
83 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
84 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
85
86 #ifdef CONFIG_X86_32
87
88 /*
89 * On x86_32, the mapping between cpu and logical apicid may vary
90 * depending on apic in use. The following early percpu variable is
91 * used for the mapping. This is where the behaviors of x86_64 and 32
92 * actually diverge. Let's keep it ugly for now.
93 */
94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
95
96 /* Local APIC was disabled by the BIOS and enabled by the kernel */
97 static int enabled_via_apicbase;
98
99 /*
100 * Handle interrupt mode configuration register (IMCR).
101 * This register controls whether the interrupt signals
102 * that reach the BSP come from the master PIC or from the
103 * local APIC. Before entering Symmetric I/O Mode, either
104 * the BIOS or the operating system must switch out of
105 * PIC Mode by changing the IMCR.
106 */
107 static inline void imcr_pic_to_apic(void)
108 {
109 /* select IMCR register */
110 outb(0x70, 0x22);
111 /* NMI and 8259 INTR go through APIC */
112 outb(0x01, 0x23);
113 }
114
115 static inline void imcr_apic_to_pic(void)
116 {
117 /* select IMCR register */
118 outb(0x70, 0x22);
119 /* NMI and 8259 INTR go directly to BSP */
120 outb(0x00, 0x23);
121 }
122 #endif
123
124 /*
125 * Knob to control our willingness to enable the local APIC.
126 *
127 * +1=force-enable
128 */
129 static int force_enable_local_apic __initdata;
130 /*
131 * APIC command line parameters
132 */
133 static int __init parse_lapic(char *arg)
134 {
135 if (config_enabled(CONFIG_X86_32) && !arg)
136 force_enable_local_apic = 1;
137 else if (arg && !strncmp(arg, "notscdeadline", 13))
138 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
139 return 0;
140 }
141 early_param("lapic", parse_lapic);
142
143 #ifdef CONFIG_X86_64
144 static int apic_calibrate_pmtmr __initdata;
145 static __init int setup_apicpmtimer(char *s)
146 {
147 apic_calibrate_pmtmr = 1;
148 notsc_setup(NULL);
149 return 0;
150 }
151 __setup("apicpmtimer", setup_apicpmtimer);
152 #endif
153
154 int x2apic_mode;
155 #ifdef CONFIG_X86_X2APIC
156 /* x2apic enabled before OS handover */
157 int x2apic_preenabled;
158 static int x2apic_disabled;
159 static int nox2apic;
160 static __init int setup_nox2apic(char *str)
161 {
162 if (x2apic_enabled()) {
163 int apicid = native_apic_msr_read(APIC_ID);
164
165 if (apicid >= 255) {
166 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
167 apicid);
168 return 0;
169 }
170
171 pr_warning("x2apic already enabled. will disable it\n");
172 } else
173 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
174
175 nox2apic = 1;
176
177 return 0;
178 }
179 early_param("nox2apic", setup_nox2apic);
180 #endif
181
182 unsigned long mp_lapic_addr;
183 int disable_apic;
184 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
185 static int disable_apic_timer __initdata;
186 /* Local APIC timer works in C2 */
187 int local_apic_timer_c2_ok;
188 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
189
190 int first_system_vector = 0xfe;
191
192 /*
193 * Debug level, exported for io_apic.c
194 */
195 unsigned int apic_verbosity;
196
197 int pic_mode;
198
199 /* Have we found an MP table */
200 int smp_found_config;
201
202 static struct resource lapic_resource = {
203 .name = "Local APIC",
204 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
205 };
206
207 unsigned int lapic_timer_frequency = 0;
208
209 static void apic_pm_activate(void);
210
211 static unsigned long apic_phys;
212
213 /*
214 * Get the LAPIC version
215 */
216 static inline int lapic_get_version(void)
217 {
218 return GET_APIC_VERSION(apic_read(APIC_LVR));
219 }
220
221 /*
222 * Check, if the APIC is integrated or a separate chip
223 */
224 static inline int lapic_is_integrated(void)
225 {
226 #ifdef CONFIG_X86_64
227 return 1;
228 #else
229 return APIC_INTEGRATED(lapic_get_version());
230 #endif
231 }
232
233 /*
234 * Check, whether this is a modern or a first generation APIC
235 */
236 static int modern_apic(void)
237 {
238 /* AMD systems use old APIC versions, so check the CPU */
239 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
240 boot_cpu_data.x86 >= 0xf)
241 return 1;
242 return lapic_get_version() >= 0x14;
243 }
244
245 /*
246 * right after this call apic become NOOP driven
247 * so apic->write/read doesn't do anything
248 */
249 static void __init apic_disable(void)
250 {
251 pr_info("APIC: switched to apic NOOP\n");
252 apic = &apic_noop;
253 }
254
255 void native_apic_wait_icr_idle(void)
256 {
257 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
258 cpu_relax();
259 }
260
261 u32 native_safe_apic_wait_icr_idle(void)
262 {
263 u32 send_status;
264 int timeout;
265
266 timeout = 0;
267 do {
268 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
269 if (!send_status)
270 break;
271 inc_irq_stat(icr_read_retry_count);
272 udelay(100);
273 } while (timeout++ < 1000);
274
275 return send_status;
276 }
277
278 void native_apic_icr_write(u32 low, u32 id)
279 {
280 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
281 apic_write(APIC_ICR, low);
282 }
283
284 u64 native_apic_icr_read(void)
285 {
286 u32 icr1, icr2;
287
288 icr2 = apic_read(APIC_ICR2);
289 icr1 = apic_read(APIC_ICR);
290
291 return icr1 | ((u64)icr2 << 32);
292 }
293
294 #ifdef CONFIG_X86_32
295 /**
296 * get_physical_broadcast - Get number of physical broadcast IDs
297 */
298 int get_physical_broadcast(void)
299 {
300 return modern_apic() ? 0xff : 0xf;
301 }
302 #endif
303
304 /**
305 * lapic_get_maxlvt - get the maximum number of local vector table entries
306 */
307 int lapic_get_maxlvt(void)
308 {
309 unsigned int v;
310
311 v = apic_read(APIC_LVR);
312 /*
313 * - we always have APIC integrated on 64bit mode
314 * - 82489DXs do not report # of LVT entries
315 */
316 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
317 }
318
319 /*
320 * Local APIC timer
321 */
322
323 /* Clock divisor */
324 #define APIC_DIVISOR 16
325 #define TSC_DIVISOR 32
326
327 /*
328 * This function sets up the local APIC timer, with a timeout of
329 * 'clocks' APIC bus clock. During calibration we actually call
330 * this function twice on the boot CPU, once with a bogus timeout
331 * value, second time for real. The other (noncalibrating) CPUs
332 * call this function only once, with the real, calibrated value.
333 *
334 * We do reads before writes even if unnecessary, to get around the
335 * P5 APIC double write bug.
336 */
337 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
338 {
339 unsigned int lvtt_value, tmp_value;
340
341 lvtt_value = LOCAL_TIMER_VECTOR;
342 if (!oneshot)
343 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
344 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
345 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
346
347 if (!lapic_is_integrated())
348 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
349
350 if (!irqen)
351 lvtt_value |= APIC_LVT_MASKED;
352
353 apic_write(APIC_LVTT, lvtt_value);
354
355 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
357 return;
358 }
359
360 /*
361 * Divide PICLK by 16
362 */
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366 APIC_TDR_DIV_16);
367
368 if (!oneshot)
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370 }
371
372 /*
373 * Setup extended LVT, AMD specific
374 *
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
379 * available.
380 *
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
385 *
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
390 */
391
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 {
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
399 }
400
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 {
403 unsigned int rsvd, vector;
404
405 if (offset >= APIC_EILVT_NR_MAX)
406 return ~0;
407
408 rsvd = atomic_read(&eilvt_offsets[offset]);
409 do {
410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
411 if (vector && !eilvt_entry_is_changeable(vector, new))
412 /* may not change if vectors are different */
413 return rsvd;
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
416
417 rsvd &= ~APIC_EILVT_MASKED;
418 if (rsvd && rsvd != vector)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
420 offset, rsvd);
421
422 return new;
423 }
424
425 /*
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
429 */
430
431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 {
433 unsigned long reg = APIC_EILVTn(offset);
434 unsigned int new, old, reserved;
435
436 new = (mask << 16) | (msg_type << 8) | vector;
437 old = apic_read(reg);
438 reserved = reserve_eilvt_offset(offset, new);
439
440 if (reserved != new) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg, offset, new, reserved);
445 return -EINVAL;
446 }
447
448 if (!eilvt_entry_is_changeable(old, new)) {
449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg, offset, new, old);
453 return -EBUSY;
454 }
455
456 apic_write(reg, new);
457
458 return 0;
459 }
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
461
462 /*
463 * Program the next event, relative to now
464 */
465 static int lapic_next_event(unsigned long delta,
466 struct clock_event_device *evt)
467 {
468 apic_write(APIC_TMICT, delta);
469 return 0;
470 }
471
472 static int lapic_next_deadline(unsigned long delta,
473 struct clock_event_device *evt)
474 {
475 u64 tsc;
476
477 rdtscll(tsc);
478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
479 return 0;
480 }
481
482 /*
483 * Setup the lapic timer in periodic or oneshot mode
484 */
485 static void lapic_timer_setup(enum clock_event_mode mode,
486 struct clock_event_device *evt)
487 {
488 unsigned long flags;
489 unsigned int v;
490
491 /* Lapic used as dummy for broadcast ? */
492 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
493 return;
494
495 local_irq_save(flags);
496
497 switch (mode) {
498 case CLOCK_EVT_MODE_PERIODIC:
499 case CLOCK_EVT_MODE_ONESHOT:
500 __setup_APIC_LVTT(lapic_timer_frequency,
501 mode != CLOCK_EVT_MODE_PERIODIC, 1);
502 break;
503 case CLOCK_EVT_MODE_UNUSED:
504 case CLOCK_EVT_MODE_SHUTDOWN:
505 v = apic_read(APIC_LVTT);
506 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
507 apic_write(APIC_LVTT, v);
508 apic_write(APIC_TMICT, 0);
509 break;
510 case CLOCK_EVT_MODE_RESUME:
511 /* Nothing to do here */
512 break;
513 }
514
515 local_irq_restore(flags);
516 }
517
518 /*
519 * Local APIC timer broadcast function
520 */
521 static void lapic_timer_broadcast(const struct cpumask *mask)
522 {
523 #ifdef CONFIG_SMP
524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
525 #endif
526 }
527
528
529 /*
530 * The local apic timer can be used for any function which is CPU local.
531 */
532 static struct clock_event_device lapic_clockevent = {
533 .name = "lapic",
534 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
535 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
536 .shift = 32,
537 .set_mode = lapic_timer_setup,
538 .set_next_event = lapic_next_event,
539 .broadcast = lapic_timer_broadcast,
540 .rating = 100,
541 .irq = -1,
542 };
543 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
544
545 /*
546 * Setup the local APIC timer for this CPU. Copy the initialized values
547 * of the boot CPU and register the clock event in the framework.
548 */
549 static void __cpuinit setup_APIC_timer(void)
550 {
551 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
552
553 if (this_cpu_has(X86_FEATURE_ARAT)) {
554 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
555 /* Make LAPIC timer preferrable over percpu HPET */
556 lapic_clockevent.rating = 150;
557 }
558
559 memcpy(levt, &lapic_clockevent, sizeof(*levt));
560 levt->cpumask = cpumask_of(smp_processor_id());
561
562 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
563 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
564 CLOCK_EVT_FEAT_DUMMY);
565 levt->set_next_event = lapic_next_deadline;
566 clockevents_config_and_register(levt,
567 (tsc_khz / TSC_DIVISOR) * 1000,
568 0xF, ~0UL);
569 } else
570 clockevents_register_device(levt);
571 }
572
573 /*
574 * In this functions we calibrate APIC bus clocks to the external timer.
575 *
576 * We want to do the calibration only once since we want to have local timer
577 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
578 * frequency.
579 *
580 * This was previously done by reading the PIT/HPET and waiting for a wrap
581 * around to find out, that a tick has elapsed. I have a box, where the PIT
582 * readout is broken, so it never gets out of the wait loop again. This was
583 * also reported by others.
584 *
585 * Monitoring the jiffies value is inaccurate and the clockevents
586 * infrastructure allows us to do a simple substitution of the interrupt
587 * handler.
588 *
589 * The calibration routine also uses the pm_timer when possible, as the PIT
590 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
591 * back to normal later in the boot process).
592 */
593
594 #define LAPIC_CAL_LOOPS (HZ/10)
595
596 static __initdata int lapic_cal_loops = -1;
597 static __initdata long lapic_cal_t1, lapic_cal_t2;
598 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
599 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
600 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
601
602 /*
603 * Temporary interrupt handler.
604 */
605 static void __init lapic_cal_handler(struct clock_event_device *dev)
606 {
607 unsigned long long tsc = 0;
608 long tapic = apic_read(APIC_TMCCT);
609 unsigned long pm = acpi_pm_read_early();
610
611 if (cpu_has_tsc)
612 rdtscll(tsc);
613
614 switch (lapic_cal_loops++) {
615 case 0:
616 lapic_cal_t1 = tapic;
617 lapic_cal_tsc1 = tsc;
618 lapic_cal_pm1 = pm;
619 lapic_cal_j1 = jiffies;
620 break;
621
622 case LAPIC_CAL_LOOPS:
623 lapic_cal_t2 = tapic;
624 lapic_cal_tsc2 = tsc;
625 if (pm < lapic_cal_pm1)
626 pm += ACPI_PM_OVRRUN;
627 lapic_cal_pm2 = pm;
628 lapic_cal_j2 = jiffies;
629 break;
630 }
631 }
632
633 static int __init
634 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
635 {
636 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
637 const long pm_thresh = pm_100ms / 100;
638 unsigned long mult;
639 u64 res;
640
641 #ifndef CONFIG_X86_PM_TIMER
642 return -1;
643 #endif
644
645 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
646
647 /* Check, if the PM timer is available */
648 if (!deltapm)
649 return -1;
650
651 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
652
653 if (deltapm > (pm_100ms - pm_thresh) &&
654 deltapm < (pm_100ms + pm_thresh)) {
655 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
656 return 0;
657 }
658
659 res = (((u64)deltapm) * mult) >> 22;
660 do_div(res, 1000000);
661 pr_warning("APIC calibration not consistent "
662 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
663
664 /* Correct the lapic counter value */
665 res = (((u64)(*delta)) * pm_100ms);
666 do_div(res, deltapm);
667 pr_info("APIC delta adjusted to PM-Timer: "
668 "%lu (%ld)\n", (unsigned long)res, *delta);
669 *delta = (long)res;
670
671 /* Correct the tsc counter value */
672 if (cpu_has_tsc) {
673 res = (((u64)(*deltatsc)) * pm_100ms);
674 do_div(res, deltapm);
675 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
676 "PM-Timer: %lu (%ld)\n",
677 (unsigned long)res, *deltatsc);
678 *deltatsc = (long)res;
679 }
680
681 return 0;
682 }
683
684 static int __init calibrate_APIC_clock(void)
685 {
686 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
687 void (*real_handler)(struct clock_event_device *dev);
688 unsigned long deltaj;
689 long delta, deltatsc;
690 int pm_referenced = 0;
691
692 /**
693 * check if lapic timer has already been calibrated by platform
694 * specific routine, such as tsc calibration code. if so, we just fill
695 * in the clockevent structure and return.
696 */
697
698 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
699 return 0;
700 } else if (lapic_timer_frequency) {
701 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
702 lapic_timer_frequency);
703 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
704 TICK_NSEC, lapic_clockevent.shift);
705 lapic_clockevent.max_delta_ns =
706 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
707 lapic_clockevent.min_delta_ns =
708 clockevent_delta2ns(0xF, &lapic_clockevent);
709 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
710 return 0;
711 }
712
713 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
714 "calibrating APIC timer ...\n");
715
716 local_irq_disable();
717
718 /* Replace the global interrupt handler */
719 real_handler = global_clock_event->event_handler;
720 global_clock_event->event_handler = lapic_cal_handler;
721
722 /*
723 * Setup the APIC counter to maximum. There is no way the lapic
724 * can underflow in the 100ms detection time frame
725 */
726 __setup_APIC_LVTT(0xffffffff, 0, 0);
727
728 /* Let the interrupts run */
729 local_irq_enable();
730
731 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
732 cpu_relax();
733
734 local_irq_disable();
735
736 /* Restore the real event handler */
737 global_clock_event->event_handler = real_handler;
738
739 /* Build delta t1-t2 as apic timer counts down */
740 delta = lapic_cal_t1 - lapic_cal_t2;
741 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
742
743 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
744
745 /* we trust the PM based calibration if possible */
746 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
747 &delta, &deltatsc);
748
749 /* Calculate the scaled math multiplication factor */
750 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
751 lapic_clockevent.shift);
752 lapic_clockevent.max_delta_ns =
753 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
754 lapic_clockevent.min_delta_ns =
755 clockevent_delta2ns(0xF, &lapic_clockevent);
756
757 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
758
759 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
760 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
761 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
762 lapic_timer_frequency);
763
764 if (cpu_has_tsc) {
765 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
766 "%ld.%04ld MHz.\n",
767 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
768 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
769 }
770
771 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
772 "%u.%04u MHz.\n",
773 lapic_timer_frequency / (1000000 / HZ),
774 lapic_timer_frequency % (1000000 / HZ));
775
776 /*
777 * Do a sanity check on the APIC calibration result
778 */
779 if (lapic_timer_frequency < (1000000 / HZ)) {
780 local_irq_enable();
781 pr_warning("APIC frequency too slow, disabling apic timer\n");
782 return -1;
783 }
784
785 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
786
787 /*
788 * PM timer calibration failed or not turned on
789 * so lets try APIC timer based calibration
790 */
791 if (!pm_referenced) {
792 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
793
794 /*
795 * Setup the apic timer manually
796 */
797 levt->event_handler = lapic_cal_handler;
798 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
799 lapic_cal_loops = -1;
800
801 /* Let the interrupts run */
802 local_irq_enable();
803
804 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
805 cpu_relax();
806
807 /* Stop the lapic timer */
808 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
809
810 /* Jiffies delta */
811 deltaj = lapic_cal_j2 - lapic_cal_j1;
812 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
813
814 /* Check, if the jiffies result is consistent */
815 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
816 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
817 else
818 levt->features |= CLOCK_EVT_FEAT_DUMMY;
819 } else
820 local_irq_enable();
821
822 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
823 pr_warning("APIC timer disabled due to verification failure\n");
824 return -1;
825 }
826
827 return 0;
828 }
829
830 /*
831 * Setup the boot APIC
832 *
833 * Calibrate and verify the result.
834 */
835 void __init setup_boot_APIC_clock(void)
836 {
837 /*
838 * The local apic timer can be disabled via the kernel
839 * commandline or from the CPU detection code. Register the lapic
840 * timer as a dummy clock event source on SMP systems, so the
841 * broadcast mechanism is used. On UP systems simply ignore it.
842 */
843 if (disable_apic_timer) {
844 pr_info("Disabling APIC timer\n");
845 /* No broadcast on UP ! */
846 if (num_possible_cpus() > 1) {
847 lapic_clockevent.mult = 1;
848 setup_APIC_timer();
849 }
850 return;
851 }
852
853 if (calibrate_APIC_clock()) {
854 /* No broadcast on UP ! */
855 if (num_possible_cpus() > 1)
856 setup_APIC_timer();
857 return;
858 }
859
860 /*
861 * If nmi_watchdog is set to IO_APIC, we need the
862 * PIT/HPET going. Otherwise register lapic as a dummy
863 * device.
864 */
865 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
866
867 /* Setup the lapic or request the broadcast */
868 setup_APIC_timer();
869 }
870
871 void __cpuinit setup_secondary_APIC_clock(void)
872 {
873 setup_APIC_timer();
874 }
875
876 /*
877 * The guts of the apic timer interrupt
878 */
879 static void local_apic_timer_interrupt(void)
880 {
881 int cpu = smp_processor_id();
882 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
883
884 /*
885 * Normally we should not be here till LAPIC has been initialized but
886 * in some cases like kdump, its possible that there is a pending LAPIC
887 * timer interrupt from previous kernel's context and is delivered in
888 * new kernel the moment interrupts are enabled.
889 *
890 * Interrupts are enabled early and LAPIC is setup much later, hence
891 * its possible that when we get here evt->event_handler is NULL.
892 * Check for event_handler being NULL and discard the interrupt as
893 * spurious.
894 */
895 if (!evt->event_handler) {
896 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
897 /* Switch it off */
898 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
899 return;
900 }
901
902 /*
903 * the NMI deadlock-detector uses this.
904 */
905 inc_irq_stat(apic_timer_irqs);
906
907 evt->event_handler(evt);
908 }
909
910 /*
911 * Local APIC timer interrupt. This is the most natural way for doing
912 * local interrupts, but local timer interrupts can be emulated by
913 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
914 *
915 * [ if a single-CPU system runs an SMP kernel then we call the local
916 * interrupt as well. Thus we cannot inline the local irq ... ]
917 */
918 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
919 {
920 struct pt_regs *old_regs = set_irq_regs(regs);
921
922 /*
923 * NOTE! We'd better ACK the irq immediately,
924 * because timer handling can be slow.
925 *
926 * update_process_times() expects us to have done irq_enter().
927 * Besides, if we don't timer interrupts ignore the global
928 * interrupt lock, which is the WrongThing (tm) to do.
929 */
930 entering_ack_irq();
931 local_apic_timer_interrupt();
932 exiting_irq();
933
934 set_irq_regs(old_regs);
935 }
936
937 void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
938 {
939 struct pt_regs *old_regs = set_irq_regs(regs);
940
941 /*
942 * NOTE! We'd better ACK the irq immediately,
943 * because timer handling can be slow.
944 *
945 * update_process_times() expects us to have done irq_enter().
946 * Besides, if we don't timer interrupts ignore the global
947 * interrupt lock, which is the WrongThing (tm) to do.
948 */
949 entering_ack_irq();
950 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
951 local_apic_timer_interrupt();
952 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
953 exiting_irq();
954
955 set_irq_regs(old_regs);
956 }
957
958 int setup_profiling_timer(unsigned int multiplier)
959 {
960 return -EINVAL;
961 }
962
963 /*
964 * Local APIC start and shutdown
965 */
966
967 /**
968 * clear_local_APIC - shutdown the local APIC
969 *
970 * This is called, when a CPU is disabled and before rebooting, so the state of
971 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
972 * leftovers during boot.
973 */
974 void clear_local_APIC(void)
975 {
976 int maxlvt;
977 u32 v;
978
979 /* APIC hasn't been mapped yet */
980 if (!x2apic_mode && !apic_phys)
981 return;
982
983 maxlvt = lapic_get_maxlvt();
984 /*
985 * Masking an LVT entry can trigger a local APIC error
986 * if the vector is zero. Mask LVTERR first to prevent this.
987 */
988 if (maxlvt >= 3) {
989 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
990 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
991 }
992 /*
993 * Careful: we have to set masks only first to deassert
994 * any level-triggered sources.
995 */
996 v = apic_read(APIC_LVTT);
997 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
998 v = apic_read(APIC_LVT0);
999 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1000 v = apic_read(APIC_LVT1);
1001 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1002 if (maxlvt >= 4) {
1003 v = apic_read(APIC_LVTPC);
1004 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1005 }
1006
1007 /* lets not touch this if we didn't frob it */
1008 #ifdef CONFIG_X86_THERMAL_VECTOR
1009 if (maxlvt >= 5) {
1010 v = apic_read(APIC_LVTTHMR);
1011 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1012 }
1013 #endif
1014 #ifdef CONFIG_X86_MCE_INTEL
1015 if (maxlvt >= 6) {
1016 v = apic_read(APIC_LVTCMCI);
1017 if (!(v & APIC_LVT_MASKED))
1018 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1019 }
1020 #endif
1021
1022 /*
1023 * Clean APIC state for other OSs:
1024 */
1025 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1026 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1027 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1028 if (maxlvt >= 3)
1029 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1030 if (maxlvt >= 4)
1031 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1032
1033 /* Integrated APIC (!82489DX) ? */
1034 if (lapic_is_integrated()) {
1035 if (maxlvt > 3)
1036 /* Clear ESR due to Pentium errata 3AP and 11AP */
1037 apic_write(APIC_ESR, 0);
1038 apic_read(APIC_ESR);
1039 }
1040 }
1041
1042 /**
1043 * disable_local_APIC - clear and disable the local APIC
1044 */
1045 void disable_local_APIC(void)
1046 {
1047 unsigned int value;
1048
1049 /* APIC hasn't been mapped yet */
1050 if (!x2apic_mode && !apic_phys)
1051 return;
1052
1053 clear_local_APIC();
1054
1055 /*
1056 * Disable APIC (implies clearing of registers
1057 * for 82489DX!).
1058 */
1059 value = apic_read(APIC_SPIV);
1060 value &= ~APIC_SPIV_APIC_ENABLED;
1061 apic_write(APIC_SPIV, value);
1062
1063 #ifdef CONFIG_X86_32
1064 /*
1065 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1066 * restore the disabled state.
1067 */
1068 if (enabled_via_apicbase) {
1069 unsigned int l, h;
1070
1071 rdmsr(MSR_IA32_APICBASE, l, h);
1072 l &= ~MSR_IA32_APICBASE_ENABLE;
1073 wrmsr(MSR_IA32_APICBASE, l, h);
1074 }
1075 #endif
1076 }
1077
1078 /*
1079 * If Linux enabled the LAPIC against the BIOS default disable it down before
1080 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1081 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1082 * for the case where Linux didn't enable the LAPIC.
1083 */
1084 void lapic_shutdown(void)
1085 {
1086 unsigned long flags;
1087
1088 if (!cpu_has_apic && !apic_from_smp_config())
1089 return;
1090
1091 local_irq_save(flags);
1092
1093 #ifdef CONFIG_X86_32
1094 if (!enabled_via_apicbase)
1095 clear_local_APIC();
1096 else
1097 #endif
1098 disable_local_APIC();
1099
1100
1101 local_irq_restore(flags);
1102 }
1103
1104 /*
1105 * This is to verify that we're looking at a real local APIC.
1106 * Check these against your board if the CPUs aren't getting
1107 * started for no apparent reason.
1108 */
1109 int __init verify_local_APIC(void)
1110 {
1111 unsigned int reg0, reg1;
1112
1113 /*
1114 * The version register is read-only in a real APIC.
1115 */
1116 reg0 = apic_read(APIC_LVR);
1117 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1118 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1119 reg1 = apic_read(APIC_LVR);
1120 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1121
1122 /*
1123 * The two version reads above should print the same
1124 * numbers. If the second one is different, then we
1125 * poke at a non-APIC.
1126 */
1127 if (reg1 != reg0)
1128 return 0;
1129
1130 /*
1131 * Check if the version looks reasonably.
1132 */
1133 reg1 = GET_APIC_VERSION(reg0);
1134 if (reg1 == 0x00 || reg1 == 0xff)
1135 return 0;
1136 reg1 = lapic_get_maxlvt();
1137 if (reg1 < 0x02 || reg1 == 0xff)
1138 return 0;
1139
1140 /*
1141 * The ID register is read/write in a real APIC.
1142 */
1143 reg0 = apic_read(APIC_ID);
1144 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1145 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1146 reg1 = apic_read(APIC_ID);
1147 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1148 apic_write(APIC_ID, reg0);
1149 if (reg1 != (reg0 ^ apic->apic_id_mask))
1150 return 0;
1151
1152 /*
1153 * The next two are just to see if we have sane values.
1154 * They're only really relevant if we're in Virtual Wire
1155 * compatibility mode, but most boxes are anymore.
1156 */
1157 reg0 = apic_read(APIC_LVT0);
1158 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1159 reg1 = apic_read(APIC_LVT1);
1160 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1161
1162 return 1;
1163 }
1164
1165 /**
1166 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1167 */
1168 void __init sync_Arb_IDs(void)
1169 {
1170 /*
1171 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1172 * needed on AMD.
1173 */
1174 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1175 return;
1176
1177 /*
1178 * Wait for idle.
1179 */
1180 apic_wait_icr_idle();
1181
1182 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1183 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1184 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1185 }
1186
1187 /*
1188 * An initial setup of the virtual wire mode.
1189 */
1190 void __init init_bsp_APIC(void)
1191 {
1192 unsigned int value;
1193
1194 /*
1195 * Don't do the setup now if we have a SMP BIOS as the
1196 * through-I/O-APIC virtual wire mode might be active.
1197 */
1198 if (smp_found_config || !cpu_has_apic)
1199 return;
1200
1201 /*
1202 * Do not trust the local APIC being empty at bootup.
1203 */
1204 clear_local_APIC();
1205
1206 /*
1207 * Enable APIC.
1208 */
1209 value = apic_read(APIC_SPIV);
1210 value &= ~APIC_VECTOR_MASK;
1211 value |= APIC_SPIV_APIC_ENABLED;
1212
1213 #ifdef CONFIG_X86_32
1214 /* This bit is reserved on P4/Xeon and should be cleared */
1215 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1216 (boot_cpu_data.x86 == 15))
1217 value &= ~APIC_SPIV_FOCUS_DISABLED;
1218 else
1219 #endif
1220 value |= APIC_SPIV_FOCUS_DISABLED;
1221 value |= SPURIOUS_APIC_VECTOR;
1222 apic_write(APIC_SPIV, value);
1223
1224 /*
1225 * Set up the virtual wire mode.
1226 */
1227 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1228 value = APIC_DM_NMI;
1229 if (!lapic_is_integrated()) /* 82489DX */
1230 value |= APIC_LVT_LEVEL_TRIGGER;
1231 apic_write(APIC_LVT1, value);
1232 }
1233
1234 static void __cpuinit lapic_setup_esr(void)
1235 {
1236 unsigned int oldvalue, value, maxlvt;
1237
1238 if (!lapic_is_integrated()) {
1239 pr_info("No ESR for 82489DX.\n");
1240 return;
1241 }
1242
1243 if (apic->disable_esr) {
1244 /*
1245 * Something untraceable is creating bad interrupts on
1246 * secondary quads ... for the moment, just leave the
1247 * ESR disabled - we can't do anything useful with the
1248 * errors anyway - mbligh
1249 */
1250 pr_info("Leaving ESR disabled.\n");
1251 return;
1252 }
1253
1254 maxlvt = lapic_get_maxlvt();
1255 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1256 apic_write(APIC_ESR, 0);
1257 oldvalue = apic_read(APIC_ESR);
1258
1259 /* enables sending errors */
1260 value = ERROR_APIC_VECTOR;
1261 apic_write(APIC_LVTERR, value);
1262
1263 /*
1264 * spec says clear errors after enabling vector.
1265 */
1266 if (maxlvt > 3)
1267 apic_write(APIC_ESR, 0);
1268 value = apic_read(APIC_ESR);
1269 if (value != oldvalue)
1270 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1271 "vector: 0x%08x after: 0x%08x\n",
1272 oldvalue, value);
1273 }
1274
1275 /**
1276 * setup_local_APIC - setup the local APIC
1277 *
1278 * Used to setup local APIC while initializing BSP or bringin up APs.
1279 * Always called with preemption disabled.
1280 */
1281 void __cpuinit setup_local_APIC(void)
1282 {
1283 int cpu = smp_processor_id();
1284 unsigned int value, queued;
1285 int i, j, acked = 0;
1286 unsigned long long tsc = 0, ntsc;
1287 long long max_loops = cpu_khz;
1288
1289 if (cpu_has_tsc)
1290 rdtscll(tsc);
1291
1292 if (disable_apic) {
1293 disable_ioapic_support();
1294 return;
1295 }
1296
1297 #ifdef CONFIG_X86_32
1298 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1299 if (lapic_is_integrated() && apic->disable_esr) {
1300 apic_write(APIC_ESR, 0);
1301 apic_write(APIC_ESR, 0);
1302 apic_write(APIC_ESR, 0);
1303 apic_write(APIC_ESR, 0);
1304 }
1305 #endif
1306 perf_events_lapic_init();
1307
1308 /*
1309 * Double-check whether this APIC is really registered.
1310 * This is meaningless in clustered apic mode, so we skip it.
1311 */
1312 BUG_ON(!apic->apic_id_registered());
1313
1314 /*
1315 * Intel recommends to set DFR, LDR and TPR before enabling
1316 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1317 * document number 292116). So here it goes...
1318 */
1319 apic->init_apic_ldr();
1320
1321 #ifdef CONFIG_X86_32
1322 /*
1323 * APIC LDR is initialized. If logical_apicid mapping was
1324 * initialized during get_smp_config(), make sure it matches the
1325 * actual value.
1326 */
1327 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1328 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1329 /* always use the value from LDR */
1330 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1331 logical_smp_processor_id();
1332
1333 /*
1334 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1335 * node mapping during NUMA init. Now that logical apicid is
1336 * guaranteed to be known, give it another chance. This is already
1337 * a bit too late - percpu allocation has already happened without
1338 * proper NUMA affinity.
1339 */
1340 if (apic->x86_32_numa_cpu_node)
1341 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1342 apic->x86_32_numa_cpu_node(cpu));
1343 #endif
1344
1345 /*
1346 * Set Task Priority to 'accept all'. We never change this
1347 * later on.
1348 */
1349 value = apic_read(APIC_TASKPRI);
1350 value &= ~APIC_TPRI_MASK;
1351 apic_write(APIC_TASKPRI, value);
1352
1353 /*
1354 * After a crash, we no longer service the interrupts and a pending
1355 * interrupt from previous kernel might still have ISR bit set.
1356 *
1357 * Most probably by now CPU has serviced that pending interrupt and
1358 * it might not have done the ack_APIC_irq() because it thought,
1359 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1360 * does not clear the ISR bit and cpu thinks it has already serivced
1361 * the interrupt. Hence a vector might get locked. It was noticed
1362 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1363 */
1364 do {
1365 queued = 0;
1366 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1367 queued |= apic_read(APIC_IRR + i*0x10);
1368
1369 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1370 value = apic_read(APIC_ISR + i*0x10);
1371 for (j = 31; j >= 0; j--) {
1372 if (value & (1<<j)) {
1373 ack_APIC_irq();
1374 acked++;
1375 }
1376 }
1377 }
1378 if (acked > 256) {
1379 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1380 acked);
1381 break;
1382 }
1383 if (queued) {
1384 if (cpu_has_tsc) {
1385 rdtscll(ntsc);
1386 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1387 } else
1388 max_loops--;
1389 }
1390 } while (queued && max_loops > 0);
1391 WARN_ON(max_loops <= 0);
1392
1393 /*
1394 * Now that we are all set up, enable the APIC
1395 */
1396 value = apic_read(APIC_SPIV);
1397 value &= ~APIC_VECTOR_MASK;
1398 /*
1399 * Enable APIC
1400 */
1401 value |= APIC_SPIV_APIC_ENABLED;
1402
1403 #ifdef CONFIG_X86_32
1404 /*
1405 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1406 * certain networking cards. If high frequency interrupts are
1407 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1408 * entry is masked/unmasked at a high rate as well then sooner or
1409 * later IOAPIC line gets 'stuck', no more interrupts are received
1410 * from the device. If focus CPU is disabled then the hang goes
1411 * away, oh well :-(
1412 *
1413 * [ This bug can be reproduced easily with a level-triggered
1414 * PCI Ne2000 networking cards and PII/PIII processors, dual
1415 * BX chipset. ]
1416 */
1417 /*
1418 * Actually disabling the focus CPU check just makes the hang less
1419 * frequent as it makes the interrupt distributon model be more
1420 * like LRU than MRU (the short-term load is more even across CPUs).
1421 * See also the comment in end_level_ioapic_irq(). --macro
1422 */
1423
1424 /*
1425 * - enable focus processor (bit==0)
1426 * - 64bit mode always use processor focus
1427 * so no need to set it
1428 */
1429 value &= ~APIC_SPIV_FOCUS_DISABLED;
1430 #endif
1431
1432 /*
1433 * Set spurious IRQ vector
1434 */
1435 value |= SPURIOUS_APIC_VECTOR;
1436 apic_write(APIC_SPIV, value);
1437
1438 /*
1439 * Set up LVT0, LVT1:
1440 *
1441 * set up through-local-APIC on the BP's LINT0. This is not
1442 * strictly necessary in pure symmetric-IO mode, but sometimes
1443 * we delegate interrupts to the 8259A.
1444 */
1445 /*
1446 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1447 */
1448 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1449 if (!cpu && (pic_mode || !value)) {
1450 value = APIC_DM_EXTINT;
1451 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1452 } else {
1453 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1454 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1455 }
1456 apic_write(APIC_LVT0, value);
1457
1458 /*
1459 * only the BP should see the LINT1 NMI signal, obviously.
1460 */
1461 if (!cpu)
1462 value = APIC_DM_NMI;
1463 else
1464 value = APIC_DM_NMI | APIC_LVT_MASKED;
1465 if (!lapic_is_integrated()) /* 82489DX */
1466 value |= APIC_LVT_LEVEL_TRIGGER;
1467 apic_write(APIC_LVT1, value);
1468
1469 #ifdef CONFIG_X86_MCE_INTEL
1470 /* Recheck CMCI information after local APIC is up on CPU #0 */
1471 if (!cpu)
1472 cmci_recheck();
1473 #endif
1474 }
1475
1476 void __cpuinit end_local_APIC_setup(void)
1477 {
1478 lapic_setup_esr();
1479
1480 #ifdef CONFIG_X86_32
1481 {
1482 unsigned int value;
1483 /* Disable the local apic timer */
1484 value = apic_read(APIC_LVTT);
1485 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1486 apic_write(APIC_LVTT, value);
1487 }
1488 #endif
1489
1490 apic_pm_activate();
1491 }
1492
1493 void __init bsp_end_local_APIC_setup(void)
1494 {
1495 end_local_APIC_setup();
1496
1497 /*
1498 * Now that local APIC setup is completed for BP, configure the fault
1499 * handling for interrupt remapping.
1500 */
1501 irq_remap_enable_fault_handling();
1502
1503 }
1504
1505 #ifdef CONFIG_X86_X2APIC
1506 /*
1507 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1508 */
1509 static inline void __disable_x2apic(u64 msr)
1510 {
1511 wrmsrl(MSR_IA32_APICBASE,
1512 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1513 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1514 }
1515
1516 static __init void disable_x2apic(void)
1517 {
1518 u64 msr;
1519
1520 if (!cpu_has_x2apic)
1521 return;
1522
1523 rdmsrl(MSR_IA32_APICBASE, msr);
1524 if (msr & X2APIC_ENABLE) {
1525 u32 x2apic_id = read_apic_id();
1526
1527 if (x2apic_id >= 255)
1528 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1529
1530 pr_info("Disabling x2apic\n");
1531 __disable_x2apic(msr);
1532
1533 if (nox2apic) {
1534 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC);
1535 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1536 }
1537
1538 x2apic_disabled = 1;
1539 x2apic_mode = 0;
1540
1541 register_lapic_address(mp_lapic_addr);
1542 }
1543 }
1544
1545 void check_x2apic(void)
1546 {
1547 if (x2apic_enabled()) {
1548 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1549 x2apic_preenabled = x2apic_mode = 1;
1550 }
1551 }
1552
1553 void enable_x2apic(void)
1554 {
1555 u64 msr;
1556
1557 rdmsrl(MSR_IA32_APICBASE, msr);
1558 if (x2apic_disabled) {
1559 __disable_x2apic(msr);
1560 return;
1561 }
1562
1563 if (!x2apic_mode)
1564 return;
1565
1566 if (!(msr & X2APIC_ENABLE)) {
1567 printk_once(KERN_INFO "Enabling x2apic\n");
1568 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1569 }
1570 }
1571 #endif /* CONFIG_X86_X2APIC */
1572
1573 int __init enable_IR(void)
1574 {
1575 #ifdef CONFIG_IRQ_REMAP
1576 if (!irq_remapping_supported()) {
1577 pr_debug("intr-remapping not supported\n");
1578 return -1;
1579 }
1580
1581 if (!x2apic_preenabled && skip_ioapic_setup) {
1582 pr_info("Skipped enabling intr-remap because of skipping "
1583 "io-apic setup\n");
1584 return -1;
1585 }
1586
1587 return irq_remapping_enable();
1588 #endif
1589 return -1;
1590 }
1591
1592 void __init enable_IR_x2apic(void)
1593 {
1594 unsigned long flags;
1595 int ret, x2apic_enabled = 0;
1596 int hardware_init_ret;
1597
1598 /* Make sure irq_remap_ops are initialized */
1599 setup_irq_remapping_ops();
1600
1601 hardware_init_ret = irq_remapping_prepare();
1602 if (hardware_init_ret && !x2apic_supported())
1603 return;
1604
1605 ret = save_ioapic_entries();
1606 if (ret) {
1607 pr_info("Saving IO-APIC state failed: %d\n", ret);
1608 return;
1609 }
1610
1611 local_irq_save(flags);
1612 legacy_pic->mask_all();
1613 mask_ioapic_entries();
1614
1615 if (x2apic_preenabled && nox2apic)
1616 disable_x2apic();
1617
1618 if (hardware_init_ret)
1619 ret = -1;
1620 else
1621 ret = enable_IR();
1622
1623 if (!x2apic_supported())
1624 goto skip_x2apic;
1625
1626 if (ret < 0) {
1627 /* IR is required if there is APIC ID > 255 even when running
1628 * under KVM
1629 */
1630 if (max_physical_apicid > 255 ||
1631 !hypervisor_x2apic_available()) {
1632 if (x2apic_preenabled)
1633 disable_x2apic();
1634 goto skip_x2apic;
1635 }
1636 /*
1637 * without IR all CPUs can be addressed by IOAPIC/MSI
1638 * only in physical mode
1639 */
1640 x2apic_force_phys();
1641 }
1642
1643 if (ret == IRQ_REMAP_XAPIC_MODE) {
1644 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1645 goto skip_x2apic;
1646 }
1647
1648 x2apic_enabled = 1;
1649
1650 if (x2apic_supported() && !x2apic_mode) {
1651 x2apic_mode = 1;
1652 enable_x2apic();
1653 pr_info("Enabled x2apic\n");
1654 }
1655
1656 skip_x2apic:
1657 if (ret < 0) /* IR enabling failed */
1658 restore_ioapic_entries();
1659 legacy_pic->restore_mask();
1660 local_irq_restore(flags);
1661 }
1662
1663 #ifdef CONFIG_X86_64
1664 /*
1665 * Detect and enable local APICs on non-SMP boards.
1666 * Original code written by Keir Fraser.
1667 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1668 * not correctly set up (usually the APIC timer won't work etc.)
1669 */
1670 static int __init detect_init_APIC(void)
1671 {
1672 if (!cpu_has_apic) {
1673 pr_info("No local APIC present\n");
1674 return -1;
1675 }
1676
1677 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1678 return 0;
1679 }
1680 #else
1681
1682 static int __init apic_verify(void)
1683 {
1684 u32 features, h, l;
1685
1686 /*
1687 * The APIC feature bit should now be enabled
1688 * in `cpuid'
1689 */
1690 features = cpuid_edx(1);
1691 if (!(features & (1 << X86_FEATURE_APIC))) {
1692 pr_warning("Could not enable APIC!\n");
1693 return -1;
1694 }
1695 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1696 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1697
1698 /* The BIOS may have set up the APIC at some other address */
1699 if (boot_cpu_data.x86 >= 6) {
1700 rdmsr(MSR_IA32_APICBASE, l, h);
1701 if (l & MSR_IA32_APICBASE_ENABLE)
1702 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1703 }
1704
1705 pr_info("Found and enabled local APIC!\n");
1706 return 0;
1707 }
1708
1709 int __init apic_force_enable(unsigned long addr)
1710 {
1711 u32 h, l;
1712
1713 if (disable_apic)
1714 return -1;
1715
1716 /*
1717 * Some BIOSes disable the local APIC in the APIC_BASE
1718 * MSR. This can only be done in software for Intel P6 or later
1719 * and AMD K7 (Model > 1) or later.
1720 */
1721 if (boot_cpu_data.x86 >= 6) {
1722 rdmsr(MSR_IA32_APICBASE, l, h);
1723 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1724 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1725 l &= ~MSR_IA32_APICBASE_BASE;
1726 l |= MSR_IA32_APICBASE_ENABLE | addr;
1727 wrmsr(MSR_IA32_APICBASE, l, h);
1728 enabled_via_apicbase = 1;
1729 }
1730 }
1731 return apic_verify();
1732 }
1733
1734 /*
1735 * Detect and initialize APIC
1736 */
1737 static int __init detect_init_APIC(void)
1738 {
1739 /* Disabled by kernel option? */
1740 if (disable_apic)
1741 return -1;
1742
1743 switch (boot_cpu_data.x86_vendor) {
1744 case X86_VENDOR_AMD:
1745 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1746 (boot_cpu_data.x86 >= 15))
1747 break;
1748 goto no_apic;
1749 case X86_VENDOR_INTEL:
1750 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1751 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1752 break;
1753 goto no_apic;
1754 default:
1755 goto no_apic;
1756 }
1757
1758 if (!cpu_has_apic) {
1759 /*
1760 * Over-ride BIOS and try to enable the local APIC only if
1761 * "lapic" specified.
1762 */
1763 if (!force_enable_local_apic) {
1764 pr_info("Local APIC disabled by BIOS -- "
1765 "you can enable it with \"lapic\"\n");
1766 return -1;
1767 }
1768 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1769 return -1;
1770 } else {
1771 if (apic_verify())
1772 return -1;
1773 }
1774
1775 apic_pm_activate();
1776
1777 return 0;
1778
1779 no_apic:
1780 pr_info("No local APIC present or hardware disabled\n");
1781 return -1;
1782 }
1783 #endif
1784
1785 /**
1786 * init_apic_mappings - initialize APIC mappings
1787 */
1788 void __init init_apic_mappings(void)
1789 {
1790 unsigned int new_apicid;
1791
1792 if (x2apic_mode) {
1793 boot_cpu_physical_apicid = read_apic_id();
1794 return;
1795 }
1796
1797 /* If no local APIC can be found return early */
1798 if (!smp_found_config && detect_init_APIC()) {
1799 /* lets NOP'ify apic operations */
1800 pr_info("APIC: disable apic facility\n");
1801 apic_disable();
1802 } else {
1803 apic_phys = mp_lapic_addr;
1804
1805 /*
1806 * acpi lapic path already maps that address in
1807 * acpi_register_lapic_address()
1808 */
1809 if (!acpi_lapic && !smp_found_config)
1810 register_lapic_address(apic_phys);
1811 }
1812
1813 /*
1814 * Fetch the APIC ID of the BSP in case we have a
1815 * default configuration (or the MP table is broken).
1816 */
1817 new_apicid = read_apic_id();
1818 if (boot_cpu_physical_apicid != new_apicid) {
1819 boot_cpu_physical_apicid = new_apicid;
1820 /*
1821 * yeah -- we lie about apic_version
1822 * in case if apic was disabled via boot option
1823 * but it's not a problem for SMP compiled kernel
1824 * since smp_sanity_check is prepared for such a case
1825 * and disable smp mode
1826 */
1827 apic_version[new_apicid] =
1828 GET_APIC_VERSION(apic_read(APIC_LVR));
1829 }
1830 }
1831
1832 void __init register_lapic_address(unsigned long address)
1833 {
1834 mp_lapic_addr = address;
1835
1836 if (!x2apic_mode) {
1837 set_fixmap_nocache(FIX_APIC_BASE, address);
1838 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1839 APIC_BASE, mp_lapic_addr);
1840 }
1841 if (boot_cpu_physical_apicid == -1U) {
1842 boot_cpu_physical_apicid = read_apic_id();
1843 apic_version[boot_cpu_physical_apicid] =
1844 GET_APIC_VERSION(apic_read(APIC_LVR));
1845 }
1846 }
1847
1848 /*
1849 * This initializes the IO-APIC and APIC hardware if this is
1850 * a UP kernel.
1851 */
1852 int apic_version[MAX_LOCAL_APIC];
1853
1854 int __init APIC_init_uniprocessor(void)
1855 {
1856 if (disable_apic) {
1857 pr_info("Apic disabled\n");
1858 return -1;
1859 }
1860 #ifdef CONFIG_X86_64
1861 if (!cpu_has_apic) {
1862 disable_apic = 1;
1863 pr_info("Apic disabled by BIOS\n");
1864 return -1;
1865 }
1866 #else
1867 if (!smp_found_config && !cpu_has_apic)
1868 return -1;
1869
1870 /*
1871 * Complain if the BIOS pretends there is one.
1872 */
1873 if (!cpu_has_apic &&
1874 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1875 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1876 boot_cpu_physical_apicid);
1877 return -1;
1878 }
1879 #endif
1880
1881 default_setup_apic_routing();
1882
1883 verify_local_APIC();
1884 connect_bsp_APIC();
1885
1886 #ifdef CONFIG_X86_64
1887 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1888 #else
1889 /*
1890 * Hack: In case of kdump, after a crash, kernel might be booting
1891 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1892 * might be zero if read from MP tables. Get it from LAPIC.
1893 */
1894 # ifdef CONFIG_CRASH_DUMP
1895 boot_cpu_physical_apicid = read_apic_id();
1896 # endif
1897 #endif
1898 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1899 setup_local_APIC();
1900
1901 #ifdef CONFIG_X86_IO_APIC
1902 /*
1903 * Now enable IO-APICs, actually call clear_IO_APIC
1904 * We need clear_IO_APIC before enabling error vector
1905 */
1906 if (!skip_ioapic_setup && nr_ioapics)
1907 enable_IO_APIC();
1908 #endif
1909
1910 bsp_end_local_APIC_setup();
1911
1912 #ifdef CONFIG_X86_IO_APIC
1913 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1914 setup_IO_APIC();
1915 else {
1916 nr_ioapics = 0;
1917 }
1918 #endif
1919
1920 x86_init.timers.setup_percpu_clockev();
1921 return 0;
1922 }
1923
1924 /*
1925 * Local APIC interrupts
1926 */
1927
1928 /*
1929 * This interrupt should _never_ happen with our APIC/SMP architecture
1930 */
1931 static inline void __smp_spurious_interrupt(void)
1932 {
1933 u32 v;
1934
1935 /*
1936 * Check if this really is a spurious interrupt and ACK it
1937 * if it is a vectored one. Just in case...
1938 * Spurious interrupts should not be ACKed.
1939 */
1940 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1941 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1942 ack_APIC_irq();
1943
1944 inc_irq_stat(irq_spurious_count);
1945
1946 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1947 pr_info("spurious APIC interrupt on CPU#%d, "
1948 "should never happen.\n", smp_processor_id());
1949 }
1950
1951 void smp_spurious_interrupt(struct pt_regs *regs)
1952 {
1953 entering_irq();
1954 __smp_spurious_interrupt();
1955 exiting_irq();
1956 }
1957
1958 void smp_trace_spurious_interrupt(struct pt_regs *regs)
1959 {
1960 entering_irq();
1961 trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR);
1962 __smp_spurious_interrupt();
1963 trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR);
1964 exiting_irq();
1965 }
1966
1967 /*
1968 * This interrupt should never happen with our APIC/SMP architecture
1969 */
1970 static inline void __smp_error_interrupt(struct pt_regs *regs)
1971 {
1972 u32 v0, v1;
1973 u32 i = 0;
1974 static const char * const error_interrupt_reason[] = {
1975 "Send CS error", /* APIC Error Bit 0 */
1976 "Receive CS error", /* APIC Error Bit 1 */
1977 "Send accept error", /* APIC Error Bit 2 */
1978 "Receive accept error", /* APIC Error Bit 3 */
1979 "Redirectable IPI", /* APIC Error Bit 4 */
1980 "Send illegal vector", /* APIC Error Bit 5 */
1981 "Received illegal vector", /* APIC Error Bit 6 */
1982 "Illegal register address", /* APIC Error Bit 7 */
1983 };
1984
1985 /* First tickle the hardware, only then report what went on. -- REW */
1986 v0 = apic_read(APIC_ESR);
1987 apic_write(APIC_ESR, 0);
1988 v1 = apic_read(APIC_ESR);
1989 ack_APIC_irq();
1990 atomic_inc(&irq_err_count);
1991
1992 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1993 smp_processor_id(), v0 , v1);
1994
1995 v1 = v1 & 0xff;
1996 while (v1) {
1997 if (v1 & 0x1)
1998 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1999 i++;
2000 v1 >>= 1;
2001 }
2002
2003 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2004
2005 }
2006
2007 void smp_error_interrupt(struct pt_regs *regs)
2008 {
2009 entering_irq();
2010 __smp_error_interrupt(regs);
2011 exiting_irq();
2012 }
2013
2014 void smp_trace_error_interrupt(struct pt_regs *regs)
2015 {
2016 entering_irq();
2017 trace_error_apic_entry(ERROR_APIC_VECTOR);
2018 __smp_error_interrupt(regs);
2019 trace_error_apic_exit(ERROR_APIC_VECTOR);
2020 exiting_irq();
2021 }
2022
2023 /**
2024 * connect_bsp_APIC - attach the APIC to the interrupt system
2025 */
2026 void __init connect_bsp_APIC(void)
2027 {
2028 #ifdef CONFIG_X86_32
2029 if (pic_mode) {
2030 /*
2031 * Do not trust the local APIC being empty at bootup.
2032 */
2033 clear_local_APIC();
2034 /*
2035 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2036 * local APIC to INT and NMI lines.
2037 */
2038 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2039 "enabling APIC mode.\n");
2040 imcr_pic_to_apic();
2041 }
2042 #endif
2043 if (apic->enable_apic_mode)
2044 apic->enable_apic_mode();
2045 }
2046
2047 /**
2048 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2049 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2050 *
2051 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2052 * APIC is disabled.
2053 */
2054 void disconnect_bsp_APIC(int virt_wire_setup)
2055 {
2056 unsigned int value;
2057
2058 #ifdef CONFIG_X86_32
2059 if (pic_mode) {
2060 /*
2061 * Put the board back into PIC mode (has an effect only on
2062 * certain older boards). Note that APIC interrupts, including
2063 * IPIs, won't work beyond this point! The only exception are
2064 * INIT IPIs.
2065 */
2066 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2067 "entering PIC mode.\n");
2068 imcr_apic_to_pic();
2069 return;
2070 }
2071 #endif
2072
2073 /* Go back to Virtual Wire compatibility mode */
2074
2075 /* For the spurious interrupt use vector F, and enable it */
2076 value = apic_read(APIC_SPIV);
2077 value &= ~APIC_VECTOR_MASK;
2078 value |= APIC_SPIV_APIC_ENABLED;
2079 value |= 0xf;
2080 apic_write(APIC_SPIV, value);
2081
2082 if (!virt_wire_setup) {
2083 /*
2084 * For LVT0 make it edge triggered, active high,
2085 * external and enabled
2086 */
2087 value = apic_read(APIC_LVT0);
2088 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2089 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2090 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2091 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2092 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2093 apic_write(APIC_LVT0, value);
2094 } else {
2095 /* Disable LVT0 */
2096 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2097 }
2098
2099 /*
2100 * For LVT1 make it edge triggered, active high,
2101 * nmi and enabled
2102 */
2103 value = apic_read(APIC_LVT1);
2104 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2105 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2106 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2107 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2108 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2109 apic_write(APIC_LVT1, value);
2110 }
2111
2112 void __cpuinit generic_processor_info(int apicid, int version)
2113 {
2114 int cpu, max = nr_cpu_ids;
2115 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2116 phys_cpu_present_map);
2117
2118 /*
2119 * If boot cpu has not been detected yet, then only allow upto
2120 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2121 */
2122 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2123 apicid != boot_cpu_physical_apicid) {
2124 int thiscpu = max + disabled_cpus - 1;
2125
2126 pr_warning(
2127 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2128 " reached. Keeping one slot for boot cpu."
2129 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2130
2131 disabled_cpus++;
2132 return;
2133 }
2134
2135 if (num_processors >= nr_cpu_ids) {
2136 int thiscpu = max + disabled_cpus;
2137
2138 pr_warning(
2139 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2140 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2141
2142 disabled_cpus++;
2143 return;
2144 }
2145
2146 num_processors++;
2147 if (apicid == boot_cpu_physical_apicid) {
2148 /*
2149 * x86_bios_cpu_apicid is required to have processors listed
2150 * in same order as logical cpu numbers. Hence the first
2151 * entry is BSP, and so on.
2152 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2153 * for BSP.
2154 */
2155 cpu = 0;
2156 } else
2157 cpu = cpumask_next_zero(-1, cpu_present_mask);
2158
2159 /*
2160 * Validate version
2161 */
2162 if (version == 0x0) {
2163 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2164 cpu, apicid);
2165 version = 0x10;
2166 }
2167 apic_version[apicid] = version;
2168
2169 if (version != apic_version[boot_cpu_physical_apicid]) {
2170 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2171 apic_version[boot_cpu_physical_apicid], cpu, version);
2172 }
2173
2174 physid_set(apicid, phys_cpu_present_map);
2175 if (apicid > max_physical_apicid)
2176 max_physical_apicid = apicid;
2177
2178 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2179 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2180 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2181 #endif
2182 #ifdef CONFIG_X86_32
2183 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2184 apic->x86_32_early_logical_apicid(cpu);
2185 #endif
2186 set_cpu_possible(cpu, true);
2187 set_cpu_present(cpu, true);
2188 }
2189
2190 int hard_smp_processor_id(void)
2191 {
2192 return read_apic_id();
2193 }
2194
2195 void default_init_apic_ldr(void)
2196 {
2197 unsigned long val;
2198
2199 apic_write(APIC_DFR, APIC_DFR_VALUE);
2200 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2201 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2202 apic_write(APIC_LDR, val);
2203 }
2204
2205 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2206 const struct cpumask *andmask,
2207 unsigned int *apicid)
2208 {
2209 unsigned int cpu;
2210
2211 for_each_cpu_and(cpu, cpumask, andmask) {
2212 if (cpumask_test_cpu(cpu, cpu_online_mask))
2213 break;
2214 }
2215
2216 if (likely(cpu < nr_cpu_ids)) {
2217 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2218 return 0;
2219 }
2220
2221 return -EINVAL;
2222 }
2223
2224 /*
2225 * Override the generic EOI implementation with an optimized version.
2226 * Only called during early boot when only one CPU is active and with
2227 * interrupts disabled, so we know this does not race with actual APIC driver
2228 * use.
2229 */
2230 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2231 {
2232 struct apic **drv;
2233
2234 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2235 /* Should happen once for each apic */
2236 WARN_ON((*drv)->eoi_write == eoi_write);
2237 (*drv)->eoi_write = eoi_write;
2238 }
2239 }
2240
2241 /*
2242 * Power management
2243 */
2244 #ifdef CONFIG_PM
2245
2246 static struct {
2247 /*
2248 * 'active' is true if the local APIC was enabled by us and
2249 * not the BIOS; this signifies that we are also responsible
2250 * for disabling it before entering apm/acpi suspend
2251 */
2252 int active;
2253 /* r/w apic fields */
2254 unsigned int apic_id;
2255 unsigned int apic_taskpri;
2256 unsigned int apic_ldr;
2257 unsigned int apic_dfr;
2258 unsigned int apic_spiv;
2259 unsigned int apic_lvtt;
2260 unsigned int apic_lvtpc;
2261 unsigned int apic_lvt0;
2262 unsigned int apic_lvt1;
2263 unsigned int apic_lvterr;
2264 unsigned int apic_tmict;
2265 unsigned int apic_tdcr;
2266 unsigned int apic_thmr;
2267 } apic_pm_state;
2268
2269 static int lapic_suspend(void)
2270 {
2271 unsigned long flags;
2272 int maxlvt;
2273
2274 if (!apic_pm_state.active)
2275 return 0;
2276
2277 maxlvt = lapic_get_maxlvt();
2278
2279 apic_pm_state.apic_id = apic_read(APIC_ID);
2280 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2281 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2282 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2283 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2284 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2285 if (maxlvt >= 4)
2286 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2287 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2288 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2289 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2290 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2291 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2292 #ifdef CONFIG_X86_THERMAL_VECTOR
2293 if (maxlvt >= 5)
2294 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2295 #endif
2296
2297 local_irq_save(flags);
2298 disable_local_APIC();
2299
2300 irq_remapping_disable();
2301
2302 local_irq_restore(flags);
2303 return 0;
2304 }
2305
2306 static void lapic_resume(void)
2307 {
2308 unsigned int l, h;
2309 unsigned long flags;
2310 int maxlvt;
2311
2312 if (!apic_pm_state.active)
2313 return;
2314
2315 local_irq_save(flags);
2316
2317 /*
2318 * IO-APIC and PIC have their own resume routines.
2319 * We just mask them here to make sure the interrupt
2320 * subsystem is completely quiet while we enable x2apic
2321 * and interrupt-remapping.
2322 */
2323 mask_ioapic_entries();
2324 legacy_pic->mask_all();
2325
2326 if (x2apic_mode)
2327 enable_x2apic();
2328 else {
2329 /*
2330 * Make sure the APICBASE points to the right address
2331 *
2332 * FIXME! This will be wrong if we ever support suspend on
2333 * SMP! We'll need to do this as part of the CPU restore!
2334 */
2335 if (boot_cpu_data.x86 >= 6) {
2336 rdmsr(MSR_IA32_APICBASE, l, h);
2337 l &= ~MSR_IA32_APICBASE_BASE;
2338 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2339 wrmsr(MSR_IA32_APICBASE, l, h);
2340 }
2341 }
2342
2343 maxlvt = lapic_get_maxlvt();
2344 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2345 apic_write(APIC_ID, apic_pm_state.apic_id);
2346 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2347 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2348 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2349 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2350 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2351 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2352 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2353 if (maxlvt >= 5)
2354 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2355 #endif
2356 if (maxlvt >= 4)
2357 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2358 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2359 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2360 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2361 apic_write(APIC_ESR, 0);
2362 apic_read(APIC_ESR);
2363 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2364 apic_write(APIC_ESR, 0);
2365 apic_read(APIC_ESR);
2366
2367 irq_remapping_reenable(x2apic_mode);
2368
2369 local_irq_restore(flags);
2370 }
2371
2372 /*
2373 * This device has no shutdown method - fully functioning local APICs
2374 * are needed on every CPU up until machine_halt/restart/poweroff.
2375 */
2376
2377 static struct syscore_ops lapic_syscore_ops = {
2378 .resume = lapic_resume,
2379 .suspend = lapic_suspend,
2380 };
2381
2382 static void __cpuinit apic_pm_activate(void)
2383 {
2384 apic_pm_state.active = 1;
2385 }
2386
2387 static int __init init_lapic_sysfs(void)
2388 {
2389 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2390 if (cpu_has_apic)
2391 register_syscore_ops(&lapic_syscore_ops);
2392
2393 return 0;
2394 }
2395
2396 /* local apic needs to resume before other devices access its registers. */
2397 core_initcall(init_lapic_sysfs);
2398
2399 #else /* CONFIG_PM */
2400
2401 static void apic_pm_activate(void) { }
2402
2403 #endif /* CONFIG_PM */
2404
2405 #ifdef CONFIG_X86_64
2406
2407 static int __cpuinit apic_cluster_num(void)
2408 {
2409 int i, clusters, zeros;
2410 unsigned id;
2411 u16 *bios_cpu_apicid;
2412 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2413
2414 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2415 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2416
2417 for (i = 0; i < nr_cpu_ids; i++) {
2418 /* are we being called early in kernel startup? */
2419 if (bios_cpu_apicid) {
2420 id = bios_cpu_apicid[i];
2421 } else if (i < nr_cpu_ids) {
2422 if (cpu_present(i))
2423 id = per_cpu(x86_bios_cpu_apicid, i);
2424 else
2425 continue;
2426 } else
2427 break;
2428
2429 if (id != BAD_APICID)
2430 __set_bit(APIC_CLUSTERID(id), clustermap);
2431 }
2432
2433 /* Problem: Partially populated chassis may not have CPUs in some of
2434 * the APIC clusters they have been allocated. Only present CPUs have
2435 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2436 * Since clusters are allocated sequentially, count zeros only if
2437 * they are bounded by ones.
2438 */
2439 clusters = 0;
2440 zeros = 0;
2441 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2442 if (test_bit(i, clustermap)) {
2443 clusters += 1 + zeros;
2444 zeros = 0;
2445 } else
2446 ++zeros;
2447 }
2448
2449 return clusters;
2450 }
2451
2452 static int __cpuinitdata multi_checked;
2453 static int __cpuinitdata multi;
2454
2455 static int __cpuinit set_multi(const struct dmi_system_id *d)
2456 {
2457 if (multi)
2458 return 0;
2459 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2460 multi = 1;
2461 return 0;
2462 }
2463
2464 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2465 {
2466 .callback = set_multi,
2467 .ident = "IBM System Summit2",
2468 .matches = {
2469 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2470 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2471 },
2472 },
2473 {}
2474 };
2475
2476 static void __cpuinit dmi_check_multi(void)
2477 {
2478 if (multi_checked)
2479 return;
2480
2481 dmi_check_system(multi_dmi_table);
2482 multi_checked = 1;
2483 }
2484
2485 /*
2486 * apic_is_clustered_box() -- Check if we can expect good TSC
2487 *
2488 * Thus far, the major user of this is IBM's Summit2 series:
2489 * Clustered boxes may have unsynced TSC problems if they are
2490 * multi-chassis.
2491 * Use DMI to check them
2492 */
2493 __cpuinit int apic_is_clustered_box(void)
2494 {
2495 dmi_check_multi();
2496 if (multi)
2497 return 1;
2498
2499 if (!is_vsmp_box())
2500 return 0;
2501
2502 /*
2503 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2504 * not guaranteed to be synced between boards
2505 */
2506 if (apic_cluster_num() > 1)
2507 return 1;
2508
2509 return 0;
2510 }
2511 #endif
2512
2513 /*
2514 * APIC command line parameters
2515 */
2516 static int __init setup_disableapic(char *arg)
2517 {
2518 disable_apic = 1;
2519 setup_clear_cpu_cap(X86_FEATURE_APIC);
2520 return 0;
2521 }
2522 early_param("disableapic", setup_disableapic);
2523
2524 /* same as disableapic, for compatibility */
2525 static int __init setup_nolapic(char *arg)
2526 {
2527 return setup_disableapic(arg);
2528 }
2529 early_param("nolapic", setup_nolapic);
2530
2531 static int __init parse_lapic_timer_c2_ok(char *arg)
2532 {
2533 local_apic_timer_c2_ok = 1;
2534 return 0;
2535 }
2536 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2537
2538 static int __init parse_disable_apic_timer(char *arg)
2539 {
2540 disable_apic_timer = 1;
2541 return 0;
2542 }
2543 early_param("noapictimer", parse_disable_apic_timer);
2544
2545 static int __init parse_nolapic_timer(char *arg)
2546 {
2547 disable_apic_timer = 1;
2548 return 0;
2549 }
2550 early_param("nolapic_timer", parse_nolapic_timer);
2551
2552 static int __init apic_set_verbosity(char *arg)
2553 {
2554 if (!arg) {
2555 #ifdef CONFIG_X86_64
2556 skip_ioapic_setup = 0;
2557 return 0;
2558 #endif
2559 return -EINVAL;
2560 }
2561
2562 if (strcmp("debug", arg) == 0)
2563 apic_verbosity = APIC_DEBUG;
2564 else if (strcmp("verbose", arg) == 0)
2565 apic_verbosity = APIC_VERBOSE;
2566 else {
2567 pr_warning("APIC Verbosity level %s not recognised"
2568 " use apic=verbose or apic=debug\n", arg);
2569 return -EINVAL;
2570 }
2571
2572 return 0;
2573 }
2574 early_param("apic", apic_set_verbosity);
2575
2576 static int __init lapic_insert_resource(void)
2577 {
2578 if (!apic_phys)
2579 return -1;
2580
2581 /* Put local APIC into the resource map. */
2582 lapic_resource.start = apic_phys;
2583 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2584 insert_resource(&iomem_resource, &lapic_resource);
2585
2586 return 0;
2587 }
2588
2589 /*
2590 * need call insert after e820_reserve_resources()
2591 * that is using request_resource
2592 */
2593 late_initcall(lapic_insert_resource);
Linux kernel - Deliverables
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