2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid
= -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic
;
90 * APIC command line parameters
92 static int __init
parse_lapic(char *arg
)
94 force_enable_local_apic
= 1;
97 early_param("lapic", parse_lapic
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
102 * Handle interrupt mode configuration register (IMCR).
103 * This register controls whether the interrupt signals
104 * that reach the BSP come from the master PIC or from the
105 * local APIC. Before entering Symmetric I/O Mode, either
106 * the BIOS or the operating system must switch out of
107 * PIC Mode by changing the IMCR.
109 static inline imcr_pic_to_apic(void)
111 /* select IMCR register */
113 /* NMI and 8259 INTR go through APIC */
117 static inline imcr_apic_to_pic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go directly to BSP */
127 static int apic_calibrate_pmtmr __initdata
;
128 static __init
int setup_apicpmtimer(char *s
)
130 apic_calibrate_pmtmr
= 1;
134 __setup("apicpmtimer", setup_apicpmtimer
);
137 #ifdef CONFIG_X86_X2APIC
139 /* x2apic enabled before OS handover */
140 static int x2apic_preenabled
;
141 static int disable_x2apic
;
142 static __init
int setup_nox2apic(char *str
)
145 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
148 early_param("nox2apic", setup_nox2apic
);
151 unsigned long mp_lapic_addr
;
153 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
154 static int disable_apic_timer __cpuinitdata
;
155 /* Local APIC timer works in C2 */
156 int local_apic_timer_c2_ok
;
157 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
159 int first_system_vector
= 0xfe;
162 * Debug level, exported for io_apic.c
164 unsigned int apic_verbosity
;
168 /* Have we found an MP table */
169 int smp_found_config
;
171 static struct resource lapic_resource
= {
172 .name
= "Local APIC",
173 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
176 static unsigned int calibration_result
;
178 static int lapic_next_event(unsigned long delta
,
179 struct clock_event_device
*evt
);
180 static void lapic_timer_setup(enum clock_event_mode mode
,
181 struct clock_event_device
*evt
);
182 static void lapic_timer_broadcast(const struct cpumask
*mask
);
183 static void apic_pm_activate(void);
186 * The local apic timer can be used for any function which is CPU local.
188 static struct clock_event_device lapic_clockevent
= {
190 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
191 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
193 .set_mode
= lapic_timer_setup
,
194 .set_next_event
= lapic_next_event
,
195 .broadcast
= lapic_timer_broadcast
,
199 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
201 static unsigned long apic_phys
;
204 * Get the LAPIC version
206 static inline int lapic_get_version(void)
208 return GET_APIC_VERSION(apic_read(APIC_LVR
));
212 * Check, if the APIC is integrated or a separate chip
214 static inline int lapic_is_integrated(void)
219 return APIC_INTEGRATED(lapic_get_version());
224 * Check, whether this is a modern or a first generation APIC
226 static int modern_apic(void)
228 /* AMD systems use old APIC versions, so check the CPU */
229 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
230 boot_cpu_data
.x86
>= 0xf)
232 return lapic_get_version() >= 0x14;
236 * bare function to substitute write operation
237 * and it's _that_ fast :)
239 void native_apic_write_dummy(u32 reg
, u32 v
)
241 WARN_ON_ONCE((cpu_has_apic
|| !disable_apic
));
245 * right after this call apic->write doesn't do anything
246 * note that there is no restore operation it works one way
248 void apic_disable(void)
250 apic
->write
= native_apic_write_dummy
;
253 void native_apic_wait_icr_idle(void)
255 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
259 u32
native_safe_apic_wait_icr_idle(void)
266 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
270 } while (timeout
++ < 1000);
275 void native_apic_icr_write(u32 low
, u32 id
)
277 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
278 apic_write(APIC_ICR
, low
);
281 u64
native_apic_icr_read(void)
285 icr2
= apic_read(APIC_ICR2
);
286 icr1
= apic_read(APIC_ICR
);
288 return icr1
| ((u64
)icr2
<< 32);
292 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
294 void __cpuinit
enable_NMI_through_LVT0(void)
298 /* unmask and set to NMI */
301 /* Level triggered for 82489DX (32bit mode) */
302 if (!lapic_is_integrated())
303 v
|= APIC_LVT_LEVEL_TRIGGER
;
305 apic_write(APIC_LVT0
, v
);
310 * get_physical_broadcast - Get number of physical broadcast IDs
312 int get_physical_broadcast(void)
314 return modern_apic() ? 0xff : 0xf;
319 * lapic_get_maxlvt - get the maximum number of local vector table entries
321 int lapic_get_maxlvt(void)
325 v
= apic_read(APIC_LVR
);
327 * - we always have APIC integrated on 64bit mode
328 * - 82489DXs do not report # of LVT entries
330 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
338 #define APIC_DIVISOR 16
341 * This function sets up the local APIC timer, with a timeout of
342 * 'clocks' APIC bus clock. During calibration we actually call
343 * this function twice on the boot CPU, once with a bogus timeout
344 * value, second time for real. The other (noncalibrating) CPUs
345 * call this function only once, with the real, calibrated value.
347 * We do reads before writes even if unnecessary, to get around the
348 * P5 APIC double write bug.
350 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
352 unsigned int lvtt_value
, tmp_value
;
354 lvtt_value
= LOCAL_TIMER_VECTOR
;
356 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
357 if (!lapic_is_integrated())
358 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
361 lvtt_value
|= APIC_LVT_MASKED
;
363 apic_write(APIC_LVTT
, lvtt_value
);
368 tmp_value
= apic_read(APIC_TDCR
);
369 apic_write(APIC_TDCR
,
370 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
374 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
378 * Setup extended LVT, AMD specific (K8, family 10h)
380 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
381 * MCE interrupts are supported. Thus MCE offset must be set to 0.
383 * If mask=1, the LVT entry does not generate interrupts while mask=0
384 * enables the vector. See also the BKDGs.
387 #define APIC_EILVT_LVTOFF_MCE 0
388 #define APIC_EILVT_LVTOFF_IBS 1
390 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
392 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
393 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
398 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
400 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
401 return APIC_EILVT_LVTOFF_MCE
;
404 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
406 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
407 return APIC_EILVT_LVTOFF_IBS
;
409 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
412 * Program the next event, relative to now
414 static int lapic_next_event(unsigned long delta
,
415 struct clock_event_device
*evt
)
417 apic_write(APIC_TMICT
, delta
);
422 * Setup the lapic timer in periodic or oneshot mode
424 static void lapic_timer_setup(enum clock_event_mode mode
,
425 struct clock_event_device
*evt
)
430 /* Lapic used as dummy for broadcast ? */
431 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
434 local_irq_save(flags
);
437 case CLOCK_EVT_MODE_PERIODIC
:
438 case CLOCK_EVT_MODE_ONESHOT
:
439 __setup_APIC_LVTT(calibration_result
,
440 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
442 case CLOCK_EVT_MODE_UNUSED
:
443 case CLOCK_EVT_MODE_SHUTDOWN
:
444 v
= apic_read(APIC_LVTT
);
445 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
446 apic_write(APIC_LVTT
, v
);
447 apic_write(APIC_TMICT
, 0xffffffff);
449 case CLOCK_EVT_MODE_RESUME
:
450 /* Nothing to do here */
454 local_irq_restore(flags
);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(const struct cpumask
*mask
)
463 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit
setup_APIC_timer(void)
473 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
475 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
476 levt
->cpumask
= cpumask_of(smp_processor_id());
478 clockevents_register_device(levt
);
482 * In this functions we calibrate APIC bus clocks to the external timer.
484 * We want to do the calibration only once since we want to have local timer
485 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
488 * This was previously done by reading the PIT/HPET and waiting for a wrap
489 * around to find out, that a tick has elapsed. I have a box, where the PIT
490 * readout is broken, so it never gets out of the wait loop again. This was
491 * also reported by others.
493 * Monitoring the jiffies value is inaccurate and the clockevents
494 * infrastructure allows us to do a simple substitution of the interrupt
497 * The calibration routine also uses the pm_timer when possible, as the PIT
498 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
499 * back to normal later in the boot process).
502 #define LAPIC_CAL_LOOPS (HZ/10)
504 static __initdata
int lapic_cal_loops
= -1;
505 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
506 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
507 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
508 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
511 * Temporary interrupt handler.
513 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
515 unsigned long long tsc
= 0;
516 long tapic
= apic_read(APIC_TMCCT
);
517 unsigned long pm
= acpi_pm_read_early();
522 switch (lapic_cal_loops
++) {
524 lapic_cal_t1
= tapic
;
525 lapic_cal_tsc1
= tsc
;
527 lapic_cal_j1
= jiffies
;
530 case LAPIC_CAL_LOOPS
:
531 lapic_cal_t2
= tapic
;
532 lapic_cal_tsc2
= tsc
;
533 if (pm
< lapic_cal_pm1
)
534 pm
+= ACPI_PM_OVRRUN
;
536 lapic_cal_j2
= jiffies
;
542 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
544 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
545 const long pm_thresh
= pm_100ms
/ 100;
549 #ifndef CONFIG_X86_PM_TIMER
553 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
555 /* Check, if the PM timer is available */
559 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
561 if (deltapm
> (pm_100ms
- pm_thresh
) &&
562 deltapm
< (pm_100ms
+ pm_thresh
)) {
563 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
567 res
= (((u64
)deltapm
) * mult
) >> 22;
568 do_div(res
, 1000000);
569 pr_warning("APIC calibration not consistent "
570 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
572 /* Correct the lapic counter value */
573 res
= (((u64
)(*delta
)) * pm_100ms
);
574 do_div(res
, deltapm
);
575 pr_info("APIC delta adjusted to PM-Timer: "
576 "%lu (%ld)\n", (unsigned long)res
, *delta
);
579 /* Correct the tsc counter value */
581 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
582 do_div(res
, deltapm
);
583 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
584 "PM-Timer: %lu (%ld) \n",
585 (unsigned long)res
, *deltatsc
);
586 *deltatsc
= (long)res
;
592 static int __init
calibrate_APIC_clock(void)
594 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
595 void (*real_handler
)(struct clock_event_device
*dev
);
596 unsigned long deltaj
;
597 long delta
, deltatsc
;
598 int pm_referenced
= 0;
602 /* Replace the global interrupt handler */
603 real_handler
= global_clock_event
->event_handler
;
604 global_clock_event
->event_handler
= lapic_cal_handler
;
607 * Setup the APIC counter to maximum. There is no way the lapic
608 * can underflow in the 100ms detection time frame
610 __setup_APIC_LVTT(0xffffffff, 0, 0);
612 /* Let the interrupts run */
615 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
620 /* Restore the real event handler */
621 global_clock_event
->event_handler
= real_handler
;
623 /* Build delta t1-t2 as apic timer counts down */
624 delta
= lapic_cal_t1
- lapic_cal_t2
;
625 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
627 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
629 /* we trust the PM based calibration if possible */
630 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
633 /* Calculate the scaled math multiplication factor */
634 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
635 lapic_clockevent
.shift
);
636 lapic_clockevent
.max_delta_ns
=
637 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
638 lapic_clockevent
.min_delta_ns
=
639 clockevent_delta2ns(0xF, &lapic_clockevent
);
641 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
643 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
644 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
645 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
649 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
651 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
652 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
655 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
657 calibration_result
/ (1000000 / HZ
),
658 calibration_result
% (1000000 / HZ
));
661 * Do a sanity check on the APIC calibration result
663 if (calibration_result
< (1000000 / HZ
)) {
665 pr_warning("APIC frequency too slow, disabling apic timer\n");
669 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
672 * PM timer calibration failed or not turned on
673 * so lets try APIC timer based calibration
675 if (!pm_referenced
) {
676 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
679 * Setup the apic timer manually
681 levt
->event_handler
= lapic_cal_handler
;
682 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
683 lapic_cal_loops
= -1;
685 /* Let the interrupts run */
688 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
691 /* Stop the lapic timer */
692 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
695 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
696 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
698 /* Check, if the jiffies result is consistent */
699 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
700 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
702 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
706 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
707 pr_warning("APIC timer disabled due to verification failure\n");
715 * Setup the boot APIC
717 * Calibrate and verify the result.
719 void __init
setup_boot_APIC_clock(void)
722 * The local apic timer can be disabled via the kernel
723 * commandline or from the CPU detection code. Register the lapic
724 * timer as a dummy clock event source on SMP systems, so the
725 * broadcast mechanism is used. On UP systems simply ignore it.
727 if (disable_apic_timer
) {
728 pr_info("Disabling APIC timer\n");
729 /* No broadcast on UP ! */
730 if (num_possible_cpus() > 1) {
731 lapic_clockevent
.mult
= 1;
737 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
738 "calibrating APIC timer ...\n");
740 if (calibrate_APIC_clock()) {
741 /* No broadcast on UP ! */
742 if (num_possible_cpus() > 1)
748 * If nmi_watchdog is set to IO_APIC, we need the
749 * PIT/HPET going. Otherwise register lapic as a dummy
752 if (nmi_watchdog
!= NMI_IO_APIC
)
753 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
755 pr_warning("APIC timer registered as dummy,"
756 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
758 /* Setup the lapic or request the broadcast */
762 void __cpuinit
setup_secondary_APIC_clock(void)
768 * The guts of the apic timer interrupt
770 static void local_apic_timer_interrupt(void)
772 int cpu
= smp_processor_id();
773 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
776 * Normally we should not be here till LAPIC has been initialized but
777 * in some cases like kdump, its possible that there is a pending LAPIC
778 * timer interrupt from previous kernel's context and is delivered in
779 * new kernel the moment interrupts are enabled.
781 * Interrupts are enabled early and LAPIC is setup much later, hence
782 * its possible that when we get here evt->event_handler is NULL.
783 * Check for event_handler being NULL and discard the interrupt as
786 if (!evt
->event_handler
) {
787 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
789 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
794 * the NMI deadlock-detector uses this.
796 inc_irq_stat(apic_timer_irqs
);
798 evt
->event_handler(evt
);
802 * Local APIC timer interrupt. This is the most natural way for doing
803 * local interrupts, but local timer interrupts can be emulated by
804 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
806 * [ if a single-CPU system runs an SMP kernel then we call the local
807 * interrupt as well. Thus we cannot inline the local irq ... ]
809 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
811 struct pt_regs
*old_regs
= set_irq_regs(regs
);
814 * NOTE! We'd better ACK the irq immediately,
815 * because timer handling can be slow.
819 * update_process_times() expects us to have done irq_enter().
820 * Besides, if we don't timer interrupts ignore the global
821 * interrupt lock, which is the WrongThing (tm) to do.
825 local_apic_timer_interrupt();
828 set_irq_regs(old_regs
);
831 int setup_profiling_timer(unsigned int multiplier
)
837 * Local APIC start and shutdown
841 * clear_local_APIC - shutdown the local APIC
843 * This is called, when a CPU is disabled and before rebooting, so the state of
844 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
845 * leftovers during boot.
847 void clear_local_APIC(void)
852 /* APIC hasn't been mapped yet */
853 if (!x2apic
&& !apic_phys
)
856 maxlvt
= lapic_get_maxlvt();
858 * Masking an LVT entry can trigger a local APIC error
859 * if the vector is zero. Mask LVTERR first to prevent this.
862 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
863 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
866 * Careful: we have to set masks only first to deassert
867 * any level-triggered sources.
869 v
= apic_read(APIC_LVTT
);
870 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
871 v
= apic_read(APIC_LVT0
);
872 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
873 v
= apic_read(APIC_LVT1
);
874 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
876 v
= apic_read(APIC_LVTPC
);
877 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
880 /* lets not touch this if we didn't frob it */
881 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
883 v
= apic_read(APIC_LVTTHMR
);
884 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
887 #ifdef CONFIG_X86_MCE_INTEL
889 v
= apic_read(APIC_LVTCMCI
);
890 if (!(v
& APIC_LVT_MASKED
))
891 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
896 * Clean APIC state for other OSs:
898 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
899 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
900 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
902 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
904 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
906 /* Integrated APIC (!82489DX) ? */
907 if (lapic_is_integrated()) {
909 /* Clear ESR due to Pentium errata 3AP and 11AP */
910 apic_write(APIC_ESR
, 0);
916 * disable_local_APIC - clear and disable the local APIC
918 void disable_local_APIC(void)
922 /* APIC hasn't been mapped yet */
929 * Disable APIC (implies clearing of registers
932 value
= apic_read(APIC_SPIV
);
933 value
&= ~APIC_SPIV_APIC_ENABLED
;
934 apic_write(APIC_SPIV
, value
);
938 * When LAPIC was disabled by the BIOS and enabled by the kernel,
939 * restore the disabled state.
941 if (enabled_via_apicbase
) {
944 rdmsr(MSR_IA32_APICBASE
, l
, h
);
945 l
&= ~MSR_IA32_APICBASE_ENABLE
;
946 wrmsr(MSR_IA32_APICBASE
, l
, h
);
952 * If Linux enabled the LAPIC against the BIOS default disable it down before
953 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
954 * not power-off. Additionally clear all LVT entries before disable_local_APIC
955 * for the case where Linux didn't enable the LAPIC.
957 void lapic_shutdown(void)
964 local_irq_save(flags
);
967 if (!enabled_via_apicbase
)
971 disable_local_APIC();
974 local_irq_restore(flags
);
978 * This is to verify that we're looking at a real local APIC.
979 * Check these against your board if the CPUs aren't getting
980 * started for no apparent reason.
982 int __init
verify_local_APIC(void)
984 unsigned int reg0
, reg1
;
987 * The version register is read-only in a real APIC.
989 reg0
= apic_read(APIC_LVR
);
990 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
991 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
992 reg1
= apic_read(APIC_LVR
);
993 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
996 * The two version reads above should print the same
997 * numbers. If the second one is different, then we
998 * poke at a non-APIC.
1004 * Check if the version looks reasonably.
1006 reg1
= GET_APIC_VERSION(reg0
);
1007 if (reg1
== 0x00 || reg1
== 0xff)
1009 reg1
= lapic_get_maxlvt();
1010 if (reg1
< 0x02 || reg1
== 0xff)
1014 * The ID register is read/write in a real APIC.
1016 reg0
= apic_read(APIC_ID
);
1017 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1018 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1019 reg1
= apic_read(APIC_ID
);
1020 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1021 apic_write(APIC_ID
, reg0
);
1022 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1026 * The next two are just to see if we have sane values.
1027 * They're only really relevant if we're in Virtual Wire
1028 * compatibility mode, but most boxes are anymore.
1030 reg0
= apic_read(APIC_LVT0
);
1031 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1032 reg1
= apic_read(APIC_LVT1
);
1033 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1039 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1041 void __init
sync_Arb_IDs(void)
1044 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1047 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1053 apic_wait_icr_idle();
1055 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1056 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1057 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1061 * An initial setup of the virtual wire mode.
1063 void __init
init_bsp_APIC(void)
1068 * Don't do the setup now if we have a SMP BIOS as the
1069 * through-I/O-APIC virtual wire mode might be active.
1071 if (smp_found_config
|| !cpu_has_apic
)
1075 * Do not trust the local APIC being empty at bootup.
1082 value
= apic_read(APIC_SPIV
);
1083 value
&= ~APIC_VECTOR_MASK
;
1084 value
|= APIC_SPIV_APIC_ENABLED
;
1086 #ifdef CONFIG_X86_32
1087 /* This bit is reserved on P4/Xeon and should be cleared */
1088 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1089 (boot_cpu_data
.x86
== 15))
1090 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1093 value
|= APIC_SPIV_FOCUS_DISABLED
;
1094 value
|= SPURIOUS_APIC_VECTOR
;
1095 apic_write(APIC_SPIV
, value
);
1098 * Set up the virtual wire mode.
1100 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1101 value
= APIC_DM_NMI
;
1102 if (!lapic_is_integrated()) /* 82489DX */
1103 value
|= APIC_LVT_LEVEL_TRIGGER
;
1104 apic_write(APIC_LVT1
, value
);
1107 static void __cpuinit
lapic_setup_esr(void)
1109 unsigned int oldvalue
, value
, maxlvt
;
1111 if (!lapic_is_integrated()) {
1112 pr_info("No ESR for 82489DX.\n");
1116 if (apic
->disable_esr
) {
1118 * Something untraceable is creating bad interrupts on
1119 * secondary quads ... for the moment, just leave the
1120 * ESR disabled - we can't do anything useful with the
1121 * errors anyway - mbligh
1123 pr_info("Leaving ESR disabled.\n");
1127 maxlvt
= lapic_get_maxlvt();
1128 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1129 apic_write(APIC_ESR
, 0);
1130 oldvalue
= apic_read(APIC_ESR
);
1132 /* enables sending errors */
1133 value
= ERROR_APIC_VECTOR
;
1134 apic_write(APIC_LVTERR
, value
);
1137 * spec says clear errors after enabling vector.
1140 apic_write(APIC_ESR
, 0);
1141 value
= apic_read(APIC_ESR
);
1142 if (value
!= oldvalue
)
1143 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1144 "vector: 0x%08x after: 0x%08x\n",
1150 * setup_local_APIC - setup the local APIC
1152 void __cpuinit
setup_local_APIC(void)
1158 arch_disable_smp_support();
1162 #ifdef CONFIG_X86_32
1163 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1164 if (lapic_is_integrated() && apic
->disable_esr
) {
1165 apic_write(APIC_ESR
, 0);
1166 apic_write(APIC_ESR
, 0);
1167 apic_write(APIC_ESR
, 0);
1168 apic_write(APIC_ESR
, 0);
1175 * Double-check whether this APIC is really registered.
1176 * This is meaningless in clustered apic mode, so we skip it.
1178 if (!apic
->apic_id_registered())
1182 * Intel recommends to set DFR, LDR and TPR before enabling
1183 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1184 * document number 292116). So here it goes...
1186 apic
->init_apic_ldr();
1189 * Set Task Priority to 'accept all'. We never change this
1192 value
= apic_read(APIC_TASKPRI
);
1193 value
&= ~APIC_TPRI_MASK
;
1194 apic_write(APIC_TASKPRI
, value
);
1197 * After a crash, we no longer service the interrupts and a pending
1198 * interrupt from previous kernel might still have ISR bit set.
1200 * Most probably by now CPU has serviced that pending interrupt and
1201 * it might not have done the ack_APIC_irq() because it thought,
1202 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1203 * does not clear the ISR bit and cpu thinks it has already serivced
1204 * the interrupt. Hence a vector might get locked. It was noticed
1205 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1207 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1208 value
= apic_read(APIC_ISR
+ i
*0x10);
1209 for (j
= 31; j
>= 0; j
--) {
1216 * Now that we are all set up, enable the APIC
1218 value
= apic_read(APIC_SPIV
);
1219 value
&= ~APIC_VECTOR_MASK
;
1223 value
|= APIC_SPIV_APIC_ENABLED
;
1225 #ifdef CONFIG_X86_32
1227 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1228 * certain networking cards. If high frequency interrupts are
1229 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1230 * entry is masked/unmasked at a high rate as well then sooner or
1231 * later IOAPIC line gets 'stuck', no more interrupts are received
1232 * from the device. If focus CPU is disabled then the hang goes
1235 * [ This bug can be reproduced easily with a level-triggered
1236 * PCI Ne2000 networking cards and PII/PIII processors, dual
1240 * Actually disabling the focus CPU check just makes the hang less
1241 * frequent as it makes the interrupt distributon model be more
1242 * like LRU than MRU (the short-term load is more even across CPUs).
1243 * See also the comment in end_level_ioapic_irq(). --macro
1247 * - enable focus processor (bit==0)
1248 * - 64bit mode always use processor focus
1249 * so no need to set it
1251 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1255 * Set spurious IRQ vector
1257 value
|= SPURIOUS_APIC_VECTOR
;
1258 apic_write(APIC_SPIV
, value
);
1261 * Set up LVT0, LVT1:
1263 * set up through-local-APIC on the BP's LINT0. This is not
1264 * strictly necessary in pure symmetric-IO mode, but sometimes
1265 * we delegate interrupts to the 8259A.
1268 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1270 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1271 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1272 value
= APIC_DM_EXTINT
;
1273 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1274 smp_processor_id());
1276 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1277 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1278 smp_processor_id());
1280 apic_write(APIC_LVT0
, value
);
1283 * only the BP should see the LINT1 NMI signal, obviously.
1285 if (!smp_processor_id())
1286 value
= APIC_DM_NMI
;
1288 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1289 if (!lapic_is_integrated()) /* 82489DX */
1290 value
|= APIC_LVT_LEVEL_TRIGGER
;
1291 apic_write(APIC_LVT1
, value
);
1295 #ifdef CONFIG_X86_MCE_INTEL
1296 /* Recheck CMCI information after local APIC is up on CPU #0 */
1297 if (smp_processor_id() == 0)
1302 void __cpuinit
end_local_APIC_setup(void)
1306 #ifdef CONFIG_X86_32
1309 /* Disable the local apic timer */
1310 value
= apic_read(APIC_LVTT
);
1311 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1312 apic_write(APIC_LVTT
, value
);
1316 setup_apic_nmi_watchdog(NULL
);
1320 #ifdef CONFIG_X86_X2APIC
1321 void check_x2apic(void)
1323 if (x2apic_enabled()) {
1324 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1325 x2apic_preenabled
= x2apic
= 1;
1329 void enable_x2apic(void)
1336 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1337 if (!(msr
& X2APIC_ENABLE
)) {
1338 pr_info("Enabling x2apic\n");
1339 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1343 void __init
enable_IR_x2apic(void)
1345 #ifdef CONFIG_INTR_REMAP
1347 unsigned long flags
;
1348 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1350 if (!cpu_has_x2apic
)
1353 if (!x2apic_preenabled
&& disable_x2apic
) {
1354 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1355 "because of nox2apic\n");
1359 if (x2apic_preenabled
&& disable_x2apic
)
1360 panic("Bios already enabled x2apic, can't enforce nox2apic");
1362 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1363 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1364 "because of skipping io-apic setup\n");
1368 ret
= dmar_table_init();
1370 pr_info("dmar_table_init() failed with %d:\n", ret
);
1372 if (x2apic_preenabled
)
1373 panic("x2apic enabled by bios. But IR enabling failed");
1375 pr_info("Not enabling x2apic,Intr-remapping\n");
1379 ioapic_entries
= alloc_ioapic_entries();
1380 if (!ioapic_entries
) {
1381 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1385 ret
= save_IO_APIC_setup(ioapic_entries
);
1387 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1391 local_irq_save(flags
);
1392 mask_IO_APIC_setup(ioapic_entries
);
1395 ret
= enable_intr_remapping(EIM_32BIT_APIC_ID
);
1397 if (ret
&& x2apic_preenabled
) {
1398 local_irq_restore(flags
);
1399 panic("x2apic enabled by bios. But IR enabling failed");
1413 * IR enabling failed
1415 restore_IO_APIC_setup(ioapic_entries
);
1417 reinit_intr_remapped_IO_APIC(x2apic_preenabled
, ioapic_entries
);
1420 local_irq_restore(flags
);
1424 if (!x2apic_preenabled
)
1425 pr_info("Enabled x2apic and interrupt-remapping\n");
1427 pr_info("Enabled Interrupt-remapping\n");
1429 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1431 free_ioapic_entries(ioapic_entries
);
1433 if (!cpu_has_x2apic
)
1436 if (x2apic_preenabled
)
1437 panic("x2apic enabled prior OS handover,"
1438 " enable CONFIG_INTR_REMAP");
1440 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1446 #endif /* CONFIG_X86_X2APIC */
1448 #ifdef CONFIG_X86_64
1450 * Detect and enable local APICs on non-SMP boards.
1451 * Original code written by Keir Fraser.
1452 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1453 * not correctly set up (usually the APIC timer won't work etc.)
1455 static int __init
detect_init_APIC(void)
1457 if (!cpu_has_apic
) {
1458 pr_info("No local APIC present\n");
1462 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1463 boot_cpu_physical_apicid
= 0;
1468 * Detect and initialize APIC
1470 static int __init
detect_init_APIC(void)
1474 /* Disabled by kernel option? */
1478 switch (boot_cpu_data
.x86_vendor
) {
1479 case X86_VENDOR_AMD
:
1480 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1481 (boot_cpu_data
.x86
>= 15))
1484 case X86_VENDOR_INTEL
:
1485 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1486 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1493 if (!cpu_has_apic
) {
1495 * Over-ride BIOS and try to enable the local APIC only if
1496 * "lapic" specified.
1498 if (!force_enable_local_apic
) {
1499 pr_info("Local APIC disabled by BIOS -- "
1500 "you can enable it with \"lapic\"\n");
1504 * Some BIOSes disable the local APIC in the APIC_BASE
1505 * MSR. This can only be done in software for Intel P6 or later
1506 * and AMD K7 (Model > 1) or later.
1508 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1509 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1510 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1511 l
&= ~MSR_IA32_APICBASE_BASE
;
1512 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1513 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1514 enabled_via_apicbase
= 1;
1518 * The APIC feature bit should now be enabled
1521 features
= cpuid_edx(1);
1522 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1523 pr_warning("Could not enable APIC!\n");
1526 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1527 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1529 /* The BIOS may have set up the APIC at some other address */
1530 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1531 if (l
& MSR_IA32_APICBASE_ENABLE
)
1532 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1534 pr_info("Found and enabled local APIC!\n");
1541 pr_info("No local APIC present or hardware disabled\n");
1546 #ifdef CONFIG_X86_64
1547 void __init
early_init_lapic_mapping(void)
1549 unsigned long phys_addr
;
1552 * If no local APIC can be found then go out
1553 * : it means there is no mpatable and MADT
1555 if (!smp_found_config
)
1558 phys_addr
= mp_lapic_addr
;
1560 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1561 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1562 APIC_BASE
, phys_addr
);
1565 * Fetch the APIC ID of the BSP in case we have a
1566 * default configuration (or the MP table is broken).
1568 boot_cpu_physical_apicid
= read_apic_id();
1573 * init_apic_mappings - initialize APIC mappings
1575 void __init
init_apic_mappings(void)
1578 boot_cpu_physical_apicid
= read_apic_id();
1583 * If no local APIC can be found then set up a fake all
1584 * zeroes page to simulate the local APIC and another
1585 * one for the IO-APIC.
1587 if (!smp_found_config
&& detect_init_APIC()) {
1588 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1589 apic_phys
= __pa(apic_phys
);
1591 apic_phys
= mp_lapic_addr
;
1593 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1594 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1595 APIC_BASE
, apic_phys
);
1598 * Fetch the APIC ID of the BSP in case we have a
1599 * default configuration (or the MP table is broken).
1601 if (boot_cpu_physical_apicid
== -1U)
1602 boot_cpu_physical_apicid
= read_apic_id();
1604 /* lets check if we may to NOP'ify apic operations */
1605 if (!cpu_has_apic
) {
1606 pr_info("APIC: disable apic facility\n");
1612 * This initializes the IO-APIC and APIC hardware if this is
1615 int apic_version
[MAX_APICS
];
1617 int __init
APIC_init_uniprocessor(void)
1620 pr_info("Apic disabled\n");
1623 #ifdef CONFIG_X86_64
1624 if (!cpu_has_apic
) {
1626 pr_info("Apic disabled by BIOS\n");
1630 if (!smp_found_config
&& !cpu_has_apic
)
1634 * Complain if the BIOS pretends there is one.
1636 if (!cpu_has_apic
&&
1637 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1638 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1639 boot_cpu_physical_apicid
);
1640 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1646 #ifdef CONFIG_X86_64
1647 default_setup_apic_routing();
1650 verify_local_APIC();
1653 #ifdef CONFIG_X86_64
1654 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1657 * Hack: In case of kdump, after a crash, kernel might be booting
1658 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1659 * might be zero if read from MP tables. Get it from LAPIC.
1661 # ifdef CONFIG_CRASH_DUMP
1662 boot_cpu_physical_apicid
= read_apic_id();
1665 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1668 #ifdef CONFIG_X86_IO_APIC
1670 * Now enable IO-APICs, actually call clear_IO_APIC
1671 * We need clear_IO_APIC before enabling error vector
1673 if (!skip_ioapic_setup
&& nr_ioapics
)
1677 end_local_APIC_setup();
1679 #ifdef CONFIG_X86_IO_APIC
1680 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1684 localise_nmi_watchdog();
1687 localise_nmi_watchdog();
1691 #ifdef CONFIG_X86_64
1692 check_nmi_watchdog();
1699 * Local APIC interrupts
1703 * This interrupt should _never_ happen with our APIC/SMP architecture
1705 void smp_spurious_interrupt(struct pt_regs
*regs
)
1712 * Check if this really is a spurious interrupt and ACK it
1713 * if it is a vectored one. Just in case...
1714 * Spurious interrupts should not be ACKed.
1716 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1717 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1720 inc_irq_stat(irq_spurious_count
);
1722 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1723 pr_info("spurious APIC interrupt on CPU#%d, "
1724 "should never happen.\n", smp_processor_id());
1729 * This interrupt should never happen with our APIC/SMP architecture
1731 void smp_error_interrupt(struct pt_regs
*regs
)
1737 /* First tickle the hardware, only then report what went on. -- REW */
1738 v
= apic_read(APIC_ESR
);
1739 apic_write(APIC_ESR
, 0);
1740 v1
= apic_read(APIC_ESR
);
1742 atomic_inc(&irq_err_count
);
1745 * Here is what the APIC error bits mean:
1747 * 1: Receive CS error
1748 * 2: Send accept error
1749 * 3: Receive accept error
1751 * 5: Send illegal vector
1752 * 6: Received illegal vector
1753 * 7: Illegal register address
1755 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1756 smp_processor_id(), v
, v1
);
1761 * connect_bsp_APIC - attach the APIC to the interrupt system
1763 void __init
connect_bsp_APIC(void)
1765 #ifdef CONFIG_X86_32
1768 * Do not trust the local APIC being empty at bootup.
1772 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1773 * local APIC to INT and NMI lines.
1775 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1776 "enabling APIC mode.\n");
1780 if (apic
->enable_apic_mode
)
1781 apic
->enable_apic_mode();
1785 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1786 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1788 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1791 void disconnect_bsp_APIC(int virt_wire_setup
)
1795 #ifdef CONFIG_X86_32
1798 * Put the board back into PIC mode (has an effect only on
1799 * certain older boards). Note that APIC interrupts, including
1800 * IPIs, won't work beyond this point! The only exception are
1803 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1804 "entering PIC mode.\n");
1810 /* Go back to Virtual Wire compatibility mode */
1812 /* For the spurious interrupt use vector F, and enable it */
1813 value
= apic_read(APIC_SPIV
);
1814 value
&= ~APIC_VECTOR_MASK
;
1815 value
|= APIC_SPIV_APIC_ENABLED
;
1817 apic_write(APIC_SPIV
, value
);
1819 if (!virt_wire_setup
) {
1821 * For LVT0 make it edge triggered, active high,
1822 * external and enabled
1824 value
= apic_read(APIC_LVT0
);
1825 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1826 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1827 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1828 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1829 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1830 apic_write(APIC_LVT0
, value
);
1833 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1837 * For LVT1 make it edge triggered, active high,
1840 value
= apic_read(APIC_LVT1
);
1841 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1842 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1843 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1844 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1845 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1846 apic_write(APIC_LVT1
, value
);
1849 void __cpuinit
generic_processor_info(int apicid
, int version
)
1856 if (version
== 0x0) {
1857 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1858 "fixing up to 0x10. (tell your hw vendor)\n",
1862 apic_version
[apicid
] = version
;
1864 if (num_processors
>= nr_cpu_ids
) {
1865 int max
= nr_cpu_ids
;
1866 int thiscpu
= max
+ disabled_cpus
;
1869 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1870 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1877 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1879 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1881 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1882 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1884 physid_set(apicid
, phys_cpu_present_map
);
1885 if (apicid
== boot_cpu_physical_apicid
) {
1887 * x86_bios_cpu_apicid is required to have processors listed
1888 * in same order as logical cpu numbers. Hence the first
1889 * entry is BSP, and so on.
1893 if (apicid
> max_physical_apicid
)
1894 max_physical_apicid
= apicid
;
1896 #ifdef CONFIG_X86_32
1898 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1899 * but we need to work other dependencies like SMP_SUSPEND etc
1900 * before this can be done without some confusion.
1901 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1902 * - Ashok Raj <ashok.raj@intel.com>
1904 if (max_physical_apicid
>= 8) {
1905 switch (boot_cpu_data
.x86_vendor
) {
1906 case X86_VENDOR_INTEL
:
1907 if (!APIC_XAPIC(version
)) {
1911 /* If P4 and above fall through */
1912 case X86_VENDOR_AMD
:
1918 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1919 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1920 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1923 set_cpu_possible(cpu
, true);
1924 set_cpu_present(cpu
, true);
1927 int hard_smp_processor_id(void)
1929 return read_apic_id();
1932 void default_init_apic_ldr(void)
1936 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1937 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1938 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1939 apic_write(APIC_LDR
, val
);
1942 #ifdef CONFIG_X86_32
1943 int default_apicid_to_node(int logical_apicid
)
1946 return apicid_2_node
[hard_smp_processor_id()];
1960 * 'active' is true if the local APIC was enabled by us and
1961 * not the BIOS; this signifies that we are also responsible
1962 * for disabling it before entering apm/acpi suspend
1965 /* r/w apic fields */
1966 unsigned int apic_id
;
1967 unsigned int apic_taskpri
;
1968 unsigned int apic_ldr
;
1969 unsigned int apic_dfr
;
1970 unsigned int apic_spiv
;
1971 unsigned int apic_lvtt
;
1972 unsigned int apic_lvtpc
;
1973 unsigned int apic_lvt0
;
1974 unsigned int apic_lvt1
;
1975 unsigned int apic_lvterr
;
1976 unsigned int apic_tmict
;
1977 unsigned int apic_tdcr
;
1978 unsigned int apic_thmr
;
1981 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1983 unsigned long flags
;
1986 if (!apic_pm_state
.active
)
1989 maxlvt
= lapic_get_maxlvt();
1991 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1992 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1993 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1994 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1995 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1996 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1998 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1999 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2000 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2001 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2002 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2003 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2004 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2006 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2009 local_irq_save(flags
);
2010 disable_local_APIC();
2011 #ifdef CONFIG_INTR_REMAP
2012 if (intr_remapping_enabled
)
2013 disable_intr_remapping();
2015 local_irq_restore(flags
);
2019 static int lapic_resume(struct sys_device
*dev
)
2022 unsigned long flags
;
2025 #ifdef CONFIG_INTR_REMAP
2027 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2029 if (!apic_pm_state
.active
)
2032 local_irq_save(flags
);
2034 ioapic_entries
= alloc_ioapic_entries();
2035 if (!ioapic_entries
) {
2036 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2040 ret
= save_IO_APIC_setup(ioapic_entries
);
2042 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2043 free_ioapic_entries(ioapic_entries
);
2047 mask_IO_APIC_setup(ioapic_entries
);
2052 if (!apic_pm_state
.active
)
2055 local_irq_save(flags
);
2062 * Make sure the APICBASE points to the right address
2064 * FIXME! This will be wrong if we ever support suspend on
2065 * SMP! We'll need to do this as part of the CPU restore!
2067 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2068 l
&= ~MSR_IA32_APICBASE_BASE
;
2069 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2070 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2073 maxlvt
= lapic_get_maxlvt();
2074 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2075 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2076 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2077 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2078 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2079 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2080 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2081 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2082 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2084 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2087 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2088 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2089 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2090 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2091 apic_write(APIC_ESR
, 0);
2092 apic_read(APIC_ESR
);
2093 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2094 apic_write(APIC_ESR
, 0);
2095 apic_read(APIC_ESR
);
2097 #ifdef CONFIG_INTR_REMAP
2098 if (intr_remapping_enabled
)
2099 reenable_intr_remapping(EIM_32BIT_APIC_ID
);
2103 restore_IO_APIC_setup(ioapic_entries
);
2104 free_ioapic_entries(ioapic_entries
);
2108 local_irq_restore(flags
);
2115 * This device has no shutdown method - fully functioning local APICs
2116 * are needed on every CPU up until machine_halt/restart/poweroff.
2119 static struct sysdev_class lapic_sysclass
= {
2121 .resume
= lapic_resume
,
2122 .suspend
= lapic_suspend
,
2125 static struct sys_device device_lapic
= {
2127 .cls
= &lapic_sysclass
,
2130 static void __cpuinit
apic_pm_activate(void)
2132 apic_pm_state
.active
= 1;
2135 static int __init
init_lapic_sysfs(void)
2141 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2143 error
= sysdev_class_register(&lapic_sysclass
);
2145 error
= sysdev_register(&device_lapic
);
2149 /* local apic needs to resume before other devices access its registers. */
2150 core_initcall(init_lapic_sysfs
);
2152 #else /* CONFIG_PM */
2154 static void apic_pm_activate(void) { }
2156 #endif /* CONFIG_PM */
2158 #ifdef CONFIG_X86_64
2160 * apic_is_clustered_box() -- Check if we can expect good TSC
2162 * Thus far, the major user of this is IBM's Summit2 series:
2164 * Clustered boxes may have unsynced TSC problems if they are
2165 * multi-chassis. Use available data to take a good guess.
2166 * If in doubt, go HPET.
2168 __cpuinit
int apic_is_clustered_box(void)
2170 int i
, clusters
, zeros
;
2172 u16
*bios_cpu_apicid
;
2173 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2176 * there is not this kind of box with AMD CPU yet.
2177 * Some AMD box with quadcore cpu and 8 sockets apicid
2178 * will be [4, 0x23] or [8, 0x27] could be thought to
2179 * vsmp box still need checking...
2181 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2184 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2185 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2187 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2188 /* are we being called early in kernel startup? */
2189 if (bios_cpu_apicid
) {
2190 id
= bios_cpu_apicid
[i
];
2191 } else if (i
< nr_cpu_ids
) {
2193 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2199 if (id
!= BAD_APICID
)
2200 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2203 /* Problem: Partially populated chassis may not have CPUs in some of
2204 * the APIC clusters they have been allocated. Only present CPUs have
2205 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2206 * Since clusters are allocated sequentially, count zeros only if
2207 * they are bounded by ones.
2211 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2212 if (test_bit(i
, clustermap
)) {
2213 clusters
+= 1 + zeros
;
2219 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2220 * not guaranteed to be synced between boards
2222 if (is_vsmp_box() && clusters
> 1)
2226 * If clusters > 2, then should be multi-chassis.
2227 * May have to revisit this when multi-core + hyperthreaded CPUs come
2228 * out, but AFAIK this will work even for them.
2230 return (clusters
> 2);
2235 * APIC command line parameters
2237 static int __init
setup_disableapic(char *arg
)
2240 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2243 early_param("disableapic", setup_disableapic
);
2245 /* same as disableapic, for compatibility */
2246 static int __init
setup_nolapic(char *arg
)
2248 return setup_disableapic(arg
);
2250 early_param("nolapic", setup_nolapic
);
2252 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2254 local_apic_timer_c2_ok
= 1;
2257 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2259 static int __init
parse_disable_apic_timer(char *arg
)
2261 disable_apic_timer
= 1;
2264 early_param("noapictimer", parse_disable_apic_timer
);
2266 static int __init
parse_nolapic_timer(char *arg
)
2268 disable_apic_timer
= 1;
2271 early_param("nolapic_timer", parse_nolapic_timer
);
2273 static int __init
apic_set_verbosity(char *arg
)
2276 #ifdef CONFIG_X86_64
2277 skip_ioapic_setup
= 0;
2283 if (strcmp("debug", arg
) == 0)
2284 apic_verbosity
= APIC_DEBUG
;
2285 else if (strcmp("verbose", arg
) == 0)
2286 apic_verbosity
= APIC_VERBOSE
;
2288 pr_warning("APIC Verbosity level %s not recognised"
2289 " use apic=verbose or apic=debug\n", arg
);
2295 early_param("apic", apic_set_verbosity
);
2297 static int __init
lapic_insert_resource(void)
2302 /* Put local APIC into the resource map. */
2303 lapic_resource
.start
= apic_phys
;
2304 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2305 insert_resource(&iomem_resource
, &lapic_resource
);
2311 * need call insert after e820_reserve_resources()
2312 * that is using request_resource
2314 late_initcall(lapic_insert_resource
);