2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid
= -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic
;
90 * APIC command line parameters
92 static int __init
parse_lapic(char *arg
)
94 force_enable_local_apic
= 1;
97 early_param("lapic", parse_lapic
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
102 * Handle interrupt mode configuration register (IMCR).
103 * This register controls whether the interrupt signals
104 * that reach the BSP come from the master PIC or from the
105 * local APIC. Before entering Symmetric I/O Mode, either
106 * the BIOS or the operating system must switch out of
107 * PIC Mode by changing the IMCR.
109 static inline void imcr_pic_to_apic(void)
111 /* select IMCR register */
113 /* NMI and 8259 INTR go through APIC */
117 static inline void imcr_apic_to_pic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go directly to BSP */
127 static int apic_calibrate_pmtmr __initdata
;
128 static __init
int setup_apicpmtimer(char *s
)
130 apic_calibrate_pmtmr
= 1;
134 __setup("apicpmtimer", setup_apicpmtimer
);
138 #ifdef CONFIG_X86_X2APIC
139 /* x2apic enabled before OS handover */
140 static int x2apic_preenabled
;
141 static int disable_x2apic
;
142 static __init
int setup_nox2apic(char *str
)
144 if (x2apic_enabled()) {
145 pr_warning("Bios already enabled x2apic, "
146 "can't enforce nox2apic");
151 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
154 early_param("nox2apic", setup_nox2apic
);
157 unsigned long mp_lapic_addr
;
159 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
160 static int disable_apic_timer __cpuinitdata
;
161 /* Local APIC timer works in C2 */
162 int local_apic_timer_c2_ok
;
163 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
165 int first_system_vector
= 0xfe;
168 * Debug level, exported for io_apic.c
170 unsigned int apic_verbosity
;
174 /* Have we found an MP table */
175 int smp_found_config
;
177 static struct resource lapic_resource
= {
178 .name
= "Local APIC",
179 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
182 static unsigned int calibration_result
;
184 static int lapic_next_event(unsigned long delta
,
185 struct clock_event_device
*evt
);
186 static void lapic_timer_setup(enum clock_event_mode mode
,
187 struct clock_event_device
*evt
);
188 static void lapic_timer_broadcast(const struct cpumask
*mask
);
189 static void apic_pm_activate(void);
192 * The local apic timer can be used for any function which is CPU local.
194 static struct clock_event_device lapic_clockevent
= {
196 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
197 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
199 .set_mode
= lapic_timer_setup
,
200 .set_next_event
= lapic_next_event
,
201 .broadcast
= lapic_timer_broadcast
,
205 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
207 static unsigned long apic_phys
;
210 * Get the LAPIC version
212 static inline int lapic_get_version(void)
214 return GET_APIC_VERSION(apic_read(APIC_LVR
));
218 * Check, if the APIC is integrated or a separate chip
220 static inline int lapic_is_integrated(void)
225 return APIC_INTEGRATED(lapic_get_version());
230 * Check, whether this is a modern or a first generation APIC
232 static int modern_apic(void)
234 /* AMD systems use old APIC versions, so check the CPU */
235 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
236 boot_cpu_data
.x86
>= 0xf)
238 return lapic_get_version() >= 0x14;
242 * bare function to substitute write operation
243 * and it's _that_ fast :)
245 static void native_apic_write_dummy(u32 reg
, u32 v
)
247 WARN_ON_ONCE((cpu_has_apic
|| !disable_apic
));
250 static u32
native_apic_read_dummy(u32 reg
)
252 WARN_ON_ONCE((cpu_has_apic
&& !disable_apic
));
257 * right after this call apic->write/read doesn't do anything
258 * note that there is no restore operation it works one way
260 void apic_disable(void)
262 apic
->read
= native_apic_read_dummy
;
263 apic
->write
= native_apic_write_dummy
;
266 void native_apic_wait_icr_idle(void)
268 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
272 u32
native_safe_apic_wait_icr_idle(void)
279 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
283 } while (timeout
++ < 1000);
288 void native_apic_icr_write(u32 low
, u32 id
)
290 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
291 apic_write(APIC_ICR
, low
);
294 u64
native_apic_icr_read(void)
298 icr2
= apic_read(APIC_ICR2
);
299 icr1
= apic_read(APIC_ICR
);
301 return icr1
| ((u64
)icr2
<< 32);
305 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
307 void __cpuinit
enable_NMI_through_LVT0(void)
311 /* unmask and set to NMI */
314 /* Level triggered for 82489DX (32bit mode) */
315 if (!lapic_is_integrated())
316 v
|= APIC_LVT_LEVEL_TRIGGER
;
318 apic_write(APIC_LVT0
, v
);
323 * get_physical_broadcast - Get number of physical broadcast IDs
325 int get_physical_broadcast(void)
327 return modern_apic() ? 0xff : 0xf;
332 * lapic_get_maxlvt - get the maximum number of local vector table entries
334 int lapic_get_maxlvt(void)
338 v
= apic_read(APIC_LVR
);
340 * - we always have APIC integrated on 64bit mode
341 * - 82489DXs do not report # of LVT entries
343 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
351 #define APIC_DIVISOR 16
354 * This function sets up the local APIC timer, with a timeout of
355 * 'clocks' APIC bus clock. During calibration we actually call
356 * this function twice on the boot CPU, once with a bogus timeout
357 * value, second time for real. The other (noncalibrating) CPUs
358 * call this function only once, with the real, calibrated value.
360 * We do reads before writes even if unnecessary, to get around the
361 * P5 APIC double write bug.
363 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
365 unsigned int lvtt_value
, tmp_value
;
367 lvtt_value
= LOCAL_TIMER_VECTOR
;
369 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
370 if (!lapic_is_integrated())
371 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
374 lvtt_value
|= APIC_LVT_MASKED
;
376 apic_write(APIC_LVTT
, lvtt_value
);
381 tmp_value
= apic_read(APIC_TDCR
);
382 apic_write(APIC_TDCR
,
383 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
387 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
391 * Setup extended LVT, AMD specific (K8, family 10h)
393 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
394 * MCE interrupts are supported. Thus MCE offset must be set to 0.
396 * If mask=1, the LVT entry does not generate interrupts while mask=0
397 * enables the vector. See also the BKDGs.
400 #define APIC_EILVT_LVTOFF_MCE 0
401 #define APIC_EILVT_LVTOFF_IBS 1
403 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
405 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVTn(0);
406 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
411 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
413 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
414 return APIC_EILVT_LVTOFF_MCE
;
417 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
419 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
420 return APIC_EILVT_LVTOFF_IBS
;
422 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
425 * Program the next event, relative to now
427 static int lapic_next_event(unsigned long delta
,
428 struct clock_event_device
*evt
)
430 apic_write(APIC_TMICT
, delta
);
435 * Setup the lapic timer in periodic or oneshot mode
437 static void lapic_timer_setup(enum clock_event_mode mode
,
438 struct clock_event_device
*evt
)
443 /* Lapic used as dummy for broadcast ? */
444 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
447 local_irq_save(flags
);
450 case CLOCK_EVT_MODE_PERIODIC
:
451 case CLOCK_EVT_MODE_ONESHOT
:
452 __setup_APIC_LVTT(calibration_result
,
453 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
455 case CLOCK_EVT_MODE_UNUSED
:
456 case CLOCK_EVT_MODE_SHUTDOWN
:
457 v
= apic_read(APIC_LVTT
);
458 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
459 apic_write(APIC_LVTT
, v
);
460 apic_write(APIC_TMICT
, 0xffffffff);
462 case CLOCK_EVT_MODE_RESUME
:
463 /* Nothing to do here */
467 local_irq_restore(flags
);
471 * Local APIC timer broadcast function
473 static void lapic_timer_broadcast(const struct cpumask
*mask
)
476 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
481 * Setup the local APIC timer for this CPU. Copy the initilized values
482 * of the boot CPU and register the clock event in the framework.
484 static void __cpuinit
setup_APIC_timer(void)
486 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
488 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
489 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
490 /* Make LAPIC timer preferrable over percpu HPET */
491 lapic_clockevent
.rating
= 150;
494 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
495 levt
->cpumask
= cpumask_of(smp_processor_id());
497 clockevents_register_device(levt
);
501 * In this functions we calibrate APIC bus clocks to the external timer.
503 * We want to do the calibration only once since we want to have local timer
504 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
507 * This was previously done by reading the PIT/HPET and waiting for a wrap
508 * around to find out, that a tick has elapsed. I have a box, where the PIT
509 * readout is broken, so it never gets out of the wait loop again. This was
510 * also reported by others.
512 * Monitoring the jiffies value is inaccurate and the clockevents
513 * infrastructure allows us to do a simple substitution of the interrupt
516 * The calibration routine also uses the pm_timer when possible, as the PIT
517 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
518 * back to normal later in the boot process).
521 #define LAPIC_CAL_LOOPS (HZ/10)
523 static __initdata
int lapic_cal_loops
= -1;
524 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
525 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
526 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
527 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
530 * Temporary interrupt handler.
532 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
534 unsigned long long tsc
= 0;
535 long tapic
= apic_read(APIC_TMCCT
);
536 unsigned long pm
= acpi_pm_read_early();
541 switch (lapic_cal_loops
++) {
543 lapic_cal_t1
= tapic
;
544 lapic_cal_tsc1
= tsc
;
546 lapic_cal_j1
= jiffies
;
549 case LAPIC_CAL_LOOPS
:
550 lapic_cal_t2
= tapic
;
551 lapic_cal_tsc2
= tsc
;
552 if (pm
< lapic_cal_pm1
)
553 pm
+= ACPI_PM_OVRRUN
;
555 lapic_cal_j2
= jiffies
;
561 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
563 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
564 const long pm_thresh
= pm_100ms
/ 100;
568 #ifndef CONFIG_X86_PM_TIMER
572 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
574 /* Check, if the PM timer is available */
578 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
580 if (deltapm
> (pm_100ms
- pm_thresh
) &&
581 deltapm
< (pm_100ms
+ pm_thresh
)) {
582 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
586 res
= (((u64
)deltapm
) * mult
) >> 22;
587 do_div(res
, 1000000);
588 pr_warning("APIC calibration not consistent "
589 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
591 /* Correct the lapic counter value */
592 res
= (((u64
)(*delta
)) * pm_100ms
);
593 do_div(res
, deltapm
);
594 pr_info("APIC delta adjusted to PM-Timer: "
595 "%lu (%ld)\n", (unsigned long)res
, *delta
);
598 /* Correct the tsc counter value */
600 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
601 do_div(res
, deltapm
);
602 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
603 "PM-Timer: %lu (%ld) \n",
604 (unsigned long)res
, *deltatsc
);
605 *deltatsc
= (long)res
;
611 static int __init
calibrate_APIC_clock(void)
613 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
614 void (*real_handler
)(struct clock_event_device
*dev
);
615 unsigned long deltaj
;
616 long delta
, deltatsc
;
617 int pm_referenced
= 0;
621 /* Replace the global interrupt handler */
622 real_handler
= global_clock_event
->event_handler
;
623 global_clock_event
->event_handler
= lapic_cal_handler
;
626 * Setup the APIC counter to maximum. There is no way the lapic
627 * can underflow in the 100ms detection time frame
629 __setup_APIC_LVTT(0xffffffff, 0, 0);
631 /* Let the interrupts run */
634 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
639 /* Restore the real event handler */
640 global_clock_event
->event_handler
= real_handler
;
642 /* Build delta t1-t2 as apic timer counts down */
643 delta
= lapic_cal_t1
- lapic_cal_t2
;
644 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
646 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
648 /* we trust the PM based calibration if possible */
649 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
652 /* Calculate the scaled math multiplication factor */
653 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
654 lapic_clockevent
.shift
);
655 lapic_clockevent
.max_delta_ns
=
656 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
657 lapic_clockevent
.min_delta_ns
=
658 clockevent_delta2ns(0xF, &lapic_clockevent
);
660 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
662 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
663 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
664 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
668 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
670 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
671 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
674 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
676 calibration_result
/ (1000000 / HZ
),
677 calibration_result
% (1000000 / HZ
));
680 * Do a sanity check on the APIC calibration result
682 if (calibration_result
< (1000000 / HZ
)) {
684 pr_warning("APIC frequency too slow, disabling apic timer\n");
688 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
691 * PM timer calibration failed or not turned on
692 * so lets try APIC timer based calibration
694 if (!pm_referenced
) {
695 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
698 * Setup the apic timer manually
700 levt
->event_handler
= lapic_cal_handler
;
701 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
702 lapic_cal_loops
= -1;
704 /* Let the interrupts run */
707 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
710 /* Stop the lapic timer */
711 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
714 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
715 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
717 /* Check, if the jiffies result is consistent */
718 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
719 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
721 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
725 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
726 pr_warning("APIC timer disabled due to verification failure\n");
734 * Setup the boot APIC
736 * Calibrate and verify the result.
738 void __init
setup_boot_APIC_clock(void)
741 * The local apic timer can be disabled via the kernel
742 * commandline or from the CPU detection code. Register the lapic
743 * timer as a dummy clock event source on SMP systems, so the
744 * broadcast mechanism is used. On UP systems simply ignore it.
746 if (disable_apic_timer
) {
747 pr_info("Disabling APIC timer\n");
748 /* No broadcast on UP ! */
749 if (num_possible_cpus() > 1) {
750 lapic_clockevent
.mult
= 1;
756 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
757 "calibrating APIC timer ...\n");
759 if (calibrate_APIC_clock()) {
760 /* No broadcast on UP ! */
761 if (num_possible_cpus() > 1)
767 * If nmi_watchdog is set to IO_APIC, we need the
768 * PIT/HPET going. Otherwise register lapic as a dummy
771 if (nmi_watchdog
!= NMI_IO_APIC
)
772 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
774 pr_warning("APIC timer registered as dummy,"
775 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
777 /* Setup the lapic or request the broadcast */
781 void __cpuinit
setup_secondary_APIC_clock(void)
787 * The guts of the apic timer interrupt
789 static void local_apic_timer_interrupt(void)
791 int cpu
= smp_processor_id();
792 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
795 * Normally we should not be here till LAPIC has been initialized but
796 * in some cases like kdump, its possible that there is a pending LAPIC
797 * timer interrupt from previous kernel's context and is delivered in
798 * new kernel the moment interrupts are enabled.
800 * Interrupts are enabled early and LAPIC is setup much later, hence
801 * its possible that when we get here evt->event_handler is NULL.
802 * Check for event_handler being NULL and discard the interrupt as
805 if (!evt
->event_handler
) {
806 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
808 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
813 * the NMI deadlock-detector uses this.
815 inc_irq_stat(apic_timer_irqs
);
817 evt
->event_handler(evt
);
821 * Local APIC timer interrupt. This is the most natural way for doing
822 * local interrupts, but local timer interrupts can be emulated by
823 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
825 * [ if a single-CPU system runs an SMP kernel then we call the local
826 * interrupt as well. Thus we cannot inline the local irq ... ]
828 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
830 struct pt_regs
*old_regs
= set_irq_regs(regs
);
833 * NOTE! We'd better ACK the irq immediately,
834 * because timer handling can be slow.
838 * update_process_times() expects us to have done irq_enter().
839 * Besides, if we don't timer interrupts ignore the global
840 * interrupt lock, which is the WrongThing (tm) to do.
844 local_apic_timer_interrupt();
847 set_irq_regs(old_regs
);
850 int setup_profiling_timer(unsigned int multiplier
)
856 * Local APIC start and shutdown
860 * clear_local_APIC - shutdown the local APIC
862 * This is called, when a CPU is disabled and before rebooting, so the state of
863 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
864 * leftovers during boot.
866 void clear_local_APIC(void)
871 /* APIC hasn't been mapped yet */
872 if (!x2apic_mode
&& !apic_phys
)
875 maxlvt
= lapic_get_maxlvt();
877 * Masking an LVT entry can trigger a local APIC error
878 * if the vector is zero. Mask LVTERR first to prevent this.
881 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
882 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
885 * Careful: we have to set masks only first to deassert
886 * any level-triggered sources.
888 v
= apic_read(APIC_LVTT
);
889 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
890 v
= apic_read(APIC_LVT0
);
891 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
892 v
= apic_read(APIC_LVT1
);
893 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
895 v
= apic_read(APIC_LVTPC
);
896 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
899 /* lets not touch this if we didn't frob it */
900 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
902 v
= apic_read(APIC_LVTTHMR
);
903 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
906 #ifdef CONFIG_X86_MCE_INTEL
908 v
= apic_read(APIC_LVTCMCI
);
909 if (!(v
& APIC_LVT_MASKED
))
910 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
915 * Clean APIC state for other OSs:
917 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
918 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
919 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
921 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
923 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
925 /* Integrated APIC (!82489DX) ? */
926 if (lapic_is_integrated()) {
928 /* Clear ESR due to Pentium errata 3AP and 11AP */
929 apic_write(APIC_ESR
, 0);
935 * disable_local_APIC - clear and disable the local APIC
937 void disable_local_APIC(void)
941 /* APIC hasn't been mapped yet */
948 * Disable APIC (implies clearing of registers
951 value
= apic_read(APIC_SPIV
);
952 value
&= ~APIC_SPIV_APIC_ENABLED
;
953 apic_write(APIC_SPIV
, value
);
957 * When LAPIC was disabled by the BIOS and enabled by the kernel,
958 * restore the disabled state.
960 if (enabled_via_apicbase
) {
963 rdmsr(MSR_IA32_APICBASE
, l
, h
);
964 l
&= ~MSR_IA32_APICBASE_ENABLE
;
965 wrmsr(MSR_IA32_APICBASE
, l
, h
);
971 * If Linux enabled the LAPIC against the BIOS default disable it down before
972 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
973 * not power-off. Additionally clear all LVT entries before disable_local_APIC
974 * for the case where Linux didn't enable the LAPIC.
976 void lapic_shutdown(void)
983 local_irq_save(flags
);
986 if (!enabled_via_apicbase
)
990 disable_local_APIC();
993 local_irq_restore(flags
);
997 * This is to verify that we're looking at a real local APIC.
998 * Check these against your board if the CPUs aren't getting
999 * started for no apparent reason.
1001 int __init
verify_local_APIC(void)
1003 unsigned int reg0
, reg1
;
1006 * The version register is read-only in a real APIC.
1008 reg0
= apic_read(APIC_LVR
);
1009 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1010 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1011 reg1
= apic_read(APIC_LVR
);
1012 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1015 * The two version reads above should print the same
1016 * numbers. If the second one is different, then we
1017 * poke at a non-APIC.
1023 * Check if the version looks reasonably.
1025 reg1
= GET_APIC_VERSION(reg0
);
1026 if (reg1
== 0x00 || reg1
== 0xff)
1028 reg1
= lapic_get_maxlvt();
1029 if (reg1
< 0x02 || reg1
== 0xff)
1033 * The ID register is read/write in a real APIC.
1035 reg0
= apic_read(APIC_ID
);
1036 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1037 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1038 reg1
= apic_read(APIC_ID
);
1039 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1040 apic_write(APIC_ID
, reg0
);
1041 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1045 * The next two are just to see if we have sane values.
1046 * They're only really relevant if we're in Virtual Wire
1047 * compatibility mode, but most boxes are anymore.
1049 reg0
= apic_read(APIC_LVT0
);
1050 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1051 reg1
= apic_read(APIC_LVT1
);
1052 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1058 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1060 void __init
sync_Arb_IDs(void)
1063 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1066 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1072 apic_wait_icr_idle();
1074 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1075 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1076 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1080 * An initial setup of the virtual wire mode.
1082 void __init
init_bsp_APIC(void)
1087 * Don't do the setup now if we have a SMP BIOS as the
1088 * through-I/O-APIC virtual wire mode might be active.
1090 if (smp_found_config
|| !cpu_has_apic
)
1094 * Do not trust the local APIC being empty at bootup.
1101 value
= apic_read(APIC_SPIV
);
1102 value
&= ~APIC_VECTOR_MASK
;
1103 value
|= APIC_SPIV_APIC_ENABLED
;
1105 #ifdef CONFIG_X86_32
1106 /* This bit is reserved on P4/Xeon and should be cleared */
1107 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1108 (boot_cpu_data
.x86
== 15))
1109 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1112 value
|= APIC_SPIV_FOCUS_DISABLED
;
1113 value
|= SPURIOUS_APIC_VECTOR
;
1114 apic_write(APIC_SPIV
, value
);
1117 * Set up the virtual wire mode.
1119 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1120 value
= APIC_DM_NMI
;
1121 if (!lapic_is_integrated()) /* 82489DX */
1122 value
|= APIC_LVT_LEVEL_TRIGGER
;
1123 apic_write(APIC_LVT1
, value
);
1126 static void __cpuinit
lapic_setup_esr(void)
1128 unsigned int oldvalue
, value
, maxlvt
;
1130 if (!lapic_is_integrated()) {
1131 pr_info("No ESR for 82489DX.\n");
1135 if (apic
->disable_esr
) {
1137 * Something untraceable is creating bad interrupts on
1138 * secondary quads ... for the moment, just leave the
1139 * ESR disabled - we can't do anything useful with the
1140 * errors anyway - mbligh
1142 pr_info("Leaving ESR disabled.\n");
1146 maxlvt
= lapic_get_maxlvt();
1147 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1148 apic_write(APIC_ESR
, 0);
1149 oldvalue
= apic_read(APIC_ESR
);
1151 /* enables sending errors */
1152 value
= ERROR_APIC_VECTOR
;
1153 apic_write(APIC_LVTERR
, value
);
1156 * spec says clear errors after enabling vector.
1159 apic_write(APIC_ESR
, 0);
1160 value
= apic_read(APIC_ESR
);
1161 if (value
!= oldvalue
)
1162 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1163 "vector: 0x%08x after: 0x%08x\n",
1169 * setup_local_APIC - setup the local APIC
1171 void __cpuinit
setup_local_APIC(void)
1177 arch_disable_smp_support();
1181 #ifdef CONFIG_X86_32
1182 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1183 if (lapic_is_integrated() && apic
->disable_esr
) {
1184 apic_write(APIC_ESR
, 0);
1185 apic_write(APIC_ESR
, 0);
1186 apic_write(APIC_ESR
, 0);
1187 apic_write(APIC_ESR
, 0);
1194 * Double-check whether this APIC is really registered.
1195 * This is meaningless in clustered apic mode, so we skip it.
1197 if (!apic
->apic_id_registered())
1201 * Intel recommends to set DFR, LDR and TPR before enabling
1202 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1203 * document number 292116). So here it goes...
1205 apic
->init_apic_ldr();
1208 * Set Task Priority to 'accept all'. We never change this
1211 value
= apic_read(APIC_TASKPRI
);
1212 value
&= ~APIC_TPRI_MASK
;
1213 apic_write(APIC_TASKPRI
, value
);
1216 * After a crash, we no longer service the interrupts and a pending
1217 * interrupt from previous kernel might still have ISR bit set.
1219 * Most probably by now CPU has serviced that pending interrupt and
1220 * it might not have done the ack_APIC_irq() because it thought,
1221 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1222 * does not clear the ISR bit and cpu thinks it has already serivced
1223 * the interrupt. Hence a vector might get locked. It was noticed
1224 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1226 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1227 value
= apic_read(APIC_ISR
+ i
*0x10);
1228 for (j
= 31; j
>= 0; j
--) {
1235 * Now that we are all set up, enable the APIC
1237 value
= apic_read(APIC_SPIV
);
1238 value
&= ~APIC_VECTOR_MASK
;
1242 value
|= APIC_SPIV_APIC_ENABLED
;
1244 #ifdef CONFIG_X86_32
1246 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1247 * certain networking cards. If high frequency interrupts are
1248 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1249 * entry is masked/unmasked at a high rate as well then sooner or
1250 * later IOAPIC line gets 'stuck', no more interrupts are received
1251 * from the device. If focus CPU is disabled then the hang goes
1254 * [ This bug can be reproduced easily with a level-triggered
1255 * PCI Ne2000 networking cards and PII/PIII processors, dual
1259 * Actually disabling the focus CPU check just makes the hang less
1260 * frequent as it makes the interrupt distributon model be more
1261 * like LRU than MRU (the short-term load is more even across CPUs).
1262 * See also the comment in end_level_ioapic_irq(). --macro
1266 * - enable focus processor (bit==0)
1267 * - 64bit mode always use processor focus
1268 * so no need to set it
1270 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1274 * Set spurious IRQ vector
1276 value
|= SPURIOUS_APIC_VECTOR
;
1277 apic_write(APIC_SPIV
, value
);
1280 * Set up LVT0, LVT1:
1282 * set up through-local-APIC on the BP's LINT0. This is not
1283 * strictly necessary in pure symmetric-IO mode, but sometimes
1284 * we delegate interrupts to the 8259A.
1287 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1289 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1290 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1291 value
= APIC_DM_EXTINT
;
1292 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1293 smp_processor_id());
1295 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1296 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1297 smp_processor_id());
1299 apic_write(APIC_LVT0
, value
);
1302 * only the BP should see the LINT1 NMI signal, obviously.
1304 if (!smp_processor_id())
1305 value
= APIC_DM_NMI
;
1307 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1308 if (!lapic_is_integrated()) /* 82489DX */
1309 value
|= APIC_LVT_LEVEL_TRIGGER
;
1310 apic_write(APIC_LVT1
, value
);
1314 #ifdef CONFIG_X86_MCE_INTEL
1315 /* Recheck CMCI information after local APIC is up on CPU #0 */
1316 if (smp_processor_id() == 0)
1321 void __cpuinit
end_local_APIC_setup(void)
1325 #ifdef CONFIG_X86_32
1328 /* Disable the local apic timer */
1329 value
= apic_read(APIC_LVTT
);
1330 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1331 apic_write(APIC_LVTT
, value
);
1335 setup_apic_nmi_watchdog(NULL
);
1339 #ifdef CONFIG_X86_X2APIC
1340 void check_x2apic(void)
1342 if (x2apic_enabled()) {
1343 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1344 x2apic_preenabled
= x2apic_mode
= 1;
1348 void enable_x2apic(void)
1355 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1356 if (!(msr
& X2APIC_ENABLE
)) {
1357 pr_info("Enabling x2apic\n");
1358 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1361 #endif /* CONFIG_X86_X2APIC */
1363 void __init
enable_IR_x2apic(void)
1365 #ifdef CONFIG_INTR_REMAP
1367 unsigned long flags
;
1368 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1370 ret
= dmar_table_init();
1372 pr_debug("dmar_table_init() failed with %d:\n", ret
);
1376 if (!intr_remapping_supported()) {
1377 pr_debug("intr-remapping not supported\n");
1382 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1383 pr_info("Skipped enabling intr-remap because of skipping "
1388 ioapic_entries
= alloc_ioapic_entries();
1389 if (!ioapic_entries
) {
1390 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1394 ret
= save_IO_APIC_setup(ioapic_entries
);
1396 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1400 local_irq_save(flags
);
1401 mask_IO_APIC_setup(ioapic_entries
);
1404 ret
= enable_intr_remapping(x2apic_supported());
1408 pr_info("Enabled Interrupt-remapping\n");
1410 if (x2apic_supported() && !x2apic_mode
) {
1413 pr_info("Enabled x2apic\n");
1419 * IR enabling failed
1421 restore_IO_APIC_setup(ioapic_entries
);
1424 local_irq_restore(flags
);
1428 free_ioapic_entries(ioapic_entries
);
1434 if (x2apic_preenabled
)
1435 panic("x2apic enabled by bios. But IR enabling failed");
1436 else if (cpu_has_x2apic
)
1437 pr_info("Not enabling x2apic,Intr-remapping\n");
1439 if (!cpu_has_x2apic
)
1442 if (x2apic_preenabled
)
1443 panic("x2apic enabled prior OS handover,"
1444 " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP");
1451 #ifdef CONFIG_X86_64
1453 * Detect and enable local APICs on non-SMP boards.
1454 * Original code written by Keir Fraser.
1455 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1456 * not correctly set up (usually the APIC timer won't work etc.)
1458 static int __init
detect_init_APIC(void)
1460 if (!cpu_has_apic
) {
1461 pr_info("No local APIC present\n");
1465 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1470 * Detect and initialize APIC
1472 static int __init
detect_init_APIC(void)
1476 /* Disabled by kernel option? */
1480 switch (boot_cpu_data
.x86_vendor
) {
1481 case X86_VENDOR_AMD
:
1482 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1483 (boot_cpu_data
.x86
>= 15))
1486 case X86_VENDOR_INTEL
:
1487 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1488 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1495 if (!cpu_has_apic
) {
1497 * Over-ride BIOS and try to enable the local APIC only if
1498 * "lapic" specified.
1500 if (!force_enable_local_apic
) {
1501 pr_info("Local APIC disabled by BIOS -- "
1502 "you can enable it with \"lapic\"\n");
1506 * Some BIOSes disable the local APIC in the APIC_BASE
1507 * MSR. This can only be done in software for Intel P6 or later
1508 * and AMD K7 (Model > 1) or later.
1510 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1511 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1512 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1513 l
&= ~MSR_IA32_APICBASE_BASE
;
1514 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1515 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1516 enabled_via_apicbase
= 1;
1520 * The APIC feature bit should now be enabled
1523 features
= cpuid_edx(1);
1524 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1525 pr_warning("Could not enable APIC!\n");
1528 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1529 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1531 /* The BIOS may have set up the APIC at some other address */
1532 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1533 if (l
& MSR_IA32_APICBASE_ENABLE
)
1534 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1536 pr_info("Found and enabled local APIC!\n");
1543 pr_info("No local APIC present or hardware disabled\n");
1548 #ifdef CONFIG_X86_64
1549 void __init
early_init_lapic_mapping(void)
1551 unsigned long phys_addr
;
1554 * If no local APIC can be found then go out
1555 * : it means there is no mpatable and MADT
1557 if (!smp_found_config
)
1560 phys_addr
= mp_lapic_addr
;
1562 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1563 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1564 APIC_BASE
, phys_addr
);
1567 * Fetch the APIC ID of the BSP in case we have a
1568 * default configuration (or the MP table is broken).
1570 boot_cpu_physical_apicid
= read_apic_id();
1575 * init_apic_mappings - initialize APIC mappings
1577 void __init
init_apic_mappings(void)
1579 unsigned int new_apicid
;
1582 boot_cpu_physical_apicid
= read_apic_id();
1586 /* If no local APIC can be found return early */
1587 if (!smp_found_config
&& detect_init_APIC()) {
1588 /* lets NOP'ify apic operations */
1589 pr_info("APIC: disable apic facility\n");
1592 apic_phys
= mp_lapic_addr
;
1595 * acpi lapic path already maps that address in
1596 * acpi_register_lapic_address()
1599 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1601 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1602 APIC_BASE
, apic_phys
);
1606 * Fetch the APIC ID of the BSP in case we have a
1607 * default configuration (or the MP table is broken).
1609 new_apicid
= read_apic_id();
1610 if (boot_cpu_physical_apicid
!= new_apicid
) {
1611 boot_cpu_physical_apicid
= new_apicid
;
1613 * yeah -- we lie about apic_version
1614 * in case if apic was disabled via boot option
1615 * but it's not a problem for SMP compiled kernel
1616 * since smp_sanity_check is prepared for such a case
1617 * and disable smp mode
1619 apic_version
[new_apicid
] =
1620 GET_APIC_VERSION(apic_read(APIC_LVR
));
1625 * This initializes the IO-APIC and APIC hardware if this is
1628 int apic_version
[MAX_APICS
];
1630 int __init
APIC_init_uniprocessor(void)
1633 pr_info("Apic disabled\n");
1636 #ifdef CONFIG_X86_64
1637 if (!cpu_has_apic
) {
1639 pr_info("Apic disabled by BIOS\n");
1643 if (!smp_found_config
&& !cpu_has_apic
)
1647 * Complain if the BIOS pretends there is one.
1649 if (!cpu_has_apic
&&
1650 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1651 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1652 boot_cpu_physical_apicid
);
1653 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1659 #ifdef CONFIG_X86_64
1660 default_setup_apic_routing();
1663 verify_local_APIC();
1666 #ifdef CONFIG_X86_64
1667 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1670 * Hack: In case of kdump, after a crash, kernel might be booting
1671 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1672 * might be zero if read from MP tables. Get it from LAPIC.
1674 # ifdef CONFIG_CRASH_DUMP
1675 boot_cpu_physical_apicid
= read_apic_id();
1678 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1681 #ifdef CONFIG_X86_IO_APIC
1683 * Now enable IO-APICs, actually call clear_IO_APIC
1684 * We need clear_IO_APIC before enabling error vector
1686 if (!skip_ioapic_setup
&& nr_ioapics
)
1690 end_local_APIC_setup();
1692 #ifdef CONFIG_X86_IO_APIC
1693 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1697 localise_nmi_watchdog();
1700 localise_nmi_watchdog();
1704 #ifdef CONFIG_X86_64
1705 check_nmi_watchdog();
1712 * Local APIC interrupts
1716 * This interrupt should _never_ happen with our APIC/SMP architecture
1718 void smp_spurious_interrupt(struct pt_regs
*regs
)
1725 * Check if this really is a spurious interrupt and ACK it
1726 * if it is a vectored one. Just in case...
1727 * Spurious interrupts should not be ACKed.
1729 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1730 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1733 inc_irq_stat(irq_spurious_count
);
1735 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1736 pr_info("spurious APIC interrupt on CPU#%d, "
1737 "should never happen.\n", smp_processor_id());
1742 * This interrupt should never happen with our APIC/SMP architecture
1744 void smp_error_interrupt(struct pt_regs
*regs
)
1750 /* First tickle the hardware, only then report what went on. -- REW */
1751 v
= apic_read(APIC_ESR
);
1752 apic_write(APIC_ESR
, 0);
1753 v1
= apic_read(APIC_ESR
);
1755 atomic_inc(&irq_err_count
);
1758 * Here is what the APIC error bits mean:
1760 * 1: Receive CS error
1761 * 2: Send accept error
1762 * 3: Receive accept error
1764 * 5: Send illegal vector
1765 * 6: Received illegal vector
1766 * 7: Illegal register address
1768 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1769 smp_processor_id(), v
, v1
);
1774 * connect_bsp_APIC - attach the APIC to the interrupt system
1776 void __init
connect_bsp_APIC(void)
1778 #ifdef CONFIG_X86_32
1781 * Do not trust the local APIC being empty at bootup.
1785 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1786 * local APIC to INT and NMI lines.
1788 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1789 "enabling APIC mode.\n");
1793 if (apic
->enable_apic_mode
)
1794 apic
->enable_apic_mode();
1798 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1799 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1801 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1804 void disconnect_bsp_APIC(int virt_wire_setup
)
1808 #ifdef CONFIG_X86_32
1811 * Put the board back into PIC mode (has an effect only on
1812 * certain older boards). Note that APIC interrupts, including
1813 * IPIs, won't work beyond this point! The only exception are
1816 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1817 "entering PIC mode.\n");
1823 /* Go back to Virtual Wire compatibility mode */
1825 /* For the spurious interrupt use vector F, and enable it */
1826 value
= apic_read(APIC_SPIV
);
1827 value
&= ~APIC_VECTOR_MASK
;
1828 value
|= APIC_SPIV_APIC_ENABLED
;
1830 apic_write(APIC_SPIV
, value
);
1832 if (!virt_wire_setup
) {
1834 * For LVT0 make it edge triggered, active high,
1835 * external and enabled
1837 value
= apic_read(APIC_LVT0
);
1838 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1839 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1840 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1841 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1842 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1843 apic_write(APIC_LVT0
, value
);
1846 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1850 * For LVT1 make it edge triggered, active high,
1853 value
= apic_read(APIC_LVT1
);
1854 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1855 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1856 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1857 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1858 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1859 apic_write(APIC_LVT1
, value
);
1862 void __cpuinit
generic_processor_info(int apicid
, int version
)
1869 if (version
== 0x0) {
1870 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1871 "fixing up to 0x10. (tell your hw vendor)\n",
1875 apic_version
[apicid
] = version
;
1877 if (num_processors
>= nr_cpu_ids
) {
1878 int max
= nr_cpu_ids
;
1879 int thiscpu
= max
+ disabled_cpus
;
1882 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1883 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1890 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1892 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1894 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1895 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1897 physid_set(apicid
, phys_cpu_present_map
);
1898 if (apicid
== boot_cpu_physical_apicid
) {
1900 * x86_bios_cpu_apicid is required to have processors listed
1901 * in same order as logical cpu numbers. Hence the first
1902 * entry is BSP, and so on.
1906 if (apicid
> max_physical_apicid
)
1907 max_physical_apicid
= apicid
;
1909 #ifdef CONFIG_X86_32
1911 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1912 * but we need to work other dependencies like SMP_SUSPEND etc
1913 * before this can be done without some confusion.
1914 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1915 * - Ashok Raj <ashok.raj@intel.com>
1917 if (max_physical_apicid
>= 8) {
1918 switch (boot_cpu_data
.x86_vendor
) {
1919 case X86_VENDOR_INTEL
:
1920 if (!APIC_XAPIC(version
)) {
1924 /* If P4 and above fall through */
1925 case X86_VENDOR_AMD
:
1931 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1932 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1933 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1936 set_cpu_possible(cpu
, true);
1937 set_cpu_present(cpu
, true);
1940 int hard_smp_processor_id(void)
1942 return read_apic_id();
1945 void default_init_apic_ldr(void)
1949 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1950 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1951 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1952 apic_write(APIC_LDR
, val
);
1955 #ifdef CONFIG_X86_32
1956 int default_apicid_to_node(int logical_apicid
)
1959 return apicid_2_node
[hard_smp_processor_id()];
1973 * 'active' is true if the local APIC was enabled by us and
1974 * not the BIOS; this signifies that we are also responsible
1975 * for disabling it before entering apm/acpi suspend
1978 /* r/w apic fields */
1979 unsigned int apic_id
;
1980 unsigned int apic_taskpri
;
1981 unsigned int apic_ldr
;
1982 unsigned int apic_dfr
;
1983 unsigned int apic_spiv
;
1984 unsigned int apic_lvtt
;
1985 unsigned int apic_lvtpc
;
1986 unsigned int apic_lvt0
;
1987 unsigned int apic_lvt1
;
1988 unsigned int apic_lvterr
;
1989 unsigned int apic_tmict
;
1990 unsigned int apic_tdcr
;
1991 unsigned int apic_thmr
;
1994 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1996 unsigned long flags
;
1999 if (!apic_pm_state
.active
)
2002 maxlvt
= lapic_get_maxlvt();
2004 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2005 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2006 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2007 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2008 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2009 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2011 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2012 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2013 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2014 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2015 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2016 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2017 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2019 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2022 local_irq_save(flags
);
2023 disable_local_APIC();
2025 if (intr_remapping_enabled
)
2026 disable_intr_remapping();
2028 local_irq_restore(flags
);
2032 static int lapic_resume(struct sys_device
*dev
)
2035 unsigned long flags
;
2038 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2040 if (!apic_pm_state
.active
)
2043 local_irq_save(flags
);
2044 if (intr_remapping_enabled
) {
2045 ioapic_entries
= alloc_ioapic_entries();
2046 if (!ioapic_entries
) {
2047 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2052 ret
= save_IO_APIC_setup(ioapic_entries
);
2054 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2055 free_ioapic_entries(ioapic_entries
);
2059 mask_IO_APIC_setup(ioapic_entries
);
2067 * Make sure the APICBASE points to the right address
2069 * FIXME! This will be wrong if we ever support suspend on
2070 * SMP! We'll need to do this as part of the CPU restore!
2072 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2073 l
&= ~MSR_IA32_APICBASE_BASE
;
2074 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2075 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2078 maxlvt
= lapic_get_maxlvt();
2079 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2080 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2081 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2082 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2083 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2084 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2085 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2086 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2087 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2089 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2092 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2093 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2094 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2095 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2096 apic_write(APIC_ESR
, 0);
2097 apic_read(APIC_ESR
);
2098 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2099 apic_write(APIC_ESR
, 0);
2100 apic_read(APIC_ESR
);
2102 if (intr_remapping_enabled
) {
2103 reenable_intr_remapping(x2apic_mode
);
2105 restore_IO_APIC_setup(ioapic_entries
);
2106 free_ioapic_entries(ioapic_entries
);
2109 local_irq_restore(flags
);
2115 * This device has no shutdown method - fully functioning local APICs
2116 * are needed on every CPU up until machine_halt/restart/poweroff.
2119 static struct sysdev_class lapic_sysclass
= {
2121 .resume
= lapic_resume
,
2122 .suspend
= lapic_suspend
,
2125 static struct sys_device device_lapic
= {
2127 .cls
= &lapic_sysclass
,
2130 static void __cpuinit
apic_pm_activate(void)
2132 apic_pm_state
.active
= 1;
2135 static int __init
init_lapic_sysfs(void)
2141 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2143 error
= sysdev_class_register(&lapic_sysclass
);
2145 error
= sysdev_register(&device_lapic
);
2149 /* local apic needs to resume before other devices access its registers. */
2150 core_initcall(init_lapic_sysfs
);
2152 #else /* CONFIG_PM */
2154 static void apic_pm_activate(void) { }
2156 #endif /* CONFIG_PM */
2158 #ifdef CONFIG_X86_64
2160 static int __cpuinit
apic_cluster_num(void)
2162 int i
, clusters
, zeros
;
2164 u16
*bios_cpu_apicid
;
2165 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2167 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2168 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2170 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2171 /* are we being called early in kernel startup? */
2172 if (bios_cpu_apicid
) {
2173 id
= bios_cpu_apicid
[i
];
2174 } else if (i
< nr_cpu_ids
) {
2176 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2182 if (id
!= BAD_APICID
)
2183 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2186 /* Problem: Partially populated chassis may not have CPUs in some of
2187 * the APIC clusters they have been allocated. Only present CPUs have
2188 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2189 * Since clusters are allocated sequentially, count zeros only if
2190 * they are bounded by ones.
2194 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2195 if (test_bit(i
, clustermap
)) {
2196 clusters
+= 1 + zeros
;
2205 static int __cpuinitdata multi_checked
;
2206 static int __cpuinitdata multi
;
2208 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2212 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2217 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2219 .callback
= set_multi
,
2220 .ident
= "IBM System Summit2",
2222 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2223 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2229 static void __cpuinit
dmi_check_multi(void)
2234 dmi_check_system(multi_dmi_table
);
2239 * apic_is_clustered_box() -- Check if we can expect good TSC
2241 * Thus far, the major user of this is IBM's Summit2 series:
2242 * Clustered boxes may have unsynced TSC problems if they are
2244 * Use DMI to check them
2246 __cpuinit
int apic_is_clustered_box(void)
2256 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2257 * not guaranteed to be synced between boards
2259 if (apic_cluster_num() > 1)
2267 * APIC command line parameters
2269 static int __init
setup_disableapic(char *arg
)
2272 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2275 early_param("disableapic", setup_disableapic
);
2277 /* same as disableapic, for compatibility */
2278 static int __init
setup_nolapic(char *arg
)
2280 return setup_disableapic(arg
);
2282 early_param("nolapic", setup_nolapic
);
2284 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2286 local_apic_timer_c2_ok
= 1;
2289 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2291 static int __init
parse_disable_apic_timer(char *arg
)
2293 disable_apic_timer
= 1;
2296 early_param("noapictimer", parse_disable_apic_timer
);
2298 static int __init
parse_nolapic_timer(char *arg
)
2300 disable_apic_timer
= 1;
2303 early_param("nolapic_timer", parse_nolapic_timer
);
2305 static int __init
apic_set_verbosity(char *arg
)
2308 #ifdef CONFIG_X86_64
2309 skip_ioapic_setup
= 0;
2315 if (strcmp("debug", arg
) == 0)
2316 apic_verbosity
= APIC_DEBUG
;
2317 else if (strcmp("verbose", arg
) == 0)
2318 apic_verbosity
= APIC_VERBOSE
;
2320 pr_warning("APIC Verbosity level %s not recognised"
2321 " use apic=verbose or apic=debug\n", arg
);
2327 early_param("apic", apic_set_verbosity
);
2329 static int __init
lapic_insert_resource(void)
2334 /* Put local APIC into the resource map. */
2335 lapic_resource
.start
= apic_phys
;
2336 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2337 insert_resource(&iomem_resource
, &lapic_resource
);
2343 * need call insert after e820_reserve_resources()
2344 * that is using request_resource
2346 late_initcall(lapic_insert_resource
);