2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/perf_counter.h>
38 #include <asm/pgalloc.h>
39 #include <asm/atomic.h>
40 #include <asm/mpspec.h>
41 #include <asm/i8253.h>
42 #include <asm/i8259.h>
43 #include <asm/proto.h>
52 unsigned int num_processors
;
54 unsigned disabled_cpus __cpuinitdata
;
56 /* Processor that is doing the boot up */
57 unsigned int boot_cpu_physical_apicid
= -1U;
60 * The highest APIC ID seen during enumeration.
62 * This determines the messaging protocol we can use: if all APIC IDs
63 * are in the 0 ... 7 range, then we can use logical addressing which
64 * has some performance advantages (better broadcasting).
66 * If there's an APIC ID above 8, we use physical addressing.
68 unsigned int max_physical_apicid
;
71 * Bitmask of physically existing CPUs:
73 physid_mask_t phys_cpu_present_map
;
76 * Map cpu index to physical APIC ID
78 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
79 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
85 * Knob to control our willingness to enable the local APIC.
89 static int force_enable_local_apic
;
91 * APIC command line parameters
93 static int __init
parse_lapic(char *arg
)
95 force_enable_local_apic
= 1;
98 early_param("lapic", parse_lapic
);
99 /* Local APIC was disabled by the BIOS and enabled by the kernel */
100 static int enabled_via_apicbase
;
105 static int apic_calibrate_pmtmr __initdata
;
106 static __init
int setup_apicpmtimer(char *s
)
108 apic_calibrate_pmtmr
= 1;
112 __setup("apicpmtimer", setup_apicpmtimer
);
115 #ifdef CONFIG_X86_X2APIC
117 /* x2apic enabled before OS handover */
118 static int x2apic_preenabled
;
119 static int disable_x2apic
;
120 static __init
int setup_nox2apic(char *str
)
123 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
126 early_param("nox2apic", setup_nox2apic
);
129 unsigned long mp_lapic_addr
;
131 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
132 static int disable_apic_timer __cpuinitdata
;
133 /* Local APIC timer works in C2 */
134 int local_apic_timer_c2_ok
;
135 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
137 int first_system_vector
= 0xfe;
140 * Debug level, exported for io_apic.c
142 unsigned int apic_verbosity
;
146 /* Have we found an MP table */
147 int smp_found_config
;
149 static struct resource lapic_resource
= {
150 .name
= "Local APIC",
151 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
154 static unsigned int calibration_result
;
156 static int lapic_next_event(unsigned long delta
,
157 struct clock_event_device
*evt
);
158 static void lapic_timer_setup(enum clock_event_mode mode
,
159 struct clock_event_device
*evt
);
160 static void lapic_timer_broadcast(const struct cpumask
*mask
);
161 static void apic_pm_activate(void);
164 * The local apic timer can be used for any function which is CPU local.
166 static struct clock_event_device lapic_clockevent
= {
168 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
169 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
171 .set_mode
= lapic_timer_setup
,
172 .set_next_event
= lapic_next_event
,
173 .broadcast
= lapic_timer_broadcast
,
177 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
179 static unsigned long apic_phys
;
182 * Get the LAPIC version
184 static inline int lapic_get_version(void)
186 return GET_APIC_VERSION(apic_read(APIC_LVR
));
190 * Check, if the APIC is integrated or a separate chip
192 static inline int lapic_is_integrated(void)
197 return APIC_INTEGRATED(lapic_get_version());
202 * Check, whether this is a modern or a first generation APIC
204 static int modern_apic(void)
206 /* AMD systems use old APIC versions, so check the CPU */
207 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
208 boot_cpu_data
.x86
>= 0xf)
210 return lapic_get_version() >= 0x14;
213 void native_apic_wait_icr_idle(void)
215 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
219 u32
native_safe_apic_wait_icr_idle(void)
226 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
230 } while (timeout
++ < 1000);
235 void native_apic_icr_write(u32 low
, u32 id
)
237 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
238 apic_write(APIC_ICR
, low
);
241 u64
native_apic_icr_read(void)
245 icr2
= apic_read(APIC_ICR2
);
246 icr1
= apic_read(APIC_ICR
);
248 return icr1
| ((u64
)icr2
<< 32);
252 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
254 void __cpuinit
enable_NMI_through_LVT0(void)
258 /* unmask and set to NMI */
261 /* Level triggered for 82489DX (32bit mode) */
262 if (!lapic_is_integrated())
263 v
|= APIC_LVT_LEVEL_TRIGGER
;
265 apic_write(APIC_LVT0
, v
);
270 * get_physical_broadcast - Get number of physical broadcast IDs
272 int get_physical_broadcast(void)
274 return modern_apic() ? 0xff : 0xf;
279 * lapic_get_maxlvt - get the maximum number of local vector table entries
281 int lapic_get_maxlvt(void)
285 v
= apic_read(APIC_LVR
);
287 * - we always have APIC integrated on 64bit mode
288 * - 82489DXs do not report # of LVT entries
290 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
298 #define APIC_DIVISOR 16
301 * This function sets up the local APIC timer, with a timeout of
302 * 'clocks' APIC bus clock. During calibration we actually call
303 * this function twice on the boot CPU, once with a bogus timeout
304 * value, second time for real. The other (noncalibrating) CPUs
305 * call this function only once, with the real, calibrated value.
307 * We do reads before writes even if unnecessary, to get around the
308 * P5 APIC double write bug.
310 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
312 unsigned int lvtt_value
, tmp_value
;
314 lvtt_value
= LOCAL_TIMER_VECTOR
;
316 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
317 if (!lapic_is_integrated())
318 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
321 lvtt_value
|= APIC_LVT_MASKED
;
323 apic_write(APIC_LVTT
, lvtt_value
);
328 tmp_value
= apic_read(APIC_TDCR
);
329 apic_write(APIC_TDCR
,
330 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
334 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
338 * Setup extended LVT, AMD specific (K8, family 10h)
340 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
341 * MCE interrupts are supported. Thus MCE offset must be set to 0.
343 * If mask=1, the LVT entry does not generate interrupts while mask=0
344 * enables the vector. See also the BKDGs.
347 #define APIC_EILVT_LVTOFF_MCE 0
348 #define APIC_EILVT_LVTOFF_IBS 1
350 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
352 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
353 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
358 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
360 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
361 return APIC_EILVT_LVTOFF_MCE
;
364 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
366 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
367 return APIC_EILVT_LVTOFF_IBS
;
369 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
372 * Program the next event, relative to now
374 static int lapic_next_event(unsigned long delta
,
375 struct clock_event_device
*evt
)
377 apic_write(APIC_TMICT
, delta
);
382 * Setup the lapic timer in periodic or oneshot mode
384 static void lapic_timer_setup(enum clock_event_mode mode
,
385 struct clock_event_device
*evt
)
390 /* Lapic used as dummy for broadcast ? */
391 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
394 local_irq_save(flags
);
397 case CLOCK_EVT_MODE_PERIODIC
:
398 case CLOCK_EVT_MODE_ONESHOT
:
399 __setup_APIC_LVTT(calibration_result
,
400 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
402 case CLOCK_EVT_MODE_UNUSED
:
403 case CLOCK_EVT_MODE_SHUTDOWN
:
404 v
= apic_read(APIC_LVTT
);
405 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
406 apic_write(APIC_LVTT
, v
);
407 apic_write(APIC_TMICT
, 0xffffffff);
409 case CLOCK_EVT_MODE_RESUME
:
410 /* Nothing to do here */
414 local_irq_restore(flags
);
418 * Local APIC timer broadcast function
420 static void lapic_timer_broadcast(const struct cpumask
*mask
)
423 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
428 * Setup the local APIC timer for this CPU. Copy the initilized values
429 * of the boot CPU and register the clock event in the framework.
431 static void __cpuinit
setup_APIC_timer(void)
433 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
435 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
436 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
437 /* Make LAPIC timer preferrable over percpu HPET */
438 lapic_clockevent
.rating
= 150;
441 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
442 levt
->cpumask
= cpumask_of(smp_processor_id());
444 clockevents_register_device(levt
);
448 * In this functions we calibrate APIC bus clocks to the external timer.
450 * We want to do the calibration only once since we want to have local timer
451 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
454 * This was previously done by reading the PIT/HPET and waiting for a wrap
455 * around to find out, that a tick has elapsed. I have a box, where the PIT
456 * readout is broken, so it never gets out of the wait loop again. This was
457 * also reported by others.
459 * Monitoring the jiffies value is inaccurate and the clockevents
460 * infrastructure allows us to do a simple substitution of the interrupt
463 * The calibration routine also uses the pm_timer when possible, as the PIT
464 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
465 * back to normal later in the boot process).
468 #define LAPIC_CAL_LOOPS (HZ/10)
470 static __initdata
int lapic_cal_loops
= -1;
471 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
472 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
473 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
474 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
477 * Temporary interrupt handler.
479 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
481 unsigned long long tsc
= 0;
482 long tapic
= apic_read(APIC_TMCCT
);
483 unsigned long pm
= acpi_pm_read_early();
488 switch (lapic_cal_loops
++) {
490 lapic_cal_t1
= tapic
;
491 lapic_cal_tsc1
= tsc
;
493 lapic_cal_j1
= jiffies
;
496 case LAPIC_CAL_LOOPS
:
497 lapic_cal_t2
= tapic
;
498 lapic_cal_tsc2
= tsc
;
499 if (pm
< lapic_cal_pm1
)
500 pm
+= ACPI_PM_OVRRUN
;
502 lapic_cal_j2
= jiffies
;
508 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
510 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
511 const long pm_thresh
= pm_100ms
/ 100;
515 #ifndef CONFIG_X86_PM_TIMER
519 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
521 /* Check, if the PM timer is available */
525 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
527 if (deltapm
> (pm_100ms
- pm_thresh
) &&
528 deltapm
< (pm_100ms
+ pm_thresh
)) {
529 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
533 res
= (((u64
)deltapm
) * mult
) >> 22;
534 do_div(res
, 1000000);
535 pr_warning("APIC calibration not consistent "
536 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
538 /* Correct the lapic counter value */
539 res
= (((u64
)(*delta
)) * pm_100ms
);
540 do_div(res
, deltapm
);
541 pr_info("APIC delta adjusted to PM-Timer: "
542 "%lu (%ld)\n", (unsigned long)res
, *delta
);
545 /* Correct the tsc counter value */
547 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
548 do_div(res
, deltapm
);
549 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
550 "PM-Timer: %lu (%ld) \n",
551 (unsigned long)res
, *deltatsc
);
552 *deltatsc
= (long)res
;
558 static int __init
calibrate_APIC_clock(void)
560 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
561 void (*real_handler
)(struct clock_event_device
*dev
);
562 unsigned long deltaj
;
563 long delta
, deltatsc
;
564 int pm_referenced
= 0;
568 /* Replace the global interrupt handler */
569 real_handler
= global_clock_event
->event_handler
;
570 global_clock_event
->event_handler
= lapic_cal_handler
;
573 * Setup the APIC counter to maximum. There is no way the lapic
574 * can underflow in the 100ms detection time frame
576 __setup_APIC_LVTT(0xffffffff, 0, 0);
578 /* Let the interrupts run */
581 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
586 /* Restore the real event handler */
587 global_clock_event
->event_handler
= real_handler
;
589 /* Build delta t1-t2 as apic timer counts down */
590 delta
= lapic_cal_t1
- lapic_cal_t2
;
591 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
593 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
595 /* we trust the PM based calibration if possible */
596 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
599 /* Calculate the scaled math multiplication factor */
600 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
601 lapic_clockevent
.shift
);
602 lapic_clockevent
.max_delta_ns
=
603 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
604 lapic_clockevent
.min_delta_ns
=
605 clockevent_delta2ns(0xF, &lapic_clockevent
);
607 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
609 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
610 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
611 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
615 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
617 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
618 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
621 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
623 calibration_result
/ (1000000 / HZ
),
624 calibration_result
% (1000000 / HZ
));
627 * Do a sanity check on the APIC calibration result
629 if (calibration_result
< (1000000 / HZ
)) {
631 pr_warning("APIC frequency too slow, disabling apic timer\n");
635 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
638 * PM timer calibration failed or not turned on
639 * so lets try APIC timer based calibration
641 if (!pm_referenced
) {
642 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
645 * Setup the apic timer manually
647 levt
->event_handler
= lapic_cal_handler
;
648 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
649 lapic_cal_loops
= -1;
651 /* Let the interrupts run */
654 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
657 /* Stop the lapic timer */
658 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
661 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
662 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
664 /* Check, if the jiffies result is consistent */
665 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
666 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
668 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
672 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
673 pr_warning("APIC timer disabled due to verification failure\n");
681 * Setup the boot APIC
683 * Calibrate and verify the result.
685 void __init
setup_boot_APIC_clock(void)
688 * The local apic timer can be disabled via the kernel
689 * commandline or from the CPU detection code. Register the lapic
690 * timer as a dummy clock event source on SMP systems, so the
691 * broadcast mechanism is used. On UP systems simply ignore it.
693 if (disable_apic_timer
) {
694 pr_info("Disabling APIC timer\n");
695 /* No broadcast on UP ! */
696 if (num_possible_cpus() > 1) {
697 lapic_clockevent
.mult
= 1;
703 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
704 "calibrating APIC timer ...\n");
706 if (calibrate_APIC_clock()) {
707 /* No broadcast on UP ! */
708 if (num_possible_cpus() > 1)
714 * If nmi_watchdog is set to IO_APIC, we need the
715 * PIT/HPET going. Otherwise register lapic as a dummy
718 if (nmi_watchdog
!= NMI_IO_APIC
)
719 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
721 pr_warning("APIC timer registered as dummy,"
722 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
724 /* Setup the lapic or request the broadcast */
728 void __cpuinit
setup_secondary_APIC_clock(void)
734 * The guts of the apic timer interrupt
736 static void local_apic_timer_interrupt(void)
738 int cpu
= smp_processor_id();
739 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
742 * Normally we should not be here till LAPIC has been initialized but
743 * in some cases like kdump, its possible that there is a pending LAPIC
744 * timer interrupt from previous kernel's context and is delivered in
745 * new kernel the moment interrupts are enabled.
747 * Interrupts are enabled early and LAPIC is setup much later, hence
748 * its possible that when we get here evt->event_handler is NULL.
749 * Check for event_handler being NULL and discard the interrupt as
752 if (!evt
->event_handler
) {
753 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
755 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
760 * the NMI deadlock-detector uses this.
762 inc_irq_stat(apic_timer_irqs
);
764 evt
->event_handler(evt
);
766 perf_counter_unthrottle();
770 * Local APIC timer interrupt. This is the most natural way for doing
771 * local interrupts, but local timer interrupts can be emulated by
772 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
774 * [ if a single-CPU system runs an SMP kernel then we call the local
775 * interrupt as well. Thus we cannot inline the local irq ... ]
777 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
779 struct pt_regs
*old_regs
= set_irq_regs(regs
);
782 * NOTE! We'd better ACK the irq immediately,
783 * because timer handling can be slow.
787 * update_process_times() expects us to have done irq_enter().
788 * Besides, if we don't timer interrupts ignore the global
789 * interrupt lock, which is the WrongThing (tm) to do.
793 local_apic_timer_interrupt();
796 set_irq_regs(old_regs
);
799 int setup_profiling_timer(unsigned int multiplier
)
805 * Local APIC start and shutdown
809 * clear_local_APIC - shutdown the local APIC
811 * This is called, when a CPU is disabled and before rebooting, so the state of
812 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
813 * leftovers during boot.
815 void clear_local_APIC(void)
820 /* APIC hasn't been mapped yet */
821 if (!x2apic
&& !apic_phys
)
824 maxlvt
= lapic_get_maxlvt();
826 * Masking an LVT entry can trigger a local APIC error
827 * if the vector is zero. Mask LVTERR first to prevent this.
830 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
831 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
834 * Careful: we have to set masks only first to deassert
835 * any level-triggered sources.
837 v
= apic_read(APIC_LVTT
);
838 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
839 v
= apic_read(APIC_LVT0
);
840 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
841 v
= apic_read(APIC_LVT1
);
842 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
844 v
= apic_read(APIC_LVTPC
);
845 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
848 /* lets not touch this if we didn't frob it */
849 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
851 v
= apic_read(APIC_LVTTHMR
);
852 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
855 #ifdef CONFIG_X86_MCE_INTEL
857 v
= apic_read(APIC_LVTCMCI
);
858 if (!(v
& APIC_LVT_MASKED
))
859 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
864 * Clean APIC state for other OSs:
866 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
867 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
868 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
870 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
872 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
874 /* Integrated APIC (!82489DX) ? */
875 if (lapic_is_integrated()) {
877 /* Clear ESR due to Pentium errata 3AP and 11AP */
878 apic_write(APIC_ESR
, 0);
884 * disable_local_APIC - clear and disable the local APIC
886 void disable_local_APIC(void)
890 /* APIC hasn't been mapped yet */
897 * Disable APIC (implies clearing of registers
900 value
= apic_read(APIC_SPIV
);
901 value
&= ~APIC_SPIV_APIC_ENABLED
;
902 apic_write(APIC_SPIV
, value
);
906 * When LAPIC was disabled by the BIOS and enabled by the kernel,
907 * restore the disabled state.
909 if (enabled_via_apicbase
) {
912 rdmsr(MSR_IA32_APICBASE
, l
, h
);
913 l
&= ~MSR_IA32_APICBASE_ENABLE
;
914 wrmsr(MSR_IA32_APICBASE
, l
, h
);
920 * If Linux enabled the LAPIC against the BIOS default disable it down before
921 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
922 * not power-off. Additionally clear all LVT entries before disable_local_APIC
923 * for the case where Linux didn't enable the LAPIC.
925 void lapic_shutdown(void)
932 local_irq_save(flags
);
935 if (!enabled_via_apicbase
)
939 disable_local_APIC();
942 local_irq_restore(flags
);
946 * This is to verify that we're looking at a real local APIC.
947 * Check these against your board if the CPUs aren't getting
948 * started for no apparent reason.
950 int __init
verify_local_APIC(void)
952 unsigned int reg0
, reg1
;
955 * The version register is read-only in a real APIC.
957 reg0
= apic_read(APIC_LVR
);
958 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
959 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
960 reg1
= apic_read(APIC_LVR
);
961 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
964 * The two version reads above should print the same
965 * numbers. If the second one is different, then we
966 * poke at a non-APIC.
972 * Check if the version looks reasonably.
974 reg1
= GET_APIC_VERSION(reg0
);
975 if (reg1
== 0x00 || reg1
== 0xff)
977 reg1
= lapic_get_maxlvt();
978 if (reg1
< 0x02 || reg1
== 0xff)
982 * The ID register is read/write in a real APIC.
984 reg0
= apic_read(APIC_ID
);
985 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
986 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
987 reg1
= apic_read(APIC_ID
);
988 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
989 apic_write(APIC_ID
, reg0
);
990 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
994 * The next two are just to see if we have sane values.
995 * They're only really relevant if we're in Virtual Wire
996 * compatibility mode, but most boxes are anymore.
998 reg0
= apic_read(APIC_LVT0
);
999 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1000 reg1
= apic_read(APIC_LVT1
);
1001 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1007 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1009 void __init
sync_Arb_IDs(void)
1012 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1015 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1021 apic_wait_icr_idle();
1023 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1024 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1025 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1029 * An initial setup of the virtual wire mode.
1031 void __init
init_bsp_APIC(void)
1036 * Don't do the setup now if we have a SMP BIOS as the
1037 * through-I/O-APIC virtual wire mode might be active.
1039 if (smp_found_config
|| !cpu_has_apic
)
1043 * Do not trust the local APIC being empty at bootup.
1050 value
= apic_read(APIC_SPIV
);
1051 value
&= ~APIC_VECTOR_MASK
;
1052 value
|= APIC_SPIV_APIC_ENABLED
;
1054 #ifdef CONFIG_X86_32
1055 /* This bit is reserved on P4/Xeon and should be cleared */
1056 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1057 (boot_cpu_data
.x86
== 15))
1058 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1061 value
|= APIC_SPIV_FOCUS_DISABLED
;
1062 value
|= SPURIOUS_APIC_VECTOR
;
1063 apic_write(APIC_SPIV
, value
);
1066 * Set up the virtual wire mode.
1068 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1069 value
= APIC_DM_NMI
;
1070 if (!lapic_is_integrated()) /* 82489DX */
1071 value
|= APIC_LVT_LEVEL_TRIGGER
;
1072 apic_write(APIC_LVT1
, value
);
1075 static void __cpuinit
lapic_setup_esr(void)
1077 unsigned int oldvalue
, value
, maxlvt
;
1079 if (!lapic_is_integrated()) {
1080 pr_info("No ESR for 82489DX.\n");
1084 if (apic
->disable_esr
) {
1086 * Something untraceable is creating bad interrupts on
1087 * secondary quads ... for the moment, just leave the
1088 * ESR disabled - we can't do anything useful with the
1089 * errors anyway - mbligh
1091 pr_info("Leaving ESR disabled.\n");
1095 maxlvt
= lapic_get_maxlvt();
1096 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1097 apic_write(APIC_ESR
, 0);
1098 oldvalue
= apic_read(APIC_ESR
);
1100 /* enables sending errors */
1101 value
= ERROR_APIC_VECTOR
;
1102 apic_write(APIC_LVTERR
, value
);
1105 * spec says clear errors after enabling vector.
1108 apic_write(APIC_ESR
, 0);
1109 value
= apic_read(APIC_ESR
);
1110 if (value
!= oldvalue
)
1111 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1112 "vector: 0x%08x after: 0x%08x\n",
1118 * setup_local_APIC - setup the local APIC
1120 void __cpuinit
setup_local_APIC(void)
1126 arch_disable_smp_support();
1130 #ifdef CONFIG_X86_32
1131 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1132 if (lapic_is_integrated() && apic
->disable_esr
) {
1133 apic_write(APIC_ESR
, 0);
1134 apic_write(APIC_ESR
, 0);
1135 apic_write(APIC_ESR
, 0);
1136 apic_write(APIC_ESR
, 0);
1139 perf_counters_lapic_init(0);
1144 * Double-check whether this APIC is really registered.
1145 * This is meaningless in clustered apic mode, so we skip it.
1147 if (!apic
->apic_id_registered())
1151 * Intel recommends to set DFR, LDR and TPR before enabling
1152 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1153 * document number 292116). So here it goes...
1155 apic
->init_apic_ldr();
1158 * Set Task Priority to 'accept all'. We never change this
1161 value
= apic_read(APIC_TASKPRI
);
1162 value
&= ~APIC_TPRI_MASK
;
1163 apic_write(APIC_TASKPRI
, value
);
1166 * After a crash, we no longer service the interrupts and a pending
1167 * interrupt from previous kernel might still have ISR bit set.
1169 * Most probably by now CPU has serviced that pending interrupt and
1170 * it might not have done the ack_APIC_irq() because it thought,
1171 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1172 * does not clear the ISR bit and cpu thinks it has already serivced
1173 * the interrupt. Hence a vector might get locked. It was noticed
1174 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1176 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1177 value
= apic_read(APIC_ISR
+ i
*0x10);
1178 for (j
= 31; j
>= 0; j
--) {
1185 * Now that we are all set up, enable the APIC
1187 value
= apic_read(APIC_SPIV
);
1188 value
&= ~APIC_VECTOR_MASK
;
1192 value
|= APIC_SPIV_APIC_ENABLED
;
1194 #ifdef CONFIG_X86_32
1196 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1197 * certain networking cards. If high frequency interrupts are
1198 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1199 * entry is masked/unmasked at a high rate as well then sooner or
1200 * later IOAPIC line gets 'stuck', no more interrupts are received
1201 * from the device. If focus CPU is disabled then the hang goes
1204 * [ This bug can be reproduced easily with a level-triggered
1205 * PCI Ne2000 networking cards and PII/PIII processors, dual
1209 * Actually disabling the focus CPU check just makes the hang less
1210 * frequent as it makes the interrupt distributon model be more
1211 * like LRU than MRU (the short-term load is more even across CPUs).
1212 * See also the comment in end_level_ioapic_irq(). --macro
1216 * - enable focus processor (bit==0)
1217 * - 64bit mode always use processor focus
1218 * so no need to set it
1220 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1224 * Set spurious IRQ vector
1226 value
|= SPURIOUS_APIC_VECTOR
;
1227 apic_write(APIC_SPIV
, value
);
1230 * Set up LVT0, LVT1:
1232 * set up through-local-APIC on the BP's LINT0. This is not
1233 * strictly necessary in pure symmetric-IO mode, but sometimes
1234 * we delegate interrupts to the 8259A.
1237 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1239 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1240 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1241 value
= APIC_DM_EXTINT
;
1242 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1243 smp_processor_id());
1245 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1246 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1247 smp_processor_id());
1249 apic_write(APIC_LVT0
, value
);
1252 * only the BP should see the LINT1 NMI signal, obviously.
1254 if (!smp_processor_id())
1255 value
= APIC_DM_NMI
;
1257 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1258 if (!lapic_is_integrated()) /* 82489DX */
1259 value
|= APIC_LVT_LEVEL_TRIGGER
;
1260 apic_write(APIC_LVT1
, value
);
1264 #ifdef CONFIG_X86_MCE_INTEL
1265 /* Recheck CMCI information after local APIC is up on CPU #0 */
1266 if (smp_processor_id() == 0)
1271 void __cpuinit
end_local_APIC_setup(void)
1275 #ifdef CONFIG_X86_32
1278 /* Disable the local apic timer */
1279 value
= apic_read(APIC_LVTT
);
1280 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1281 apic_write(APIC_LVTT
, value
);
1285 setup_apic_nmi_watchdog(NULL
);
1289 #ifdef CONFIG_X86_X2APIC
1290 void check_x2apic(void)
1292 if (x2apic_enabled()) {
1293 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1294 x2apic_preenabled
= x2apic
= 1;
1298 void enable_x2apic(void)
1305 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1306 if (!(msr
& X2APIC_ENABLE
)) {
1307 pr_info("Enabling x2apic\n");
1308 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1312 void __init
enable_IR_x2apic(void)
1314 #ifdef CONFIG_INTR_REMAP
1316 unsigned long flags
;
1317 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1319 if (!cpu_has_x2apic
)
1322 if (!x2apic_preenabled
&& disable_x2apic
) {
1323 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1324 "because of nox2apic\n");
1328 if (x2apic_preenabled
&& disable_x2apic
)
1329 panic("Bios already enabled x2apic, can't enforce nox2apic");
1331 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1332 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1333 "because of skipping io-apic setup\n");
1337 ret
= dmar_table_init();
1339 pr_info("dmar_table_init() failed with %d:\n", ret
);
1341 if (x2apic_preenabled
)
1342 panic("x2apic enabled by bios. But IR enabling failed");
1344 pr_info("Not enabling x2apic,Intr-remapping\n");
1348 ioapic_entries
= alloc_ioapic_entries();
1349 if (!ioapic_entries
) {
1350 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1354 ret
= save_IO_APIC_setup(ioapic_entries
);
1356 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1360 local_irq_save(flags
);
1361 mask_IO_APIC_setup(ioapic_entries
);
1364 ret
= enable_intr_remapping(EIM_32BIT_APIC_ID
);
1366 if (ret
&& x2apic_preenabled
) {
1367 local_irq_restore(flags
);
1368 panic("x2apic enabled by bios. But IR enabling failed");
1382 * IR enabling failed
1384 restore_IO_APIC_setup(ioapic_entries
);
1386 reinit_intr_remapped_IO_APIC(x2apic_preenabled
, ioapic_entries
);
1389 local_irq_restore(flags
);
1393 if (!x2apic_preenabled
)
1394 pr_info("Enabled x2apic and interrupt-remapping\n");
1396 pr_info("Enabled Interrupt-remapping\n");
1398 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1400 free_ioapic_entries(ioapic_entries
);
1402 if (!cpu_has_x2apic
)
1405 if (x2apic_preenabled
)
1406 panic("x2apic enabled prior OS handover,"
1407 " enable CONFIG_INTR_REMAP");
1409 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1415 #endif /* CONFIG_X86_X2APIC */
1417 #ifdef CONFIG_X86_64
1419 * Detect and enable local APICs on non-SMP boards.
1420 * Original code written by Keir Fraser.
1421 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1422 * not correctly set up (usually the APIC timer won't work etc.)
1424 static int __init
detect_init_APIC(void)
1426 if (!cpu_has_apic
) {
1427 pr_info("No local APIC present\n");
1431 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1432 boot_cpu_physical_apicid
= 0;
1437 * Detect and initialize APIC
1439 static int __init
detect_init_APIC(void)
1443 /* Disabled by kernel option? */
1447 switch (boot_cpu_data
.x86_vendor
) {
1448 case X86_VENDOR_AMD
:
1449 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1450 (boot_cpu_data
.x86
>= 15))
1453 case X86_VENDOR_INTEL
:
1454 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1455 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1462 if (!cpu_has_apic
) {
1464 * Over-ride BIOS and try to enable the local APIC only if
1465 * "lapic" specified.
1467 if (!force_enable_local_apic
) {
1468 pr_info("Local APIC disabled by BIOS -- "
1469 "you can enable it with \"lapic\"\n");
1473 * Some BIOSes disable the local APIC in the APIC_BASE
1474 * MSR. This can only be done in software for Intel P6 or later
1475 * and AMD K7 (Model > 1) or later.
1477 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1478 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1479 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1480 l
&= ~MSR_IA32_APICBASE_BASE
;
1481 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1482 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1483 enabled_via_apicbase
= 1;
1487 * The APIC feature bit should now be enabled
1490 features
= cpuid_edx(1);
1491 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1492 pr_warning("Could not enable APIC!\n");
1495 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1496 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1498 /* The BIOS may have set up the APIC at some other address */
1499 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1500 if (l
& MSR_IA32_APICBASE_ENABLE
)
1501 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1503 pr_info("Found and enabled local APIC!\n");
1510 pr_info("No local APIC present or hardware disabled\n");
1515 #ifdef CONFIG_X86_64
1516 void __init
early_init_lapic_mapping(void)
1518 unsigned long phys_addr
;
1521 * If no local APIC can be found then go out
1522 * : it means there is no mpatable and MADT
1524 if (!smp_found_config
)
1527 phys_addr
= mp_lapic_addr
;
1529 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1530 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1531 APIC_BASE
, phys_addr
);
1534 * Fetch the APIC ID of the BSP in case we have a
1535 * default configuration (or the MP table is broken).
1537 boot_cpu_physical_apicid
= read_apic_id();
1542 * init_apic_mappings - initialize APIC mappings
1544 void __init
init_apic_mappings(void)
1547 boot_cpu_physical_apicid
= read_apic_id();
1552 * If no local APIC can be found then set up a fake all
1553 * zeroes page to simulate the local APIC and another
1554 * one for the IO-APIC.
1556 if (!smp_found_config
&& detect_init_APIC()) {
1557 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1558 apic_phys
= __pa(apic_phys
);
1560 apic_phys
= mp_lapic_addr
;
1562 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1563 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1564 APIC_BASE
, apic_phys
);
1567 * Fetch the APIC ID of the BSP in case we have a
1568 * default configuration (or the MP table is broken).
1570 if (boot_cpu_physical_apicid
== -1U)
1571 boot_cpu_physical_apicid
= read_apic_id();
1575 * This initializes the IO-APIC and APIC hardware if this is
1578 int apic_version
[MAX_APICS
];
1580 int __init
APIC_init_uniprocessor(void)
1583 pr_info("Apic disabled\n");
1586 #ifdef CONFIG_X86_64
1587 if (!cpu_has_apic
) {
1589 pr_info("Apic disabled by BIOS\n");
1593 if (!smp_found_config
&& !cpu_has_apic
)
1597 * Complain if the BIOS pretends there is one.
1599 if (!cpu_has_apic
&&
1600 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1601 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1602 boot_cpu_physical_apicid
);
1603 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1609 #ifdef CONFIG_X86_64
1610 default_setup_apic_routing();
1613 verify_local_APIC();
1616 #ifdef CONFIG_X86_64
1617 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1620 * Hack: In case of kdump, after a crash, kernel might be booting
1621 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1622 * might be zero if read from MP tables. Get it from LAPIC.
1624 # ifdef CONFIG_CRASH_DUMP
1625 boot_cpu_physical_apicid
= read_apic_id();
1628 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1631 #ifdef CONFIG_X86_IO_APIC
1633 * Now enable IO-APICs, actually call clear_IO_APIC
1634 * We need clear_IO_APIC before enabling error vector
1636 if (!skip_ioapic_setup
&& nr_ioapics
)
1640 end_local_APIC_setup();
1642 #ifdef CONFIG_X86_IO_APIC
1643 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1647 localise_nmi_watchdog();
1650 localise_nmi_watchdog();
1654 #ifdef CONFIG_X86_64
1655 check_nmi_watchdog();
1662 * Local APIC interrupts
1666 * This interrupt should _never_ happen with our APIC/SMP architecture
1668 void smp_spurious_interrupt(struct pt_regs
*regs
)
1675 * Check if this really is a spurious interrupt and ACK it
1676 * if it is a vectored one. Just in case...
1677 * Spurious interrupts should not be ACKed.
1679 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1680 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1683 inc_irq_stat(irq_spurious_count
);
1685 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1686 pr_info("spurious APIC interrupt on CPU#%d, "
1687 "should never happen.\n", smp_processor_id());
1692 * This interrupt should never happen with our APIC/SMP architecture
1694 void smp_error_interrupt(struct pt_regs
*regs
)
1700 /* First tickle the hardware, only then report what went on. -- REW */
1701 v
= apic_read(APIC_ESR
);
1702 apic_write(APIC_ESR
, 0);
1703 v1
= apic_read(APIC_ESR
);
1705 atomic_inc(&irq_err_count
);
1708 * Here is what the APIC error bits mean:
1710 * 1: Receive CS error
1711 * 2: Send accept error
1712 * 3: Receive accept error
1714 * 5: Send illegal vector
1715 * 6: Received illegal vector
1716 * 7: Illegal register address
1718 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1719 smp_processor_id(), v
, v1
);
1724 * connect_bsp_APIC - attach the APIC to the interrupt system
1726 void __init
connect_bsp_APIC(void)
1728 #ifdef CONFIG_X86_32
1731 * Do not trust the local APIC being empty at bootup.
1735 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1736 * local APIC to INT and NMI lines.
1738 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1739 "enabling APIC mode.\n");
1744 if (apic
->enable_apic_mode
)
1745 apic
->enable_apic_mode();
1749 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1750 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1752 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1755 void disconnect_bsp_APIC(int virt_wire_setup
)
1759 #ifdef CONFIG_X86_32
1762 * Put the board back into PIC mode (has an effect only on
1763 * certain older boards). Note that APIC interrupts, including
1764 * IPIs, won't work beyond this point! The only exception are
1767 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1768 "entering PIC mode.\n");
1775 /* Go back to Virtual Wire compatibility mode */
1777 /* For the spurious interrupt use vector F, and enable it */
1778 value
= apic_read(APIC_SPIV
);
1779 value
&= ~APIC_VECTOR_MASK
;
1780 value
|= APIC_SPIV_APIC_ENABLED
;
1782 apic_write(APIC_SPIV
, value
);
1784 if (!virt_wire_setup
) {
1786 * For LVT0 make it edge triggered, active high,
1787 * external and enabled
1789 value
= apic_read(APIC_LVT0
);
1790 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1791 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1792 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1793 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1794 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1795 apic_write(APIC_LVT0
, value
);
1798 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1802 * For LVT1 make it edge triggered, active high,
1805 value
= apic_read(APIC_LVT1
);
1806 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1807 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1808 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1809 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1810 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1811 apic_write(APIC_LVT1
, value
);
1814 void __cpuinit
generic_processor_info(int apicid
, int version
)
1821 if (version
== 0x0) {
1822 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1823 "fixing up to 0x10. (tell your hw vendor)\n",
1827 apic_version
[apicid
] = version
;
1829 if (num_processors
>= nr_cpu_ids
) {
1830 int max
= nr_cpu_ids
;
1831 int thiscpu
= max
+ disabled_cpus
;
1834 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1835 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1842 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1844 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1846 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1847 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1849 physid_set(apicid
, phys_cpu_present_map
);
1850 if (apicid
== boot_cpu_physical_apicid
) {
1852 * x86_bios_cpu_apicid is required to have processors listed
1853 * in same order as logical cpu numbers. Hence the first
1854 * entry is BSP, and so on.
1858 if (apicid
> max_physical_apicid
)
1859 max_physical_apicid
= apicid
;
1861 #ifdef CONFIG_X86_32
1863 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1864 * but we need to work other dependencies like SMP_SUSPEND etc
1865 * before this can be done without some confusion.
1866 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1867 * - Ashok Raj <ashok.raj@intel.com>
1869 if (max_physical_apicid
>= 8) {
1870 switch (boot_cpu_data
.x86_vendor
) {
1871 case X86_VENDOR_INTEL
:
1872 if (!APIC_XAPIC(version
)) {
1876 /* If P4 and above fall through */
1877 case X86_VENDOR_AMD
:
1883 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1884 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1885 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1888 set_cpu_possible(cpu
, true);
1889 set_cpu_present(cpu
, true);
1892 int hard_smp_processor_id(void)
1894 return read_apic_id();
1897 void default_init_apic_ldr(void)
1901 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1902 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1903 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1904 apic_write(APIC_LDR
, val
);
1907 #ifdef CONFIG_X86_32
1908 int default_apicid_to_node(int logical_apicid
)
1911 return apicid_2_node
[hard_smp_processor_id()];
1925 * 'active' is true if the local APIC was enabled by us and
1926 * not the BIOS; this signifies that we are also responsible
1927 * for disabling it before entering apm/acpi suspend
1930 /* r/w apic fields */
1931 unsigned int apic_id
;
1932 unsigned int apic_taskpri
;
1933 unsigned int apic_ldr
;
1934 unsigned int apic_dfr
;
1935 unsigned int apic_spiv
;
1936 unsigned int apic_lvtt
;
1937 unsigned int apic_lvtpc
;
1938 unsigned int apic_lvt0
;
1939 unsigned int apic_lvt1
;
1940 unsigned int apic_lvterr
;
1941 unsigned int apic_tmict
;
1942 unsigned int apic_tdcr
;
1943 unsigned int apic_thmr
;
1946 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1948 unsigned long flags
;
1951 if (!apic_pm_state
.active
)
1954 maxlvt
= lapic_get_maxlvt();
1956 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1957 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1958 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1959 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1960 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1961 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1963 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1964 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1965 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1966 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1967 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1968 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1969 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1971 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1974 local_irq_save(flags
);
1975 disable_local_APIC();
1976 #ifdef CONFIG_INTR_REMAP
1977 if (intr_remapping_enabled
)
1978 disable_intr_remapping();
1980 local_irq_restore(flags
);
1984 static int lapic_resume(struct sys_device
*dev
)
1987 unsigned long flags
;
1990 #ifdef CONFIG_INTR_REMAP
1992 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1994 if (!apic_pm_state
.active
)
1997 local_irq_save(flags
);
1999 ioapic_entries
= alloc_ioapic_entries();
2000 if (!ioapic_entries
) {
2001 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2005 ret
= save_IO_APIC_setup(ioapic_entries
);
2007 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2008 free_ioapic_entries(ioapic_entries
);
2012 mask_IO_APIC_setup(ioapic_entries
);
2017 if (!apic_pm_state
.active
)
2020 local_irq_save(flags
);
2027 * Make sure the APICBASE points to the right address
2029 * FIXME! This will be wrong if we ever support suspend on
2030 * SMP! We'll need to do this as part of the CPU restore!
2032 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2033 l
&= ~MSR_IA32_APICBASE_BASE
;
2034 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2035 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2038 maxlvt
= lapic_get_maxlvt();
2039 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2040 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2041 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2042 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2043 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2044 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2045 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2046 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2047 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2049 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2052 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2053 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2054 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2055 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2056 apic_write(APIC_ESR
, 0);
2057 apic_read(APIC_ESR
);
2058 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2059 apic_write(APIC_ESR
, 0);
2060 apic_read(APIC_ESR
);
2062 #ifdef CONFIG_INTR_REMAP
2063 if (intr_remapping_enabled
)
2064 reenable_intr_remapping(EIM_32BIT_APIC_ID
);
2068 restore_IO_APIC_setup(ioapic_entries
);
2069 free_ioapic_entries(ioapic_entries
);
2073 local_irq_restore(flags
);
2080 * This device has no shutdown method - fully functioning local APICs
2081 * are needed on every CPU up until machine_halt/restart/poweroff.
2084 static struct sysdev_class lapic_sysclass
= {
2086 .resume
= lapic_resume
,
2087 .suspend
= lapic_suspend
,
2090 static struct sys_device device_lapic
= {
2092 .cls
= &lapic_sysclass
,
2095 static void __cpuinit
apic_pm_activate(void)
2097 apic_pm_state
.active
= 1;
2100 static int __init
init_lapic_sysfs(void)
2106 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2108 error
= sysdev_class_register(&lapic_sysclass
);
2110 error
= sysdev_register(&device_lapic
);
2114 /* local apic needs to resume before other devices access its registers. */
2115 core_initcall(init_lapic_sysfs
);
2117 #else /* CONFIG_PM */
2119 static void apic_pm_activate(void) { }
2121 #endif /* CONFIG_PM */
2123 #ifdef CONFIG_X86_64
2125 * apic_is_clustered_box() -- Check if we can expect good TSC
2127 * Thus far, the major user of this is IBM's Summit2 series:
2129 * Clustered boxes may have unsynced TSC problems if they are
2130 * multi-chassis. Use available data to take a good guess.
2131 * If in doubt, go HPET.
2133 __cpuinit
int apic_is_clustered_box(void)
2135 int i
, clusters
, zeros
;
2137 u16
*bios_cpu_apicid
;
2138 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2141 * there is not this kind of box with AMD CPU yet.
2142 * Some AMD box with quadcore cpu and 8 sockets apicid
2143 * will be [4, 0x23] or [8, 0x27] could be thought to
2144 * vsmp box still need checking...
2146 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2149 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2150 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2152 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2153 /* are we being called early in kernel startup? */
2154 if (bios_cpu_apicid
) {
2155 id
= bios_cpu_apicid
[i
];
2156 } else if (i
< nr_cpu_ids
) {
2158 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2164 if (id
!= BAD_APICID
)
2165 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2168 /* Problem: Partially populated chassis may not have CPUs in some of
2169 * the APIC clusters they have been allocated. Only present CPUs have
2170 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2171 * Since clusters are allocated sequentially, count zeros only if
2172 * they are bounded by ones.
2176 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2177 if (test_bit(i
, clustermap
)) {
2178 clusters
+= 1 + zeros
;
2184 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2185 * not guaranteed to be synced between boards
2187 if (is_vsmp_box() && clusters
> 1)
2191 * If clusters > 2, then should be multi-chassis.
2192 * May have to revisit this when multi-core + hyperthreaded CPUs come
2193 * out, but AFAIK this will work even for them.
2195 return (clusters
> 2);
2200 * APIC command line parameters
2202 static int __init
setup_disableapic(char *arg
)
2205 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2208 early_param("disableapic", setup_disableapic
);
2210 /* same as disableapic, for compatibility */
2211 static int __init
setup_nolapic(char *arg
)
2213 return setup_disableapic(arg
);
2215 early_param("nolapic", setup_nolapic
);
2217 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2219 local_apic_timer_c2_ok
= 1;
2222 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2224 static int __init
parse_disable_apic_timer(char *arg
)
2226 disable_apic_timer
= 1;
2229 early_param("noapictimer", parse_disable_apic_timer
);
2231 static int __init
parse_nolapic_timer(char *arg
)
2233 disable_apic_timer
= 1;
2236 early_param("nolapic_timer", parse_nolapic_timer
);
2238 static int __init
apic_set_verbosity(char *arg
)
2241 #ifdef CONFIG_X86_64
2242 skip_ioapic_setup
= 0;
2248 if (strcmp("debug", arg
) == 0)
2249 apic_verbosity
= APIC_DEBUG
;
2250 else if (strcmp("verbose", arg
) == 0)
2251 apic_verbosity
= APIC_VERBOSE
;
2253 pr_warning("APIC Verbosity level %s not recognised"
2254 " use apic=verbose or apic=debug\n", arg
);
2260 early_param("apic", apic_set_verbosity
);
2262 static int __init
lapic_insert_resource(void)
2267 /* Put local APIC into the resource map. */
2268 lapic_resource
.start
= apic_phys
;
2269 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2270 insert_resource(&iomem_resource
, &lapic_resource
);
2276 * need call insert after e820_reserve_resources()
2277 * that is using request_resource
2279 late_initcall(lapic_insert_resource
);