2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
57 #include <asm/hypervisor.h>
59 unsigned int num_processors
;
61 unsigned disabled_cpus
;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid
= -1U;
65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid
);
68 * The highest APIC ID seen during enumeration.
70 static unsigned int max_physical_apicid
;
73 * Bitmask of physically existing CPUs:
75 physid_mask_t phys_cpu_present_map
;
78 * Processor to be disabled specified by kernel parameter
79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
80 * avoid undefined behaviour caused by sending INIT from AP to BSP.
82 static unsigned int disabled_cpu_apicid __read_mostly
= BAD_APICID
;
85 * This variable controls which CPUs receive external NMIs. By default,
86 * external NMIs are delivered only to the BSP.
88 static int apic_extnmi
= APIC_EXTNMI_BSP
;
91 * Map cpu index to physical APIC ID
93 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_cpu_to_apicid
, BAD_APICID
);
94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
95 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32
, x86_cpu_to_acpiid
, U32_MAX
);
96 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
97 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
98 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid
);
103 * On x86_32, the mapping between cpu and logical apicid may vary
104 * depending on apic in use. The following early percpu variable is
105 * used for the mapping. This is where the behaviors of x86_64 and 32
106 * actually diverge. Let's keep it ugly for now.
108 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
110 /* Local APIC was disabled by the BIOS and enabled by the kernel */
111 static int enabled_via_apicbase
;
114 * Handle interrupt mode configuration register (IMCR).
115 * This register controls whether the interrupt signals
116 * that reach the BSP come from the master PIC or from the
117 * local APIC. Before entering Symmetric I/O Mode, either
118 * the BIOS or the operating system must switch out of
119 * PIC Mode by changing the IMCR.
121 static inline void imcr_pic_to_apic(void)
123 /* select IMCR register */
125 /* NMI and 8259 INTR go through APIC */
129 static inline void imcr_apic_to_pic(void)
131 /* select IMCR register */
133 /* NMI and 8259 INTR go directly to BSP */
139 * Knob to control our willingness to enable the local APIC.
143 static int force_enable_local_apic __initdata
;
146 * APIC command line parameters
148 static int __init
parse_lapic(char *arg
)
150 if (config_enabled(CONFIG_X86_32
) && !arg
)
151 force_enable_local_apic
= 1;
152 else if (arg
&& !strncmp(arg
, "notscdeadline", 13))
153 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
156 early_param("lapic", parse_lapic
);
159 static int apic_calibrate_pmtmr __initdata
;
160 static __init
int setup_apicpmtimer(char *s
)
162 apic_calibrate_pmtmr
= 1;
166 __setup("apicpmtimer", setup_apicpmtimer
);
169 unsigned long mp_lapic_addr
;
171 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
172 static int disable_apic_timer __initdata
;
173 /* Local APIC timer works in C2 */
174 int local_apic_timer_c2_ok
;
175 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
177 int first_system_vector
= FIRST_SYSTEM_VECTOR
;
180 * Debug level, exported for io_apic.c
182 unsigned int apic_verbosity
;
186 /* Have we found an MP table */
187 int smp_found_config
;
189 static struct resource lapic_resource
= {
190 .name
= "Local APIC",
191 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
194 unsigned int lapic_timer_frequency
= 0;
196 static void apic_pm_activate(void);
198 static unsigned long apic_phys
;
201 * Get the LAPIC version
203 static inline int lapic_get_version(void)
205 return GET_APIC_VERSION(apic_read(APIC_LVR
));
209 * Check, if the APIC is integrated or a separate chip
211 static inline int lapic_is_integrated(void)
216 return APIC_INTEGRATED(lapic_get_version());
221 * Check, whether this is a modern or a first generation APIC
223 static int modern_apic(void)
225 /* AMD systems use old APIC versions, so check the CPU */
226 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
227 boot_cpu_data
.x86
>= 0xf)
229 return lapic_get_version() >= 0x14;
233 * right after this call apic become NOOP driven
234 * so apic->write/read doesn't do anything
236 static void __init
apic_disable(void)
238 pr_info("APIC: switched to apic NOOP\n");
242 void native_apic_wait_icr_idle(void)
244 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
248 u32
native_safe_apic_wait_icr_idle(void)
255 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
258 inc_irq_stat(icr_read_retry_count
);
260 } while (timeout
++ < 1000);
265 void native_apic_icr_write(u32 low
, u32 id
)
269 local_irq_save(flags
);
270 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
271 apic_write(APIC_ICR
, low
);
272 local_irq_restore(flags
);
275 u64
native_apic_icr_read(void)
279 icr2
= apic_read(APIC_ICR2
);
280 icr1
= apic_read(APIC_ICR
);
282 return icr1
| ((u64
)icr2
<< 32);
287 * get_physical_broadcast - Get number of physical broadcast IDs
289 int get_physical_broadcast(void)
291 return modern_apic() ? 0xff : 0xf;
296 * lapic_get_maxlvt - get the maximum number of local vector table entries
298 int lapic_get_maxlvt(void)
302 v
= apic_read(APIC_LVR
);
304 * - we always have APIC integrated on 64bit mode
305 * - 82489DXs do not report # of LVT entries
307 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
315 #define APIC_DIVISOR 16
316 #define TSC_DIVISOR 32
319 * This function sets up the local APIC timer, with a timeout of
320 * 'clocks' APIC bus clock. During calibration we actually call
321 * this function twice on the boot CPU, once with a bogus timeout
322 * value, second time for real. The other (noncalibrating) CPUs
323 * call this function only once, with the real, calibrated value.
325 * We do reads before writes even if unnecessary, to get around the
326 * P5 APIC double write bug.
328 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
330 unsigned int lvtt_value
, tmp_value
;
332 lvtt_value
= LOCAL_TIMER_VECTOR
;
334 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
335 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
336 lvtt_value
|= APIC_LVT_TIMER_TSCDEADLINE
;
338 if (!lapic_is_integrated())
339 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
342 lvtt_value
|= APIC_LVT_MASKED
;
344 apic_write(APIC_LVTT
, lvtt_value
);
346 if (lvtt_value
& APIC_LVT_TIMER_TSCDEADLINE
) {
348 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
349 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
350 * According to Intel, MFENCE can do the serialization here.
352 asm volatile("mfence" : : : "memory");
354 printk_once(KERN_DEBUG
"TSC deadline timer enabled\n");
361 tmp_value
= apic_read(APIC_TDCR
);
362 apic_write(APIC_TDCR
,
363 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
367 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
371 * Setup extended LVT, AMD specific
373 * Software should use the LVT offsets the BIOS provides. The offsets
374 * are determined by the subsystems using it like those for MCE
375 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
376 * are supported. Beginning with family 10h at least 4 offsets are
379 * Since the offsets must be consistent for all cores, we keep track
380 * of the LVT offsets in software and reserve the offset for the same
381 * vector also to be used on other cores. An offset is freed by
382 * setting the entry to APIC_EILVT_MASKED.
384 * If the BIOS is right, there should be no conflicts. Otherwise a
385 * "[Firmware Bug]: ..." error message is generated. However, if
386 * software does not properly determines the offsets, it is not
387 * necessarily a BIOS bug.
390 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
392 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
394 return (old
& APIC_EILVT_MASKED
)
395 || (new == APIC_EILVT_MASKED
)
396 || ((new & ~APIC_EILVT_MASKED
) == old
);
399 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
401 unsigned int rsvd
, vector
;
403 if (offset
>= APIC_EILVT_NR_MAX
)
406 rsvd
= atomic_read(&eilvt_offsets
[offset
]);
408 vector
= rsvd
& ~APIC_EILVT_MASKED
; /* 0: unassigned */
409 if (vector
&& !eilvt_entry_is_changeable(vector
, new))
410 /* may not change if vectors are different */
412 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
413 } while (rsvd
!= new);
415 rsvd
&= ~APIC_EILVT_MASKED
;
416 if (rsvd
&& rsvd
!= vector
)
417 pr_info("LVT offset %d assigned for vector 0x%02x\n",
424 * If mask=1, the LVT entry does not generate interrupts while mask=0
425 * enables the vector. See also the BKDGs. Must be called with
426 * preemption disabled.
429 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
431 unsigned long reg
= APIC_EILVTn(offset
);
432 unsigned int new, old
, reserved
;
434 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
435 old
= apic_read(reg
);
436 reserved
= reserve_eilvt_offset(offset
, new);
438 if (reserved
!= new) {
439 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
440 "vector 0x%x, but the register is already in use for "
441 "vector 0x%x on another cpu\n",
442 smp_processor_id(), reg
, offset
, new, reserved
);
446 if (!eilvt_entry_is_changeable(old
, new)) {
447 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
448 "vector 0x%x, but the register is already in use for "
449 "vector 0x%x on this cpu\n",
450 smp_processor_id(), reg
, offset
, new, old
);
454 apic_write(reg
, new);
458 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
461 * Program the next event, relative to now
463 static int lapic_next_event(unsigned long delta
,
464 struct clock_event_device
*evt
)
466 apic_write(APIC_TMICT
, delta
);
470 static int lapic_next_deadline(unsigned long delta
,
471 struct clock_event_device
*evt
)
476 wrmsrl(MSR_IA32_TSC_DEADLINE
, tsc
+ (((u64
) delta
) * TSC_DIVISOR
));
480 static int lapic_timer_shutdown(struct clock_event_device
*evt
)
484 /* Lapic used as dummy for broadcast ? */
485 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
488 v
= apic_read(APIC_LVTT
);
489 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
490 apic_write(APIC_LVTT
, v
);
491 apic_write(APIC_TMICT
, 0);
496 lapic_timer_set_periodic_oneshot(struct clock_event_device
*evt
, bool oneshot
)
498 /* Lapic used as dummy for broadcast ? */
499 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
502 __setup_APIC_LVTT(lapic_timer_frequency
, oneshot
, 1);
506 static int lapic_timer_set_periodic(struct clock_event_device
*evt
)
508 return lapic_timer_set_periodic_oneshot(evt
, false);
511 static int lapic_timer_set_oneshot(struct clock_event_device
*evt
)
513 return lapic_timer_set_periodic_oneshot(evt
, true);
517 * Local APIC timer broadcast function
519 static void lapic_timer_broadcast(const struct cpumask
*mask
)
522 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
528 * The local apic timer can be used for any function which is CPU local.
530 static struct clock_event_device lapic_clockevent
= {
532 .features
= CLOCK_EVT_FEAT_PERIODIC
|
533 CLOCK_EVT_FEAT_ONESHOT
| CLOCK_EVT_FEAT_C3STOP
534 | CLOCK_EVT_FEAT_DUMMY
,
536 .set_state_shutdown
= lapic_timer_shutdown
,
537 .set_state_periodic
= lapic_timer_set_periodic
,
538 .set_state_oneshot
= lapic_timer_set_oneshot
,
539 .set_next_event
= lapic_next_event
,
540 .broadcast
= lapic_timer_broadcast
,
544 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
547 * Setup the local APIC timer for this CPU. Copy the initialized values
548 * of the boot CPU and register the clock event in the framework.
550 static void setup_APIC_timer(void)
552 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
554 if (this_cpu_has(X86_FEATURE_ARAT
)) {
555 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
556 /* Make LAPIC timer preferrable over percpu HPET */
557 lapic_clockevent
.rating
= 150;
560 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
561 levt
->cpumask
= cpumask_of(smp_processor_id());
563 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
564 levt
->features
&= ~(CLOCK_EVT_FEAT_PERIODIC
|
565 CLOCK_EVT_FEAT_DUMMY
);
566 levt
->set_next_event
= lapic_next_deadline
;
567 clockevents_config_and_register(levt
,
568 (tsc_khz
/ TSC_DIVISOR
) * 1000,
571 clockevents_register_device(levt
);
575 * In this functions we calibrate APIC bus clocks to the external timer.
577 * We want to do the calibration only once since we want to have local timer
578 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
581 * This was previously done by reading the PIT/HPET and waiting for a wrap
582 * around to find out, that a tick has elapsed. I have a box, where the PIT
583 * readout is broken, so it never gets out of the wait loop again. This was
584 * also reported by others.
586 * Monitoring the jiffies value is inaccurate and the clockevents
587 * infrastructure allows us to do a simple substitution of the interrupt
590 * The calibration routine also uses the pm_timer when possible, as the PIT
591 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
592 * back to normal later in the boot process).
595 #define LAPIC_CAL_LOOPS (HZ/10)
597 static __initdata
int lapic_cal_loops
= -1;
598 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
599 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
600 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
601 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
604 * Temporary interrupt handler.
606 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
608 unsigned long long tsc
= 0;
609 long tapic
= apic_read(APIC_TMCCT
);
610 unsigned long pm
= acpi_pm_read_early();
612 if (boot_cpu_has(X86_FEATURE_TSC
))
615 switch (lapic_cal_loops
++) {
617 lapic_cal_t1
= tapic
;
618 lapic_cal_tsc1
= tsc
;
620 lapic_cal_j1
= jiffies
;
623 case LAPIC_CAL_LOOPS
:
624 lapic_cal_t2
= tapic
;
625 lapic_cal_tsc2
= tsc
;
626 if (pm
< lapic_cal_pm1
)
627 pm
+= ACPI_PM_OVRRUN
;
629 lapic_cal_j2
= jiffies
;
635 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
637 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
638 const long pm_thresh
= pm_100ms
/ 100;
642 #ifndef CONFIG_X86_PM_TIMER
646 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
648 /* Check, if the PM timer is available */
652 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
654 if (deltapm
> (pm_100ms
- pm_thresh
) &&
655 deltapm
< (pm_100ms
+ pm_thresh
)) {
656 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
660 res
= (((u64
)deltapm
) * mult
) >> 22;
661 do_div(res
, 1000000);
662 pr_warning("APIC calibration not consistent "
663 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
665 /* Correct the lapic counter value */
666 res
= (((u64
)(*delta
)) * pm_100ms
);
667 do_div(res
, deltapm
);
668 pr_info("APIC delta adjusted to PM-Timer: "
669 "%lu (%ld)\n", (unsigned long)res
, *delta
);
672 /* Correct the tsc counter value */
673 if (boot_cpu_has(X86_FEATURE_TSC
)) {
674 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
675 do_div(res
, deltapm
);
676 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
677 "PM-Timer: %lu (%ld)\n",
678 (unsigned long)res
, *deltatsc
);
679 *deltatsc
= (long)res
;
685 static int __init
calibrate_APIC_clock(void)
687 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
688 void (*real_handler
)(struct clock_event_device
*dev
);
689 unsigned long deltaj
;
690 long delta
, deltatsc
;
691 int pm_referenced
= 0;
694 * check if lapic timer has already been calibrated by platform
695 * specific routine, such as tsc calibration code. if so, we just fill
696 * in the clockevent structure and return.
699 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
701 } else if (lapic_timer_frequency
) {
702 apic_printk(APIC_VERBOSE
, "lapic timer already calibrated %d\n",
703 lapic_timer_frequency
);
704 lapic_clockevent
.mult
= div_sc(lapic_timer_frequency
/APIC_DIVISOR
,
705 TICK_NSEC
, lapic_clockevent
.shift
);
706 lapic_clockevent
.max_delta_ns
=
707 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
708 lapic_clockevent
.min_delta_ns
=
709 clockevent_delta2ns(0xF, &lapic_clockevent
);
710 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
714 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
715 "calibrating APIC timer ...\n");
719 /* Replace the global interrupt handler */
720 real_handler
= global_clock_event
->event_handler
;
721 global_clock_event
->event_handler
= lapic_cal_handler
;
724 * Setup the APIC counter to maximum. There is no way the lapic
725 * can underflow in the 100ms detection time frame
727 __setup_APIC_LVTT(0xffffffff, 0, 0);
729 /* Let the interrupts run */
732 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
737 /* Restore the real event handler */
738 global_clock_event
->event_handler
= real_handler
;
740 /* Build delta t1-t2 as apic timer counts down */
741 delta
= lapic_cal_t1
- lapic_cal_t2
;
742 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
744 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
746 /* we trust the PM based calibration if possible */
747 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
750 /* Calculate the scaled math multiplication factor */
751 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
752 lapic_clockevent
.shift
);
753 lapic_clockevent
.max_delta_ns
=
754 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
755 lapic_clockevent
.min_delta_ns
=
756 clockevent_delta2ns(0xF, &lapic_clockevent
);
758 lapic_timer_frequency
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
760 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
761 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
762 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
763 lapic_timer_frequency
);
765 if (boot_cpu_has(X86_FEATURE_TSC
)) {
766 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
768 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
769 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
772 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
774 lapic_timer_frequency
/ (1000000 / HZ
),
775 lapic_timer_frequency
% (1000000 / HZ
));
778 * Do a sanity check on the APIC calibration result
780 if (lapic_timer_frequency
< (1000000 / HZ
)) {
782 pr_warning("APIC frequency too slow, disabling apic timer\n");
786 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
789 * PM timer calibration failed or not turned on
790 * so lets try APIC timer based calibration
792 if (!pm_referenced
) {
793 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
796 * Setup the apic timer manually
798 levt
->event_handler
= lapic_cal_handler
;
799 lapic_timer_set_periodic(levt
);
800 lapic_cal_loops
= -1;
802 /* Let the interrupts run */
805 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
808 /* Stop the lapic timer */
810 lapic_timer_shutdown(levt
);
813 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
814 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
816 /* Check, if the jiffies result is consistent */
817 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
818 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
820 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
824 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
825 pr_warning("APIC timer disabled due to verification failure\n");
833 * Setup the boot APIC
835 * Calibrate and verify the result.
837 void __init
setup_boot_APIC_clock(void)
840 * The local apic timer can be disabled via the kernel
841 * commandline or from the CPU detection code. Register the lapic
842 * timer as a dummy clock event source on SMP systems, so the
843 * broadcast mechanism is used. On UP systems simply ignore it.
845 if (disable_apic_timer
) {
846 pr_info("Disabling APIC timer\n");
847 /* No broadcast on UP ! */
848 if (num_possible_cpus() > 1) {
849 lapic_clockevent
.mult
= 1;
855 if (calibrate_APIC_clock()) {
856 /* No broadcast on UP ! */
857 if (num_possible_cpus() > 1)
863 * If nmi_watchdog is set to IO_APIC, we need the
864 * PIT/HPET going. Otherwise register lapic as a dummy
867 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
869 /* Setup the lapic or request the broadcast */
873 void setup_secondary_APIC_clock(void)
879 * The guts of the apic timer interrupt
881 static void local_apic_timer_interrupt(void)
883 int cpu
= smp_processor_id();
884 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
887 * Normally we should not be here till LAPIC has been initialized but
888 * in some cases like kdump, its possible that there is a pending LAPIC
889 * timer interrupt from previous kernel's context and is delivered in
890 * new kernel the moment interrupts are enabled.
892 * Interrupts are enabled early and LAPIC is setup much later, hence
893 * its possible that when we get here evt->event_handler is NULL.
894 * Check for event_handler being NULL and discard the interrupt as
897 if (!evt
->event_handler
) {
898 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
900 lapic_timer_shutdown(evt
);
905 * the NMI deadlock-detector uses this.
907 inc_irq_stat(apic_timer_irqs
);
909 evt
->event_handler(evt
);
913 * Local APIC timer interrupt. This is the most natural way for doing
914 * local interrupts, but local timer interrupts can be emulated by
915 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
917 * [ if a single-CPU system runs an SMP kernel then we call the local
918 * interrupt as well. Thus we cannot inline the local irq ... ]
920 __visible
void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
922 struct pt_regs
*old_regs
= set_irq_regs(regs
);
925 * NOTE! We'd better ACK the irq immediately,
926 * because timer handling can be slow.
928 * update_process_times() expects us to have done irq_enter().
929 * Besides, if we don't timer interrupts ignore the global
930 * interrupt lock, which is the WrongThing (tm) to do.
933 local_apic_timer_interrupt();
936 set_irq_regs(old_regs
);
939 __visible
void __irq_entry
smp_trace_apic_timer_interrupt(struct pt_regs
*regs
)
941 struct pt_regs
*old_regs
= set_irq_regs(regs
);
944 * NOTE! We'd better ACK the irq immediately,
945 * because timer handling can be slow.
947 * update_process_times() expects us to have done irq_enter().
948 * Besides, if we don't timer interrupts ignore the global
949 * interrupt lock, which is the WrongThing (tm) to do.
952 trace_local_timer_entry(LOCAL_TIMER_VECTOR
);
953 local_apic_timer_interrupt();
954 trace_local_timer_exit(LOCAL_TIMER_VECTOR
);
957 set_irq_regs(old_regs
);
960 int setup_profiling_timer(unsigned int multiplier
)
966 * Local APIC start and shutdown
970 * clear_local_APIC - shutdown the local APIC
972 * This is called, when a CPU is disabled and before rebooting, so the state of
973 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
974 * leftovers during boot.
976 void clear_local_APIC(void)
981 /* APIC hasn't been mapped yet */
982 if (!x2apic_mode
&& !apic_phys
)
985 maxlvt
= lapic_get_maxlvt();
987 * Masking an LVT entry can trigger a local APIC error
988 * if the vector is zero. Mask LVTERR first to prevent this.
991 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
992 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
995 * Careful: we have to set masks only first to deassert
996 * any level-triggered sources.
998 v
= apic_read(APIC_LVTT
);
999 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1000 v
= apic_read(APIC_LVT0
);
1001 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1002 v
= apic_read(APIC_LVT1
);
1003 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
1005 v
= apic_read(APIC_LVTPC
);
1006 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
1009 /* lets not touch this if we didn't frob it */
1010 #ifdef CONFIG_X86_THERMAL_VECTOR
1012 v
= apic_read(APIC_LVTTHMR
);
1013 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
1016 #ifdef CONFIG_X86_MCE_INTEL
1018 v
= apic_read(APIC_LVTCMCI
);
1019 if (!(v
& APIC_LVT_MASKED
))
1020 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
1025 * Clean APIC state for other OSs:
1027 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
1028 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1029 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
1031 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
1033 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
1035 /* Integrated APIC (!82489DX) ? */
1036 if (lapic_is_integrated()) {
1038 /* Clear ESR due to Pentium errata 3AP and 11AP */
1039 apic_write(APIC_ESR
, 0);
1040 apic_read(APIC_ESR
);
1045 * disable_local_APIC - clear and disable the local APIC
1047 void disable_local_APIC(void)
1051 /* APIC hasn't been mapped yet */
1052 if (!x2apic_mode
&& !apic_phys
)
1058 * Disable APIC (implies clearing of registers
1061 value
= apic_read(APIC_SPIV
);
1062 value
&= ~APIC_SPIV_APIC_ENABLED
;
1063 apic_write(APIC_SPIV
, value
);
1065 #ifdef CONFIG_X86_32
1067 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1068 * restore the disabled state.
1070 if (enabled_via_apicbase
) {
1073 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1074 l
&= ~MSR_IA32_APICBASE_ENABLE
;
1075 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1081 * If Linux enabled the LAPIC against the BIOS default disable it down before
1082 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1083 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1084 * for the case where Linux didn't enable the LAPIC.
1086 void lapic_shutdown(void)
1088 unsigned long flags
;
1090 if (!boot_cpu_has(X86_FEATURE_APIC
) && !apic_from_smp_config())
1093 local_irq_save(flags
);
1095 #ifdef CONFIG_X86_32
1096 if (!enabled_via_apicbase
)
1100 disable_local_APIC();
1103 local_irq_restore(flags
);
1107 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1109 void __init
sync_Arb_IDs(void)
1112 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1115 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1121 apic_wait_icr_idle();
1123 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1124 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1125 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1129 * An initial setup of the virtual wire mode.
1131 void __init
init_bsp_APIC(void)
1136 * Don't do the setup now if we have a SMP BIOS as the
1137 * through-I/O-APIC virtual wire mode might be active.
1139 if (smp_found_config
|| !boot_cpu_has(X86_FEATURE_APIC
))
1143 * Do not trust the local APIC being empty at bootup.
1150 value
= apic_read(APIC_SPIV
);
1151 value
&= ~APIC_VECTOR_MASK
;
1152 value
|= APIC_SPIV_APIC_ENABLED
;
1154 #ifdef CONFIG_X86_32
1155 /* This bit is reserved on P4/Xeon and should be cleared */
1156 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1157 (boot_cpu_data
.x86
== 15))
1158 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1161 value
|= APIC_SPIV_FOCUS_DISABLED
;
1162 value
|= SPURIOUS_APIC_VECTOR
;
1163 apic_write(APIC_SPIV
, value
);
1166 * Set up the virtual wire mode.
1168 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1169 value
= APIC_DM_NMI
;
1170 if (!lapic_is_integrated()) /* 82489DX */
1171 value
|= APIC_LVT_LEVEL_TRIGGER
;
1172 if (apic_extnmi
== APIC_EXTNMI_NONE
)
1173 value
|= APIC_LVT_MASKED
;
1174 apic_write(APIC_LVT1
, value
);
1177 static void lapic_setup_esr(void)
1179 unsigned int oldvalue
, value
, maxlvt
;
1181 if (!lapic_is_integrated()) {
1182 pr_info("No ESR for 82489DX.\n");
1186 if (apic
->disable_esr
) {
1188 * Something untraceable is creating bad interrupts on
1189 * secondary quads ... for the moment, just leave the
1190 * ESR disabled - we can't do anything useful with the
1191 * errors anyway - mbligh
1193 pr_info("Leaving ESR disabled.\n");
1197 maxlvt
= lapic_get_maxlvt();
1198 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1199 apic_write(APIC_ESR
, 0);
1200 oldvalue
= apic_read(APIC_ESR
);
1202 /* enables sending errors */
1203 value
= ERROR_APIC_VECTOR
;
1204 apic_write(APIC_LVTERR
, value
);
1207 * spec says clear errors after enabling vector.
1210 apic_write(APIC_ESR
, 0);
1211 value
= apic_read(APIC_ESR
);
1212 if (value
!= oldvalue
)
1213 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1214 "vector: 0x%08x after: 0x%08x\n",
1219 * setup_local_APIC - setup the local APIC
1221 * Used to setup local APIC while initializing BSP or bringin up APs.
1222 * Always called with preemption disabled.
1224 void setup_local_APIC(void)
1226 int cpu
= smp_processor_id();
1227 unsigned int value
, queued
;
1228 int i
, j
, acked
= 0;
1229 unsigned long long tsc
= 0, ntsc
;
1230 long long max_loops
= cpu_khz
? cpu_khz
: 1000000;
1232 if (boot_cpu_has(X86_FEATURE_TSC
))
1236 disable_ioapic_support();
1240 #ifdef CONFIG_X86_32
1241 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1242 if (lapic_is_integrated() && apic
->disable_esr
) {
1243 apic_write(APIC_ESR
, 0);
1244 apic_write(APIC_ESR
, 0);
1245 apic_write(APIC_ESR
, 0);
1246 apic_write(APIC_ESR
, 0);
1249 perf_events_lapic_init();
1252 * Double-check whether this APIC is really registered.
1253 * This is meaningless in clustered apic mode, so we skip it.
1255 BUG_ON(!apic
->apic_id_registered());
1258 * Intel recommends to set DFR, LDR and TPR before enabling
1259 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1260 * document number 292116). So here it goes...
1262 apic
->init_apic_ldr();
1264 #ifdef CONFIG_X86_32
1266 * APIC LDR is initialized. If logical_apicid mapping was
1267 * initialized during get_smp_config(), make sure it matches the
1270 i
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1271 WARN_ON(i
!= BAD_APICID
&& i
!= logical_smp_processor_id());
1272 /* always use the value from LDR */
1273 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1274 logical_smp_processor_id();
1278 * Set Task Priority to 'accept all'. We never change this
1281 value
= apic_read(APIC_TASKPRI
);
1282 value
&= ~APIC_TPRI_MASK
;
1283 apic_write(APIC_TASKPRI
, value
);
1286 * After a crash, we no longer service the interrupts and a pending
1287 * interrupt from previous kernel might still have ISR bit set.
1289 * Most probably by now CPU has serviced that pending interrupt and
1290 * it might not have done the ack_APIC_irq() because it thought,
1291 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1292 * does not clear the ISR bit and cpu thinks it has already serivced
1293 * the interrupt. Hence a vector might get locked. It was noticed
1294 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1298 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1299 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1301 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1302 value
= apic_read(APIC_ISR
+ i
*0x10);
1303 for (j
= 31; j
>= 0; j
--) {
1304 if (value
& (1<<j
)) {
1311 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1316 if (boot_cpu_has(X86_FEATURE_TSC
) && cpu_khz
) {
1318 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1322 } while (queued
&& max_loops
> 0);
1323 WARN_ON(max_loops
<= 0);
1326 * Now that we are all set up, enable the APIC
1328 value
= apic_read(APIC_SPIV
);
1329 value
&= ~APIC_VECTOR_MASK
;
1333 value
|= APIC_SPIV_APIC_ENABLED
;
1335 #ifdef CONFIG_X86_32
1337 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1338 * certain networking cards. If high frequency interrupts are
1339 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1340 * entry is masked/unmasked at a high rate as well then sooner or
1341 * later IOAPIC line gets 'stuck', no more interrupts are received
1342 * from the device. If focus CPU is disabled then the hang goes
1345 * [ This bug can be reproduced easily with a level-triggered
1346 * PCI Ne2000 networking cards and PII/PIII processors, dual
1350 * Actually disabling the focus CPU check just makes the hang less
1351 * frequent as it makes the interrupt distributon model be more
1352 * like LRU than MRU (the short-term load is more even across CPUs).
1353 * See also the comment in end_level_ioapic_irq(). --macro
1357 * - enable focus processor (bit==0)
1358 * - 64bit mode always use processor focus
1359 * so no need to set it
1361 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1365 * Set spurious IRQ vector
1367 value
|= SPURIOUS_APIC_VECTOR
;
1368 apic_write(APIC_SPIV
, value
);
1371 * Set up LVT0, LVT1:
1373 * set up through-local-APIC on the BP's LINT0. This is not
1374 * strictly necessary in pure symmetric-IO mode, but sometimes
1375 * we delegate interrupts to the 8259A.
1378 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1380 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1381 if (!cpu
&& (pic_mode
|| !value
)) {
1382 value
= APIC_DM_EXTINT
;
1383 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1385 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1386 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1388 apic_write(APIC_LVT0
, value
);
1391 * Only the BSP sees the LINT1 NMI signal by default. This can be
1392 * modified by apic_extnmi= boot option.
1394 if ((!cpu
&& apic_extnmi
!= APIC_EXTNMI_NONE
) ||
1395 apic_extnmi
== APIC_EXTNMI_ALL
)
1396 value
= APIC_DM_NMI
;
1398 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1399 if (!lapic_is_integrated()) /* 82489DX */
1400 value
|= APIC_LVT_LEVEL_TRIGGER
;
1401 apic_write(APIC_LVT1
, value
);
1403 #ifdef CONFIG_X86_MCE_INTEL
1404 /* Recheck CMCI information after local APIC is up on CPU #0 */
1410 static void end_local_APIC_setup(void)
1414 #ifdef CONFIG_X86_32
1417 /* Disable the local apic timer */
1418 value
= apic_read(APIC_LVTT
);
1419 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1420 apic_write(APIC_LVTT
, value
);
1428 * APIC setup function for application processors. Called from smpboot.c
1430 void apic_ap_setup(void)
1433 end_local_APIC_setup();
1436 #ifdef CONFIG_X86_X2APIC
1444 static int x2apic_state
;
1446 static void __x2apic_disable(void)
1450 if (!boot_cpu_has(X86_FEATURE_APIC
))
1453 rdmsrl(MSR_IA32_APICBASE
, msr
);
1454 if (!(msr
& X2APIC_ENABLE
))
1456 /* Disable xapic and x2apic first and then reenable xapic mode */
1457 wrmsrl(MSR_IA32_APICBASE
, msr
& ~(X2APIC_ENABLE
| XAPIC_ENABLE
));
1458 wrmsrl(MSR_IA32_APICBASE
, msr
& ~X2APIC_ENABLE
);
1459 printk_once(KERN_INFO
"x2apic disabled\n");
1462 static void __x2apic_enable(void)
1466 rdmsrl(MSR_IA32_APICBASE
, msr
);
1467 if (msr
& X2APIC_ENABLE
)
1469 wrmsrl(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
);
1470 printk_once(KERN_INFO
"x2apic enabled\n");
1473 static int __init
setup_nox2apic(char *str
)
1475 if (x2apic_enabled()) {
1476 int apicid
= native_apic_msr_read(APIC_ID
);
1478 if (apicid
>= 255) {
1479 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1483 pr_warning("x2apic already enabled.\n");
1486 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
1487 x2apic_state
= X2APIC_DISABLED
;
1491 early_param("nox2apic", setup_nox2apic
);
1493 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1494 void x2apic_setup(void)
1497 * If x2apic is not in ON state, disable it if already enabled
1500 if (x2apic_state
!= X2APIC_ON
) {
1507 static __init
void x2apic_disable(void)
1509 u32 x2apic_id
, state
= x2apic_state
;
1512 x2apic_state
= X2APIC_DISABLED
;
1514 if (state
!= X2APIC_ON
)
1517 x2apic_id
= read_apic_id();
1518 if (x2apic_id
>= 255)
1519 panic("Cannot disable x2apic, id: %08x\n", x2apic_id
);
1522 register_lapic_address(mp_lapic_addr
);
1525 static __init
void x2apic_enable(void)
1527 if (x2apic_state
!= X2APIC_OFF
)
1531 x2apic_state
= X2APIC_ON
;
1535 static __init
void try_to_enable_x2apic(int remap_mode
)
1537 if (x2apic_state
== X2APIC_DISABLED
)
1540 if (remap_mode
!= IRQ_REMAP_X2APIC_MODE
) {
1541 /* IR is required if there is APIC ID > 255 even when running
1544 if (max_physical_apicid
> 255 ||
1545 !hypervisor_x2apic_available()) {
1546 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1552 * without IR all CPUs can be addressed by IOAPIC/MSI
1553 * only in physical mode
1560 void __init
check_x2apic(void)
1562 if (x2apic_enabled()) {
1563 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1565 x2apic_state
= X2APIC_ON
;
1566 } else if (!boot_cpu_has(X86_FEATURE_X2APIC
)) {
1567 x2apic_state
= X2APIC_DISABLED
;
1570 #else /* CONFIG_X86_X2APIC */
1571 static int __init
validate_x2apic(void)
1573 if (!apic_is_x2apic_enabled())
1576 * Checkme: Can we simply turn off x2apic here instead of panic?
1578 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1580 early_initcall(validate_x2apic
);
1582 static inline void try_to_enable_x2apic(int remap_mode
) { }
1583 static inline void __x2apic_enable(void) { }
1584 #endif /* !CONFIG_X86_X2APIC */
1586 static int __init
try_to_enable_IR(void)
1588 #ifdef CONFIG_X86_IO_APIC
1589 if (!x2apic_enabled() && skip_ioapic_setup
) {
1590 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1594 return irq_remapping_enable();
1597 void __init
enable_IR_x2apic(void)
1599 unsigned long flags
;
1602 ir_stat
= irq_remapping_prepare();
1603 if (ir_stat
< 0 && !x2apic_supported())
1606 ret
= save_ioapic_entries();
1608 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1612 local_irq_save(flags
);
1613 legacy_pic
->mask_all();
1614 mask_ioapic_entries();
1616 /* If irq_remapping_prepare() succeeded, try to enable it */
1618 ir_stat
= try_to_enable_IR();
1619 /* ir_stat contains the remap mode or an error code */
1620 try_to_enable_x2apic(ir_stat
);
1623 restore_ioapic_entries();
1624 legacy_pic
->restore_mask();
1625 local_irq_restore(flags
);
1628 #ifdef CONFIG_X86_64
1630 * Detect and enable local APICs on non-SMP boards.
1631 * Original code written by Keir Fraser.
1632 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1633 * not correctly set up (usually the APIC timer won't work etc.)
1635 static int __init
detect_init_APIC(void)
1637 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
1638 pr_info("No local APIC present\n");
1642 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1647 static int __init
apic_verify(void)
1652 * The APIC feature bit should now be enabled
1655 features
= cpuid_edx(1);
1656 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1657 pr_warning("Could not enable APIC!\n");
1660 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1661 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1663 /* The BIOS may have set up the APIC at some other address */
1664 if (boot_cpu_data
.x86
>= 6) {
1665 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1666 if (l
& MSR_IA32_APICBASE_ENABLE
)
1667 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1670 pr_info("Found and enabled local APIC!\n");
1674 int __init
apic_force_enable(unsigned long addr
)
1682 * Some BIOSes disable the local APIC in the APIC_BASE
1683 * MSR. This can only be done in software for Intel P6 or later
1684 * and AMD K7 (Model > 1) or later.
1686 if (boot_cpu_data
.x86
>= 6) {
1687 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1688 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1689 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1690 l
&= ~MSR_IA32_APICBASE_BASE
;
1691 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1692 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1693 enabled_via_apicbase
= 1;
1696 return apic_verify();
1700 * Detect and initialize APIC
1702 static int __init
detect_init_APIC(void)
1704 /* Disabled by kernel option? */
1708 switch (boot_cpu_data
.x86_vendor
) {
1709 case X86_VENDOR_AMD
:
1710 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1711 (boot_cpu_data
.x86
>= 15))
1714 case X86_VENDOR_INTEL
:
1715 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1716 (boot_cpu_data
.x86
== 5 && boot_cpu_has(X86_FEATURE_APIC
)))
1723 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
1725 * Over-ride BIOS and try to enable the local APIC only if
1726 * "lapic" specified.
1728 if (!force_enable_local_apic
) {
1729 pr_info("Local APIC disabled by BIOS -- "
1730 "you can enable it with \"lapic\"\n");
1733 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
1745 pr_info("No local APIC present or hardware disabled\n");
1751 * init_apic_mappings - initialize APIC mappings
1753 void __init
init_apic_mappings(void)
1755 unsigned int new_apicid
;
1758 boot_cpu_physical_apicid
= read_apic_id();
1762 /* If no local APIC can be found return early */
1763 if (!smp_found_config
&& detect_init_APIC()) {
1764 /* lets NOP'ify apic operations */
1765 pr_info("APIC: disable apic facility\n");
1768 apic_phys
= mp_lapic_addr
;
1771 * acpi lapic path already maps that address in
1772 * acpi_register_lapic_address()
1774 if (!acpi_lapic
&& !smp_found_config
)
1775 register_lapic_address(apic_phys
);
1779 * Fetch the APIC ID of the BSP in case we have a
1780 * default configuration (or the MP table is broken).
1782 new_apicid
= read_apic_id();
1783 if (boot_cpu_physical_apicid
!= new_apicid
) {
1784 boot_cpu_physical_apicid
= new_apicid
;
1786 * yeah -- we lie about apic_version
1787 * in case if apic was disabled via boot option
1788 * but it's not a problem for SMP compiled kernel
1789 * since smp_sanity_check is prepared for such a case
1790 * and disable smp mode
1792 apic_version
[new_apicid
] =
1793 GET_APIC_VERSION(apic_read(APIC_LVR
));
1797 void __init
register_lapic_address(unsigned long address
)
1799 mp_lapic_addr
= address
;
1802 set_fixmap_nocache(FIX_APIC_BASE
, address
);
1803 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1804 APIC_BASE
, mp_lapic_addr
);
1806 if (boot_cpu_physical_apicid
== -1U) {
1807 boot_cpu_physical_apicid
= read_apic_id();
1808 apic_version
[boot_cpu_physical_apicid
] =
1809 GET_APIC_VERSION(apic_read(APIC_LVR
));
1813 int apic_version
[MAX_LOCAL_APIC
];
1816 * Local APIC interrupts
1820 * This interrupt should _never_ happen with our APIC/SMP architecture
1822 static void __smp_spurious_interrupt(u8 vector
)
1827 * Check if this really is a spurious interrupt and ACK it
1828 * if it is a vectored one. Just in case...
1829 * Spurious interrupts should not be ACKed.
1831 v
= apic_read(APIC_ISR
+ ((vector
& ~0x1f) >> 1));
1832 if (v
& (1 << (vector
& 0x1f)))
1835 inc_irq_stat(irq_spurious_count
);
1837 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1838 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1839 "should never happen.\n", vector
, smp_processor_id());
1842 __visible
void smp_spurious_interrupt(struct pt_regs
*regs
)
1845 __smp_spurious_interrupt(~regs
->orig_ax
);
1849 __visible
void smp_trace_spurious_interrupt(struct pt_regs
*regs
)
1851 u8 vector
= ~regs
->orig_ax
;
1854 trace_spurious_apic_entry(vector
);
1855 __smp_spurious_interrupt(vector
);
1856 trace_spurious_apic_exit(vector
);
1861 * This interrupt should never happen with our APIC/SMP architecture
1863 static void __smp_error_interrupt(struct pt_regs
*regs
)
1867 static const char * const error_interrupt_reason
[] = {
1868 "Send CS error", /* APIC Error Bit 0 */
1869 "Receive CS error", /* APIC Error Bit 1 */
1870 "Send accept error", /* APIC Error Bit 2 */
1871 "Receive accept error", /* APIC Error Bit 3 */
1872 "Redirectable IPI", /* APIC Error Bit 4 */
1873 "Send illegal vector", /* APIC Error Bit 5 */
1874 "Received illegal vector", /* APIC Error Bit 6 */
1875 "Illegal register address", /* APIC Error Bit 7 */
1878 /* First tickle the hardware, only then report what went on. -- REW */
1879 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1880 apic_write(APIC_ESR
, 0);
1881 v
= apic_read(APIC_ESR
);
1883 atomic_inc(&irq_err_count
);
1885 apic_printk(APIC_DEBUG
, KERN_DEBUG
"APIC error on CPU%d: %02x",
1886 smp_processor_id(), v
);
1891 apic_printk(APIC_DEBUG
, KERN_CONT
" : %s", error_interrupt_reason
[i
]);
1896 apic_printk(APIC_DEBUG
, KERN_CONT
"\n");
1900 __visible
void smp_error_interrupt(struct pt_regs
*regs
)
1903 __smp_error_interrupt(regs
);
1907 __visible
void smp_trace_error_interrupt(struct pt_regs
*regs
)
1910 trace_error_apic_entry(ERROR_APIC_VECTOR
);
1911 __smp_error_interrupt(regs
);
1912 trace_error_apic_exit(ERROR_APIC_VECTOR
);
1917 * connect_bsp_APIC - attach the APIC to the interrupt system
1919 static void __init
connect_bsp_APIC(void)
1921 #ifdef CONFIG_X86_32
1924 * Do not trust the local APIC being empty at bootup.
1928 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1929 * local APIC to INT and NMI lines.
1931 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1932 "enabling APIC mode.\n");
1939 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1940 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1942 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1945 void disconnect_bsp_APIC(int virt_wire_setup
)
1949 #ifdef CONFIG_X86_32
1952 * Put the board back into PIC mode (has an effect only on
1953 * certain older boards). Note that APIC interrupts, including
1954 * IPIs, won't work beyond this point! The only exception are
1957 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1958 "entering PIC mode.\n");
1964 /* Go back to Virtual Wire compatibility mode */
1966 /* For the spurious interrupt use vector F, and enable it */
1967 value
= apic_read(APIC_SPIV
);
1968 value
&= ~APIC_VECTOR_MASK
;
1969 value
|= APIC_SPIV_APIC_ENABLED
;
1971 apic_write(APIC_SPIV
, value
);
1973 if (!virt_wire_setup
) {
1975 * For LVT0 make it edge triggered, active high,
1976 * external and enabled
1978 value
= apic_read(APIC_LVT0
);
1979 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1980 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1981 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1982 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1983 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1984 apic_write(APIC_LVT0
, value
);
1987 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1991 * For LVT1 make it edge triggered, active high,
1994 value
= apic_read(APIC_LVT1
);
1995 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1996 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1997 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1998 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1999 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
2000 apic_write(APIC_LVT1
, value
);
2003 int generic_processor_info(int apicid
, int version
)
2005 int cpu
, max
= nr_cpu_ids
;
2006 bool boot_cpu_detected
= physid_isset(boot_cpu_physical_apicid
,
2007 phys_cpu_present_map
);
2010 * boot_cpu_physical_apicid is designed to have the apicid
2011 * returned by read_apic_id(), i.e, the apicid of the
2012 * currently booting-up processor. However, on some platforms,
2013 * it is temporarily modified by the apicid reported as BSP
2014 * through MP table. Concretely:
2016 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2017 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2019 * This function is executed with the modified
2020 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2021 * parameter doesn't work to disable APs on kdump 2nd kernel.
2023 * Since fixing handling of boot_cpu_physical_apicid requires
2024 * another discussion and tests on each platform, we leave it
2025 * for now and here we use read_apic_id() directly in this
2026 * function, generic_processor_info().
2028 if (disabled_cpu_apicid
!= BAD_APICID
&&
2029 disabled_cpu_apicid
!= read_apic_id() &&
2030 disabled_cpu_apicid
== apicid
) {
2031 int thiscpu
= num_processors
+ disabled_cpus
;
2033 pr_warning("APIC: Disabling requested cpu."
2034 " Processor %d/0x%x ignored.\n",
2042 * If boot cpu has not been detected yet, then only allow upto
2043 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2045 if (!boot_cpu_detected
&& num_processors
>= nr_cpu_ids
- 1 &&
2046 apicid
!= boot_cpu_physical_apicid
) {
2047 int thiscpu
= max
+ disabled_cpus
- 1;
2050 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2051 " reached. Keeping one slot for boot cpu."
2052 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2058 if (num_processors
>= nr_cpu_ids
) {
2059 int thiscpu
= max
+ disabled_cpus
;
2062 "APIC: NR_CPUS/possible_cpus limit of %i reached."
2063 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2070 if (apicid
== boot_cpu_physical_apicid
) {
2072 * x86_bios_cpu_apicid is required to have processors listed
2073 * in same order as logical cpu numbers. Hence the first
2074 * entry is BSP, and so on.
2075 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2080 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
2083 * This can happen on physical hotplug. The sanity check at boot time
2084 * is done from native_smp_prepare_cpus() after num_possible_cpus() is
2087 if (topology_update_package_map(apicid
, cpu
) < 0) {
2088 int thiscpu
= max
+ disabled_cpus
;
2090 pr_warning("APIC: Package limit reached. Processor %d/0x%x ignored.\n",
2099 if (version
== 0x0) {
2100 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2104 apic_version
[apicid
] = version
;
2106 if (version
!= apic_version
[boot_cpu_physical_apicid
]) {
2107 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2108 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
2111 physid_set(apicid
, phys_cpu_present_map
);
2112 if (apicid
> max_physical_apicid
)
2113 max_physical_apicid
= apicid
;
2115 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2116 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
2117 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
2119 #ifdef CONFIG_X86_32
2120 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
2121 apic
->x86_32_early_logical_apicid(cpu
);
2123 set_cpu_possible(cpu
, true);
2124 set_cpu_present(cpu
, true);
2129 int hard_smp_processor_id(void)
2131 return read_apic_id();
2134 void default_init_apic_ldr(void)
2138 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
2139 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
2140 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2141 apic_write(APIC_LDR
, val
);
2144 int default_cpu_mask_to_apicid_and(const struct cpumask
*cpumask
,
2145 const struct cpumask
*andmask
,
2146 unsigned int *apicid
)
2150 for_each_cpu_and(cpu
, cpumask
, andmask
) {
2151 if (cpumask_test_cpu(cpu
, cpu_online_mask
))
2155 if (likely(cpu
< nr_cpu_ids
)) {
2156 *apicid
= per_cpu(x86_cpu_to_apicid
, cpu
);
2164 * Override the generic EOI implementation with an optimized version.
2165 * Only called during early boot when only one CPU is active and with
2166 * interrupts disabled, so we know this does not race with actual APIC driver
2169 void __init
apic_set_eoi_write(void (*eoi_write
)(u32 reg
, u32 v
))
2173 for (drv
= __apicdrivers
; drv
< __apicdrivers_end
; drv
++) {
2174 /* Should happen once for each apic */
2175 WARN_ON((*drv
)->eoi_write
== eoi_write
);
2176 (*drv
)->eoi_write
= eoi_write
;
2180 static void __init
apic_bsp_up_setup(void)
2182 #ifdef CONFIG_X86_64
2183 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
2186 * Hack: In case of kdump, after a crash, kernel might be booting
2187 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2188 * might be zero if read from MP tables. Get it from LAPIC.
2190 # ifdef CONFIG_CRASH_DUMP
2191 boot_cpu_physical_apicid
= read_apic_id();
2194 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
2198 * apic_bsp_setup - Setup function for local apic and io-apic
2199 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2202 * apic_id of BSP APIC
2204 int __init
apic_bsp_setup(bool upmode
)
2210 apic_bsp_up_setup();
2214 id
= apic_read(APIC_LDR
);
2216 id
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
2219 end_local_APIC_setup();
2220 irq_remap_enable_fault_handling();
2222 /* Setup local timer */
2223 x86_init
.timers
.setup_percpu_clockev();
2228 * This initializes the IO-APIC and APIC hardware if this is
2231 int __init
APIC_init_uniprocessor(void)
2234 pr_info("Apic disabled\n");
2237 #ifdef CONFIG_X86_64
2238 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
2240 pr_info("Apic disabled by BIOS\n");
2244 if (!smp_found_config
&& !boot_cpu_has(X86_FEATURE_APIC
))
2248 * Complain if the BIOS pretends there is one.
2250 if (!boot_cpu_has(X86_FEATURE_APIC
) &&
2251 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
2252 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2253 boot_cpu_physical_apicid
);
2258 if (!smp_found_config
)
2259 disable_ioapic_support();
2261 default_setup_apic_routing();
2262 apic_bsp_setup(true);
2266 #ifdef CONFIG_UP_LATE_INIT
2267 void __init
up_late_init(void)
2269 APIC_init_uniprocessor();
2280 * 'active' is true if the local APIC was enabled by us and
2281 * not the BIOS; this signifies that we are also responsible
2282 * for disabling it before entering apm/acpi suspend
2285 /* r/w apic fields */
2286 unsigned int apic_id
;
2287 unsigned int apic_taskpri
;
2288 unsigned int apic_ldr
;
2289 unsigned int apic_dfr
;
2290 unsigned int apic_spiv
;
2291 unsigned int apic_lvtt
;
2292 unsigned int apic_lvtpc
;
2293 unsigned int apic_lvt0
;
2294 unsigned int apic_lvt1
;
2295 unsigned int apic_lvterr
;
2296 unsigned int apic_tmict
;
2297 unsigned int apic_tdcr
;
2298 unsigned int apic_thmr
;
2299 unsigned int apic_cmci
;
2302 static int lapic_suspend(void)
2304 unsigned long flags
;
2307 if (!apic_pm_state
.active
)
2310 maxlvt
= lapic_get_maxlvt();
2312 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2313 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2314 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2315 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2316 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2317 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2319 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2320 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2321 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2322 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2323 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2324 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2325 #ifdef CONFIG_X86_THERMAL_VECTOR
2327 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2329 #ifdef CONFIG_X86_MCE_INTEL
2331 apic_pm_state
.apic_cmci
= apic_read(APIC_LVTCMCI
);
2334 local_irq_save(flags
);
2335 disable_local_APIC();
2337 irq_remapping_disable();
2339 local_irq_restore(flags
);
2343 static void lapic_resume(void)
2346 unsigned long flags
;
2349 if (!apic_pm_state
.active
)
2352 local_irq_save(flags
);
2355 * IO-APIC and PIC have their own resume routines.
2356 * We just mask them here to make sure the interrupt
2357 * subsystem is completely quiet while we enable x2apic
2358 * and interrupt-remapping.
2360 mask_ioapic_entries();
2361 legacy_pic
->mask_all();
2367 * Make sure the APICBASE points to the right address
2369 * FIXME! This will be wrong if we ever support suspend on
2370 * SMP! We'll need to do this as part of the CPU restore!
2372 if (boot_cpu_data
.x86
>= 6) {
2373 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2374 l
&= ~MSR_IA32_APICBASE_BASE
;
2375 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2376 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2380 maxlvt
= lapic_get_maxlvt();
2381 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2382 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2383 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2384 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2385 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2386 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2387 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2388 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2389 #ifdef CONFIG_X86_THERMAL_VECTOR
2391 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2393 #ifdef CONFIG_X86_MCE_INTEL
2395 apic_write(APIC_LVTCMCI
, apic_pm_state
.apic_cmci
);
2398 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2399 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2400 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2401 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2402 apic_write(APIC_ESR
, 0);
2403 apic_read(APIC_ESR
);
2404 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2405 apic_write(APIC_ESR
, 0);
2406 apic_read(APIC_ESR
);
2408 irq_remapping_reenable(x2apic_mode
);
2410 local_irq_restore(flags
);
2414 * This device has no shutdown method - fully functioning local APICs
2415 * are needed on every CPU up until machine_halt/restart/poweroff.
2418 static struct syscore_ops lapic_syscore_ops
= {
2419 .resume
= lapic_resume
,
2420 .suspend
= lapic_suspend
,
2423 static void apic_pm_activate(void)
2425 apic_pm_state
.active
= 1;
2428 static int __init
init_lapic_sysfs(void)
2430 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2431 if (boot_cpu_has(X86_FEATURE_APIC
))
2432 register_syscore_ops(&lapic_syscore_ops
);
2437 /* local apic needs to resume before other devices access its registers. */
2438 core_initcall(init_lapic_sysfs
);
2440 #else /* CONFIG_PM */
2442 static void apic_pm_activate(void) { }
2444 #endif /* CONFIG_PM */
2446 #ifdef CONFIG_X86_64
2448 static int multi_checked
;
2451 static int set_multi(const struct dmi_system_id
*d
)
2455 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2460 static const struct dmi_system_id multi_dmi_table
[] = {
2462 .callback
= set_multi
,
2463 .ident
= "IBM System Summit2",
2465 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2466 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2472 static void dmi_check_multi(void)
2477 dmi_check_system(multi_dmi_table
);
2482 * apic_is_clustered_box() -- Check if we can expect good TSC
2484 * Thus far, the major user of this is IBM's Summit2 series:
2485 * Clustered boxes may have unsynced TSC problems if they are
2487 * Use DMI to check them
2489 int apic_is_clustered_box(void)
2497 * APIC command line parameters
2499 static int __init
setup_disableapic(char *arg
)
2502 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2505 early_param("disableapic", setup_disableapic
);
2507 /* same as disableapic, for compatibility */
2508 static int __init
setup_nolapic(char *arg
)
2510 return setup_disableapic(arg
);
2512 early_param("nolapic", setup_nolapic
);
2514 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2516 local_apic_timer_c2_ok
= 1;
2519 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2521 static int __init
parse_disable_apic_timer(char *arg
)
2523 disable_apic_timer
= 1;
2526 early_param("noapictimer", parse_disable_apic_timer
);
2528 static int __init
parse_nolapic_timer(char *arg
)
2530 disable_apic_timer
= 1;
2533 early_param("nolapic_timer", parse_nolapic_timer
);
2535 static int __init
apic_set_verbosity(char *arg
)
2538 #ifdef CONFIG_X86_64
2539 skip_ioapic_setup
= 0;
2545 if (strcmp("debug", arg
) == 0)
2546 apic_verbosity
= APIC_DEBUG
;
2547 else if (strcmp("verbose", arg
) == 0)
2548 apic_verbosity
= APIC_VERBOSE
;
2550 pr_warning("APIC Verbosity level %s not recognised"
2551 " use apic=verbose or apic=debug\n", arg
);
2557 early_param("apic", apic_set_verbosity
);
2559 static int __init
lapic_insert_resource(void)
2564 /* Put local APIC into the resource map. */
2565 lapic_resource
.start
= apic_phys
;
2566 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2567 insert_resource(&iomem_resource
, &lapic_resource
);
2573 * need call insert after e820_reserve_resources()
2574 * that is using request_resource
2576 late_initcall(lapic_insert_resource
);
2578 static int __init
apic_set_disabled_cpu_apicid(char *arg
)
2580 if (!arg
|| !get_option(&arg
, &disabled_cpu_apicid
))
2585 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid
);
2587 static int __init
apic_set_extnmi(char *arg
)
2592 if (!strncmp("all", arg
, 3))
2593 apic_extnmi
= APIC_EXTNMI_ALL
;
2594 else if (!strncmp("none", arg
, 4))
2595 apic_extnmi
= APIC_EXTNMI_NONE
;
2596 else if (!strncmp("bsp", arg
, 3))
2597 apic_extnmi
= APIC_EXTNMI_BSP
;
2599 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg
);
2605 early_param("apic_extnmi", apic_set_extnmi
);